From patchwork Tue Nov 27 07:42:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 10699829 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0EBE15A7 for ; Tue, 27 Nov 2018 08:10:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B564C2AB44 for ; Tue, 27 Nov 2018 08:10:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A9EF82AB48; Tue, 27 Nov 2018 08:10:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5D2B72AB44 for ; Tue, 27 Nov 2018 08:10:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7EC5189FD9; Tue, 27 Nov 2018 08:09:42 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from hermes.aosc.io (hermes.aosc.io [199.195.250.187]) by gabe.freedesktop.org (Postfix) with ESMTPS id 85BAA89DC2 for ; Tue, 27 Nov 2018 07:49:49 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 7212A11E6FA; Tue, 27 Nov 2018 07:43:13 +0000 (UTC) From: Icenowy Zheng To: Jernej Skrabec , Chen-Yu Tsai , Maxime Ripard , David Airlie , Rob Herring , Mark Rutland Subject: [PATCH 1/2] dt-bindings: gpu: add bus clock for Mali Midgard GPUs Date: Tue, 27 Nov 2018 15:42:48 +0800 Message-Id: <20181127074249.15204-1-icenowy@aosc.io> X-Mailman-Approved-At: Tue, 27 Nov 2018 08:09:36 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Icenowy Zheng MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Some SoCs adds a bus clock gate to the Mali Midgard GPU. Add the binding for the bus clock. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 18a2cde2e5f3..02f870cd60e6 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -31,6 +31,12 @@ Optional properties: - clocks : Phandle to clock for the Mali Midgard device. +- clock-names : Specify the names of the clocks specified in clocks + when multiple clocks are present. + * bus: bus clock for the GPU + * core: clock driving the GPU itself (When only one clock is present, + assume it's this clock.) + - mali-supply : Phandle to regulator for the Mali device. Refer to Documentation/devicetree/bindings/regulator/regulator.txt for details. From patchwork Tue Nov 27 07:42:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 10699833 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9A73114E2 for ; Tue, 27 Nov 2018 08:11:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8FD862AB46 for ; Tue, 27 Nov 2018 08:11:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 833452AB50; Tue, 27 Nov 2018 08:11:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 46D0A2AB46 for ; Tue, 27 Nov 2018 08:11:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C6D689F3C; Tue, 27 Nov 2018 08:11:00 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org X-Greylist: delayed 390 seconds by postgrey-1.36 at gabe; Tue, 27 Nov 2018 07:49:49 UTC Received: from hermes.aosc.io (hermes.aosc.io [199.195.250.187]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8557A89DC0 for ; Tue, 27 Nov 2018 07:49:49 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 02DA611E7EF; Tue, 27 Nov 2018 07:43:24 +0000 (UTC) From: Icenowy Zheng To: Jernej Skrabec , Chen-Yu Tsai , Maxime Ripard , David Airlie , Rob Herring , Mark Rutland Subject: [PATCH 2/2] dt-bindings: gpu: add Allwinner H6 Mali Midgard binding Date: Tue, 27 Nov 2018 15:42:49 +0800 Message-Id: <20181127074249.15204-2-icenowy@aosc.io> In-Reply-To: <20181127074249.15204-1-icenowy@aosc.io> References: <20181127074249.15204-1-icenowy@aosc.io> X-Mailman-Approved-At: Tue, 27 Nov 2018 08:09:36 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Icenowy Zheng MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Allwinner H6 SoC uses a Mali T720 GPU, which is one of the GPUs in the Midgard GPU product line. Add binding for the H6 Mali Midgard GPU. Signed-off-by: Icenowy Zheng --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt index 02f870cd60e6..c897dd7be48f 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -18,6 +18,7 @@ Required properties: + "amlogic,meson-gxm-mali" + "rockchip,rk3288-mali" + "rockchip,rk3399-mali" + + "allwinner,sun50i-h6-mali" - reg : Physical base address of the device and length of the register area. @@ -44,6 +45,18 @@ Optional properties: for details. +Vendor-specific bindings +------------------------ + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + + - allwinner,sun50i-h6-mali + Required properties: + * resets: phandle to the reset line for the GPU + + Example for a Mali-T760: gpu@ffa30000 {