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Tue, 27 Nov 2018 02:03:34 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v2 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base Date: Tue, 27 Nov 2018 15:33:14 +0530 Message-Id: <20181127100317.12809-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181127100317.12809-1-anup@brainfault.org> References: <20181127100317.12809-1-anup@brainfault.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181127_020345_761403_88115B6D X-CRM114-Status: GOOD ( 14.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoph Hellwig , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch does following optimizations: 1. Pre-compute hart base for each context handler 2. Pre-compute enable base for each context handler 3. Have enable lock for each context handler instead of global plic_toggle_lock Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 41 +++++++++++++------------------ 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 357e9daf94ae..56fce648a901 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -60,36 +60,24 @@ static void __iomem *plic_regs; struct plic_handler { bool present; int ctxid; + void __iomem *hart_base; + raw_spinlock_t enable_lock; + void __iomem *enable_base; }; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); -static inline void __iomem *plic_hart_offset(int ctxid) +static inline void plic_toggle(struct plic_handler *handler, + int hwirq, int enable) { - return plic_regs + CONTEXT_BASE + ctxid * CONTEXT_PER_HART; -} - -static inline u32 __iomem *plic_enable_base(int ctxid) -{ - return plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART; -} - -/* - * Protect mask operations on the registers given that we can't assume that - * atomic memory operations work on them. - */ -static DEFINE_RAW_SPINLOCK(plic_toggle_lock); - -static inline void plic_toggle(int ctxid, int hwirq, int enable) -{ - u32 __iomem *reg = plic_enable_base(ctxid) + (hwirq / 32); + u32 __iomem *reg = handler->enable_base + (hwirq / 32); u32 hwirq_mask = 1 << (hwirq % 32); - raw_spin_lock(&plic_toggle_lock); + raw_spin_lock(&handler->enable_lock); if (enable) writel(readl(reg) | hwirq_mask, reg); else writel(readl(reg) & ~hwirq_mask, reg); - raw_spin_unlock(&plic_toggle_lock); + raw_spin_unlock(&handler->enable_lock); } static inline void plic_irq_toggle(struct irq_data *d, int enable) @@ -101,7 +89,7 @@ static inline void plic_irq_toggle(struct irq_data *d, int enable) struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); if (handler->present) - plic_toggle(handler->ctxid, d->hwirq, enable); + plic_toggle(handler, d->hwirq, enable); } } @@ -150,7 +138,7 @@ static struct irq_domain *plic_irqdomain; static void plic_handle_irq(struct pt_regs *regs) { struct plic_handler *handler = this_cpu_ptr(&plic_handlers); - void __iomem *claim = plic_hart_offset(handler->ctxid) + CONTEXT_CLAIM; + void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; irq_hw_number_t hwirq; WARN_ON_ONCE(!handler->present); @@ -240,11 +228,16 @@ static int __init plic_init(struct device_node *node, handler = per_cpu_ptr(&plic_handlers, cpu); handler->present = true; handler->ctxid = i; + handler->hart_base = + plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART; + raw_spin_lock_init(&handler->enable_lock); + handler->enable_base = + plic_regs + ENABLE_BASE + i * ENABLE_PER_HART; /* priority must be > threshold to trigger an interrupt */ - writel(0, plic_hart_offset(i) + CONTEXT_THRESHOLD); + writel(0, handler->hart_base + CONTEXT_THRESHOLD); for (hwirq = 1; hwirq <= nr_irqs; hwirq++) - plic_toggle(i, hwirq, 0); + plic_toggle(handler, hwirq, 0); nr_mapped++; } From patchwork Tue Nov 27 10:03:15 2018 Content-Type: text/plain; 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Tue, 27 Nov 2018 02:03:39 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v2 2/4] irqchip: sifive-plic: More flexible plic_irq_toggle() Date: Tue, 27 Nov 2018 15:33:15 +0530 Message-Id: <20181127100317.12809-3-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181127100317.12809-1-anup@brainfault.org> References: <20181127100317.12809-1-anup@brainfault.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181127_020350_590517_4CA39646 X-CRM114-Status: GOOD ( 16.36 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoph Hellwig , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We make plic_irq_toggle() more generic so that we can enable/disable hwirq for given cpumask. This generic plic_irq_toggle() will be eventually used to implement set_affinity for PLIC driver. Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 79 +++++++++++++++---------------- 1 file changed, 39 insertions(+), 40 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 56fce648a901..95b4b92ca9b8 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -55,19 +55,26 @@ #define CONTEXT_THRESHOLD 0x00 #define CONTEXT_CLAIM 0x04 -static void __iomem *plic_regs; - struct plic_handler { bool present; - int ctxid; void __iomem *hart_base; raw_spinlock_t enable_lock; void __iomem *enable_base; }; + static DEFINE_PER_CPU(struct plic_handler, plic_handlers); -static inline void plic_toggle(struct plic_handler *handler, - int hwirq, int enable) +struct plic_hw { + u32 nr_irqs; + u32 nr_handlers; + u32 nr_mapped; + void __iomem *regs; + struct irq_domain *irqdomain; +}; + +static struct plic_hw plic; + +static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) { u32 __iomem *reg = handler->enable_base + (hwirq / 32); u32 hwirq_mask = 1 << (hwirq % 32); @@ -80,27 +87,23 @@ static inline void plic_toggle(struct plic_handler *handler, raw_spin_unlock(&handler->enable_lock); } -static inline void plic_irq_toggle(struct irq_data *d, int enable) +static void plic_irq_toggle(const struct cpumask *mask, int hwirq, int enable) { int cpu; - writel(enable, plic_regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); - for_each_cpu(cpu, irq_data_get_affinity_mask(d)) { - struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); - - if (handler->present) - plic_toggle(handler, d->hwirq, enable); - } + writel(enable, plic.regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); + for_each_cpu(cpu, mask) + plic_toggle(per_cpu_ptr(&plic_handlers, cpu), hwirq, enable); } static void plic_irq_enable(struct irq_data *d) { - plic_irq_toggle(d, 1); + plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 1); } static void plic_irq_disable(struct irq_data *d) { - plic_irq_toggle(d, 0); + plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 0); } static struct irq_chip plic_chip = { @@ -127,8 +130,6 @@ static const struct irq_domain_ops plic_irqdomain_ops = { .xlate = irq_domain_xlate_onecell, }; -static struct irq_domain *plic_irqdomain; - /* * Handling an interrupt is a two-step process: first you claim the interrupt * by reading the claim register, then you complete the interrupt by writing @@ -145,7 +146,7 @@ static void plic_handle_irq(struct pt_regs *regs) csr_clear(sie, SIE_SEIE); while ((hwirq = readl(claim))) { - int irq = irq_find_mapping(plic_irqdomain, hwirq); + int irq = irq_find_mapping(plic.irqdomain, hwirq); if (unlikely(irq <= 0)) pr_warn_ratelimited("can't find mapping for hwirq %lu\n", @@ -174,36 +175,34 @@ static int plic_find_hart_id(struct device_node *node) static int __init plic_init(struct device_node *node, struct device_node *parent) { - int error = 0, nr_handlers, nr_mapped = 0, i; - u32 nr_irqs; + int error = 0, i; - if (plic_regs) { + if (plic.regs) { pr_warn("PLIC already present.\n"); return -ENXIO; } - plic_regs = of_iomap(node, 0); - if (WARN_ON(!plic_regs)) + plic.regs = of_iomap(node, 0); + if (WARN_ON(!plic.regs)) return -EIO; error = -EINVAL; - of_property_read_u32(node, "riscv,ndev", &nr_irqs); - if (WARN_ON(!nr_irqs)) + of_property_read_u32(node, "riscv,ndev", &plic.nr_irqs); + if (WARN_ON(!plic.nr_irqs)) goto out_iounmap; - nr_handlers = of_irq_count(node); - if (WARN_ON(!nr_handlers)) + plic.nr_handlers = of_irq_count(node); + if (WARN_ON(!plic.nr_handlers)) goto out_iounmap; - if (WARN_ON(nr_handlers < num_possible_cpus())) + if (WARN_ON(plic.nr_handlers < num_possible_cpus())) goto out_iounmap; - error = -ENOMEM; - plic_irqdomain = irq_domain_add_linear(node, nr_irqs + 1, - &plic_irqdomain_ops, NULL); - if (WARN_ON(!plic_irqdomain)) + plic.irqdomain = irq_domain_add_linear(node, plic.nr_irqs + 1, + &plic_irqdomain_ops, NULL); + if (WARN_ON(!plic.irqdomain)) goto out_iounmap; - for (i = 0; i < nr_handlers; i++) { + for (i = 0; i < plic.nr_handlers; i++) { struct of_phandle_args parent; struct plic_handler *handler; irq_hw_number_t hwirq; @@ -227,27 +226,27 @@ static int __init plic_init(struct device_node *node, cpu = riscv_hartid_to_cpuid(hartid); handler = per_cpu_ptr(&plic_handlers, cpu); handler->present = true; - handler->ctxid = i; handler->hart_base = - plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART; + plic.regs + CONTEXT_BASE + i * CONTEXT_PER_HART; raw_spin_lock_init(&handler->enable_lock); handler->enable_base = - plic_regs + ENABLE_BASE + i * ENABLE_PER_HART; + plic.regs + ENABLE_BASE + i * ENABLE_PER_HART; /* priority must be > threshold to trigger an interrupt */ writel(0, handler->hart_base + CONTEXT_THRESHOLD); - for (hwirq = 1; hwirq <= nr_irqs; hwirq++) + for (hwirq = 1; hwirq <= plic.nr_irqs; hwirq++) plic_toggle(handler, hwirq, 0); - nr_mapped++; + + plic.nr_mapped++; } pr_info("mapped %d interrupts to %d (out of %d) handlers.\n", - nr_irqs, nr_mapped, nr_handlers); + plic.nr_irqs, plic.nr_mapped, plic.nr_handlers); set_handle_irq(plic_handle_irq); return 0; out_iounmap: - iounmap(plic_regs); + iounmap(plic.regs); return error; } From patchwork Tue Nov 27 10:03:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 10700011 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 984A813BF for ; Tue, 27 Nov 2018 10:04:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 869FB2A4CA for ; Tue, 27 Nov 2018 10:04:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 774C72A96C; Tue, 27 Nov 2018 10:04:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0CCDB2A4CA for ; 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Tue, 27 Nov 2018 02:03:43 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v2 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context Date: Tue, 27 Nov 2018 15:33:16 +0530 Message-Id: <20181127100317.12809-4-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181127100317.12809-1-anup@brainfault.org> References: <20181127100317.12809-1-anup@brainfault.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181127_020355_252609_F276FD18 X-CRM114-Status: GOOD ( 13.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoph Hellwig , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We explicitly differentiate between PLIC handler and context because PLIC context is for given mode of HART whereas PLIC handler is per-CPU software construct meant for handling interrupts from a particular PLIC context. Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 95b4b92ca9b8..ffd4deaca057 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -66,8 +66,8 @@ static DEFINE_PER_CPU(struct plic_handler, plic_handlers); struct plic_hw { u32 nr_irqs; + u32 nr_contexts; u32 nr_handlers; - u32 nr_mapped; void __iomem *regs; struct irq_domain *irqdomain; }; @@ -191,10 +191,10 @@ static int __init plic_init(struct device_node *node, if (WARN_ON(!plic.nr_irqs)) goto out_iounmap; - plic.nr_handlers = of_irq_count(node); - if (WARN_ON(!plic.nr_handlers)) + plic.nr_contexts = of_irq_count(node); + if (WARN_ON(!plic.nr_contexts)) goto out_iounmap; - if (WARN_ON(plic.nr_handlers < num_possible_cpus())) + if (WARN_ON(plic.nr_contexts < num_possible_cpus())) goto out_iounmap; plic.irqdomain = irq_domain_add_linear(node, plic.nr_irqs + 1, @@ -202,7 +202,7 @@ static int __init plic_init(struct device_node *node, if (WARN_ON(!plic.irqdomain)) goto out_iounmap; - for (i = 0; i < plic.nr_handlers; i++) { + for (i = 0; i < plic.nr_contexts; i++) { struct of_phandle_args parent; struct plic_handler *handler; irq_hw_number_t hwirq; @@ -225,6 +225,11 @@ static int __init plic_init(struct device_node *node, cpu = riscv_hartid_to_cpuid(hartid); handler = per_cpu_ptr(&plic_handlers, cpu); + if (handler->present) { + pr_warn("handler not available for context %d.\n", i); + continue; + } + handler->present = true; handler->hart_base = plic.regs + CONTEXT_BASE + i * CONTEXT_PER_HART; @@ -237,11 +242,11 @@ static int __init plic_init(struct device_node *node, for (hwirq = 1; hwirq <= plic.nr_irqs; hwirq++) plic_toggle(handler, hwirq, 0); - plic.nr_mapped++; + plic.nr_handlers++; } - pr_info("mapped %d interrupts to %d (out of %d) handlers.\n", - plic.nr_irqs, plic.nr_mapped, plic.nr_handlers); + pr_info("mapped %d interrupts with %d handlers for %d contexts.\n", + plic.nr_irqs, plic.nr_handlers, plic.nr_contexts); set_handle_irq(plic_handle_irq); return 0; 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Tue, 27 Nov 2018 02:03:48 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v2 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Date: Tue, 27 Nov 2018 15:33:17 +0530 Message-Id: <20181127100317.12809-5-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181127100317.12809-1-anup@brainfault.org> References: <20181127100317.12809-1-anup@brainfault.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181127_020400_257252_E9DBA4AB X-CRM114-Status: GOOD ( 14.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoph Hellwig , Atish Patra , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently on SMP host, all CPUs take external interrupts routed via PLIC. All CPUs will try to claim a given external interrupt but only one of them will succeed while other CPUs would simply resume whatever they were doing before. This means if we have N CPUs then for every external interrupt N-1 CPUs will always fail to claim it and waste their CPU time. Instead of above, external interrupts should be taken by only one CPU and we should have provision to explicity specify IRQ affinity from kernel-space or user-space. This patch provides irq_set_affinity() implementation for PLIC driver. It also updates irq_enable() such that PLIC interrupts are only enabled for one of CPUs specified in IRQ affinity mask. With this patch in-place, we can change IRQ affinity at any-time from user-space using procfs. Example: / # cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 8: 44 0 0 0 SiFive PLIC 8 virtio0 10: 48 0 0 0 SiFive PLIC 10 ttyS0 IPI0: 55 663 58 363 Rescheduling interrupts IPI1: 0 1 3 16 Function call interrupts / # / # / # echo 4 > /proc/irq/10/smp_affinity / # / # cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 8: 45 0 0 0 SiFive PLIC 8 virtio0 10: 160 0 17 0 SiFive PLIC 10 ttyS0 IPI0: 68 693 77 410 Rescheduling interrupts IPI1: 0 2 3 16 Function call interrupts Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 35 +++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index ffd4deaca057..fec7da3797fa 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -98,14 +98,42 @@ static void plic_irq_toggle(const struct cpumask *mask, int hwirq, int enable) static void plic_irq_enable(struct irq_data *d) { - plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 1); + unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d), + cpu_online_mask); + WARN_ON(cpu >= nr_cpu_ids); + plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1); } static void plic_irq_disable(struct irq_data *d) { - plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 0); + plic_irq_toggle(cpu_possible_mask, d->hwirq, 0); } +#ifdef CONFIG_SMP +static int plic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, + bool force) +{ + unsigned int cpu; + + if (!force) + cpu = cpumask_any_and(mask_val, cpu_online_mask); + else + cpu = cpumask_first(mask_val); + + if (cpu >= nr_cpu_ids) + return -EINVAL; + + if (!irqd_irq_disabled(d)) { + plic_irq_toggle(cpu_possible_mask, d->hwirq, 0); + plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1); + } + + irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK_DONE; +} +#endif + static struct irq_chip plic_chip = { .name = "SiFive PLIC", /* @@ -114,6 +142,9 @@ static struct irq_chip plic_chip = { */ .irq_enable = plic_irq_enable, .irq_disable = plic_irq_disable, +#ifdef CONFIG_SMP + .irq_set_affinity = plic_set_affinity, +#endif }; static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,