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[2001:1c00:c1e:bf00:1054:9d19:e0f0:8214]) by smtp.gmail.com with ESMTPSA id i8sm17337145edu.64.2021.05.12.03.06.23 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 May 2021 03:06:23 -0700 (PDT) From: Hans de Goede To: intel-gfx Message-ID: <3e2e12f6-a5bd-858f-7454-fce19f70cf30@redhat.com> Date: Wed, 12 May 2021 12:06:23 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=hdegoede@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Subject: [Intel-gfx] i915 clear-residuals BYT + IVB rendering issue + possible fix X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi All, We (Fedora) received a bug-report about rendering issues on BYT and IVB caused by the i915 clear-residuals work which landed in 5.10.y : The Fedora bug: https://bugzilla.redhat.com/show_bug.cgi?id=1959581 Points to these i915 bugs: https://gitlab.freedesktop.org/drm/intel/-/issues/3071 https://gitlab.freedesktop.org/drm/intel/-/issues/3081#note_890606 With the second link containing a possible fix which looks promising if someone can take a look at this, then that would be great: Note the: https://gitlab.freedesktop.org/drm/intel/-/issues/3081#note_890606 Link contains details about the what and why of this change. Regards, Hans diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index de575fdb0..054a0f5b8 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -397,7 +397,7 @@ static void emit_batch(struct i915_vma * const vma, gen7_emit_pipeline_invalidate(&cmds); batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); - batch_add(&cmds, 0xffff0000); + batch_add(&cmds, 0xfffb0000); batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); gen7_emit_pipeline_invalidate(&cmds);