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Thu, 13 May 2021 11:47:15 +0000 From: quanyang.wang@windriver.com To: Hyun Kwon , Laurent Pinchart , David Airlie , Daniel Vetter , Michal Simek Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Quanyang Wang Subject: [PATCH 1/2] drm: xlnx: add is_layer_vid() to simplify the code Date: Thu, 13 May 2021 19:45:39 +0800 Message-Id: <20210513114540.1241122-2-quanyang.wang@windriver.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210513114540.1241122-1-quanyang.wang@windriver.com> References: <20210513114540.1241122-1-quanyang.wang@windriver.com> X-Originating-IP: [60.247.85.82] X-ClientProxiedBy: HK2P15301CA0015.APCP153.PROD.OUTLOOK.COM (2603:1096:202:1::25) To CY4PR11MB0071.namprd11.prod.outlook.com (2603:10b6:910:7a::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from pek-qwang2-d1.wrs.com (60.247.85.82) by HK2P15301CA0015.APCP153.PROD.OUTLOOK.COM (2603:1096:202:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4150.8 via Frontend Transport; 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Signed-off-by: Quanyang Wang Acked-by: Paul Cercueil --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 39 +++++++++++++++++------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index 109d627968ac..c55e24412f8c 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -434,30 +434,35 @@ static void zynqmp_disp_avbuf_write(struct zynqmp_disp_avbuf *avbuf, writel(val, avbuf->base + reg); } +static bool is_layer_vid(struct zynqmp_disp_layer *layer) +{ + return (layer->id == ZYNQMP_DISP_LAYER_VID) ? true : false; +} + /** * zynqmp_disp_avbuf_set_format - Set the input format for a layer * @avbuf: Audio/video buffer manager - * @layer: The layer ID + * @layer: The layer * @fmt: The format information * * Set the video buffer manager format for @layer to @fmt. */ static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp_avbuf *avbuf, - enum zynqmp_disp_layer_id layer, + struct zynqmp_disp_layer *layer, const struct zynqmp_disp_format *fmt) { unsigned int i; u32 val; val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_FMT); - val &= layer == ZYNQMP_DISP_LAYER_VID + val &= is_layer_vid(layer) ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK; val |= fmt->buf_fmt; zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_FMT, val); for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) { - unsigned int reg = layer == ZYNQMP_DISP_LAYER_VID + unsigned int reg = is_layer_vid(layer) ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i) : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i); @@ -573,19 +578,19 @@ static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp_avbuf *avbuf) /** * zynqmp_disp_avbuf_enable_video - Enable a video layer * @avbuf: Audio/video buffer manager - * @layer: The layer ID + * @layer: The layer * @mode: Operating mode of layer * * Enable the video/graphics buffer for @layer. */ static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp_avbuf *avbuf, - enum zynqmp_disp_layer_id layer, + struct zynqmp_disp_layer *layer, enum zynqmp_disp_layer_mode mode) { u32 val; val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); - if (layer == ZYNQMP_DISP_LAYER_VID) { + if (is_layer_vid(layer)) { val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; if (mode == ZYNQMP_DISP_LAYER_NONLIVE) val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM; @@ -605,17 +610,17 @@ static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp_avbuf *avbuf, /** * zynqmp_disp_avbuf_disable_video - Disable a video layer * @avbuf: Audio/video buffer manager - * @layer: The layer ID + * @layer: The layer * * Disable the video/graphics buffer for @layer. */ static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp_avbuf *avbuf, - enum zynqmp_disp_layer_id layer) + struct zynqmp_disp_layer *layer) { u32 val; val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); - if (layer == ZYNQMP_DISP_LAYER_VID) { + if (is_layer_vid(layer)) { val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE; } else { @@ -807,7 +812,7 @@ static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp_blend *blend, } } - if (layer->id == ZYNQMP_DISP_LAYER_VID) + if (is_layer_vid(layer)) reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0); else reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0); @@ -818,7 +823,7 @@ static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp_blend *blend, zynqmp_disp_blend_write(blend, reg + 8, coeffs[i + swap[2]]); } - if (layer->id == ZYNQMP_DISP_LAYER_VID) + if (is_layer_vid(layer)) reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0); else reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0); @@ -1025,7 +1030,7 @@ zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, */ static void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer) { - zynqmp_disp_avbuf_enable_video(&layer->disp->avbuf, layer->id, + zynqmp_disp_avbuf_enable_video(&layer->disp->avbuf, layer, ZYNQMP_DISP_LAYER_NONLIVE); zynqmp_disp_blend_layer_enable(&layer->disp->blend, layer); @@ -1046,7 +1051,7 @@ static void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) for (i = 0; i < layer->drm_fmt->num_planes; i++) dmaengine_terminate_sync(layer->dmas[i].chan); - zynqmp_disp_avbuf_disable_video(&layer->disp->avbuf, layer->id); + zynqmp_disp_avbuf_disable_video(&layer->disp->avbuf, layer); zynqmp_disp_blend_layer_disable(&layer->disp->blend, layer); } @@ -1067,7 +1072,7 @@ static void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format); layer->drm_fmt = info; - zynqmp_disp_avbuf_set_format(&layer->disp->avbuf, layer->id, + zynqmp_disp_avbuf_set_format(&layer->disp->avbuf, layer, layer->disp_fmt); /* @@ -1244,8 +1249,8 @@ static int zynqmp_disp_create_planes(struct zynqmp_disp *disp) drm_formats[j] = layer->info->formats[j].drm_fmt; /* Graphics layer is primary, and video layer is overlay. */ - type = i == ZYNQMP_DISP_LAYER_GFX - ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; + type = is_layer_vid(layer) + ? DRM_PLANE_TYPE_OVERLAY : DRM_PLANE_TYPE_PRIMARY; ret = drm_universal_plane_init(disp->drm, &layer->plane, 0, &zynqmp_disp_plane_funcs, drm_formats, From patchwork Thu May 13 11:45:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quanyang Wang X-Patchwork-Id: 12255669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B508FC433ED for ; Thu, 13 May 2021 11:49:15 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1E972613B5 for ; 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Thu, 13 May 2021 11:47:19 +0000 From: quanyang.wang@windriver.com To: Hyun Kwon , Laurent Pinchart , David Airlie , Daniel Vetter , Michal Simek Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Quanyang Wang Subject: [PATCH 2/2] drm: xlnx: consolidate the functions which programming AUDIO_VIDEO_SELECT register Date: Thu, 13 May 2021 19:45:40 +0800 Message-Id: <20210513114540.1241122-3-quanyang.wang@windriver.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210513114540.1241122-1-quanyang.wang@windriver.com> References: <20210513114540.1241122-1-quanyang.wang@windriver.com> X-Originating-IP: [60.247.85.82] X-ClientProxiedBy: HK2P15301CA0015.APCP153.PROD.OUTLOOK.COM (2603:1096:202:1::25) To CY4PR11MB0071.namprd11.prod.outlook.com (2603:10b6:910:7a::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from pek-qwang2-d1.wrs.com (60.247.85.82) by HK2P15301CA0015.APCP153.PROD.OUTLOOK.COM (2603:1096:202:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4150.8 via Frontend Transport; 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And in the future, many drm properties (like video_tpg, audio_tpg, audio_pl, etc) also need to access it. So let's introduce some variables of enum type and consolidate the code to unify handling this. Signed-off-by: Quanyang Wang --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 166 ++++++++++++++---------- drivers/gpu/drm/xlnx/zynqmp_disp_regs.h | 15 +-- 2 files changed, 101 insertions(+), 80 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index c55e24412f8c..a82bc88a98aa 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -102,12 +102,39 @@ enum zynqmp_disp_layer_id { /** * enum zynqmp_disp_layer_mode - Layer mode - * @ZYNQMP_DISP_LAYER_NONLIVE: non-live (memory) mode + * @ZYNQMP_DISP_LAYER_MEM: memory mode * @ZYNQMP_DISP_LAYER_LIVE: live (stream) mode + * @ZYNQMP_DISP_LAYER_TPG: tpg mode (only for video layer) + * @ZYNQMP_DISP_LAYER_DISABLE: disable mode */ enum zynqmp_disp_layer_mode { - ZYNQMP_DISP_LAYER_NONLIVE, - ZYNQMP_DISP_LAYER_LIVE + ZYNQMP_DISP_LAYER_MEM, + ZYNQMP_DISP_LAYER_LIVE, + ZYNQMP_DISP_LAYER_TPG, + ZYNQMP_DISP_LAYER_DISABLE +}; + +enum avbuf_vid_mode { + VID_MODE_LIVE, + VID_MODE_MEM, + VID_MODE_TPG, + VID_MODE_NONE +}; + +enum avbuf_gfx_mode { + GFX_MODE_DISABLE, + GFX_MODE_MEM, + GFX_MODE_LIVE, + GFX_MODE_NONE +}; + +enum avbuf_aud_mode { + AUD1_MODE_LIVE, + AUD1_MODE_MEM, + AUD1_MODE_TPG, + AUD1_MODE_DISABLE, + AUD2_MODE_DISABLE, + AUD2_MODE_ENABLE }; /** @@ -542,92 +569,98 @@ static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp_avbuf *avbuf) } /** - * zynqmp_disp_avbuf_enable_audio - Enable audio + * zynqmp_disp_avbuf_output_select - Select the buffer manager outputs * @avbuf: Audio/video buffer manager + * @layer: The layer + * @mode: The mode for this layer * - * Enable all audio buffers with a non-live (memory) source. + * Select the buffer manager outputs for @layer. */ -static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp_avbuf *avbuf) +static void zynqmp_disp_avbuf_output_select(struct zynqmp_disp_avbuf *avbuf, + struct zynqmp_disp_layer *layer, u32 mode) { - u32 val; - - val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); - val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM; - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; - zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); + u32 reg; + + reg = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); + /* Select audio mode when the layer is NULL */ + if (layer == NULL) { + if (mode >= AUD2_MODE_DISABLE) { + reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_MASK; + reg |= (mode - AUD2_MODE_DISABLE) + << ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_SHIFT; + } else { + reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; + reg |= mode << ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_SHIFT; + } + } else if (is_layer_vid(layer)) { + reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; + reg |= mode << ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_SHIFT; + } else { + reg &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; + reg |= mode << ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_SHIFT; + } + zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, reg); } /** - * zynqmp_disp_avbuf_disable_audio - Disable audio + * zynqmp_disp_avbuf_enable_audio - Enable audio * @avbuf: Audio/video buffer manager * - * Disable all audio buffers. + * Enable all audio buffers. */ -static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp_avbuf *avbuf) +static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp_avbuf *avbuf) { - u32 val; - - val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); - val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE; - val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; - zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); + zynqmp_disp_avbuf_output_select(avbuf, NULL, AUD1_MODE_MEM); + zynqmp_disp_avbuf_output_select(avbuf, NULL, AUD2_MODE_ENABLE); } /** - * zynqmp_disp_avbuf_enable_video - Enable a video layer + * zynqmp_disp_avbuf_disable_audio - Disable audio * @avbuf: Audio/video buffer manager - * @layer: The layer - * @mode: Operating mode of layer * - * Enable the video/graphics buffer for @layer. + * Disable all audio buffers. */ -static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp_avbuf *avbuf, - struct zynqmp_disp_layer *layer, - enum zynqmp_disp_layer_mode mode) +static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp_avbuf *avbuf) { - u32 val; - - val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); - if (is_layer_vid(layer)) { - val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; - if (mode == ZYNQMP_DISP_LAYER_NONLIVE) - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM; - else - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE; - } else { - val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; - if (mode == ZYNQMP_DISP_LAYER_NONLIVE) - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; - else - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE; - } - zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); + zynqmp_disp_avbuf_output_select(avbuf, NULL, AUD1_MODE_DISABLE); + zynqmp_disp_avbuf_output_select(avbuf, NULL, AUD2_MODE_DISABLE); } /** - * zynqmp_disp_avbuf_disable_video - Disable a video layer - * @avbuf: Audio/video buffer manager + * zynqmp_disp_avbuf_set_layer_output -Set layer output * @layer: The layer + * @mode: The layer mode * - * Disable the video/graphics buffer for @layer. + * Set output for @layer */ -static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp_avbuf *avbuf, - struct zynqmp_disp_layer *layer) +static void zynqmp_disp_avbuf_set_layer_output(struct zynqmp_disp_layer *layer, + enum zynqmp_disp_layer_mode mode) { - u32 val; - - val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); - if (is_layer_vid(layer)) { - val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE; - } else { - val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; - val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE; + int val; + struct zynqmp_disp *disp = layer->disp; + + switch (mode) { + case ZYNQMP_DISP_LAYER_LIVE: + val = is_layer_vid(layer) ? VID_MODE_LIVE : GFX_MODE_LIVE; + break; + case ZYNQMP_DISP_LAYER_MEM: + val = is_layer_vid(layer) ? VID_MODE_MEM : GFX_MODE_MEM; + break; + case ZYNQMP_DISP_LAYER_TPG: + if (!is_layer_vid(layer)) { + dev_err(disp->dev, "gfx layer has no tpg mode\n"); + return; + } + val = VID_MODE_TPG; + break; + case ZYNQMP_DISP_LAYER_DISABLE: + val = is_layer_vid(layer) ? VID_MODE_NONE : GFX_MODE_DISABLE; + break; + default: + dev_err(disp->dev, "invalid layer mode\n"); + return; } - zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); + zynqmp_disp_avbuf_output_select(&disp->avbuf, layer, val); } /** @@ -1030,11 +1063,10 @@ zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, */ static void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer) { - zynqmp_disp_avbuf_enable_video(&layer->disp->avbuf, layer, - ZYNQMP_DISP_LAYER_NONLIVE); + zynqmp_disp_avbuf_set_layer_output(layer, ZYNQMP_DISP_LAYER_MEM); zynqmp_disp_blend_layer_enable(&layer->disp->blend, layer); - layer->mode = ZYNQMP_DISP_LAYER_NONLIVE; + layer->mode = ZYNQMP_DISP_LAYER_MEM; } /** @@ -1051,7 +1083,7 @@ static void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) for (i = 0; i < layer->drm_fmt->num_planes; i++) dmaengine_terminate_sync(layer->dmas[i].chan); - zynqmp_disp_avbuf_disable_video(&layer->disp->avbuf, layer); + zynqmp_disp_avbuf_set_layer_output(layer, ZYNQMP_DISP_LAYER_DISABLE); zynqmp_disp_blend_layer_disable(&layer->disp->blend, layer); } diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h b/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h index f92a006d5070..dad3e356d9ab 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h +++ b/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h @@ -120,23 +120,12 @@ #define ZYNQMP_DISP_AV_BUF_OUTPUT 0x70 #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_SHIFT 0 #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK (0x3 << 0) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE (0 << 0) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM (1 << 0) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_PATTERN (2 << 0) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE (3 << 0) #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_SHIFT 2 #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK (0x3 << 2) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE (0 << 2) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM (1 << 2) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE (2 << 2) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_NONE (3 << 2) #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_SHIFT 4 #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK (0x3 << 4) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PL (0 << 4) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM (1 << 4) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PATTERN (2 << 4) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE (3 << 4) -#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN BIT(6) +#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_MASK (0x1 << 6) +#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_SHIFT 6 #define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT0 0x74 #define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT1 0x78 #define ZYNQMP_DISP_AV_BUF_PATTERN_GEN_SELECT 0x100