From patchwork Thu May 13 13:45:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 12255849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06AA9C433ED for ; Thu, 13 May 2021 13:48:33 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CC2F613C5 for ; Thu, 13 May 2021 13:48:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6CC2F613C5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Ln5a/lJQoJFw9bHGY9/XtLlrKfofyTe0FE8KdWWTi68=; b=Dw0LGZU6sDWVhyO29rmhQQbBc kl0uWpjAcRlYujnh4dXK0jBWOEeR73S2sh5WHqDT3QRW9hwE+6lc9RvS9KRF8PLoMLE8TR4DqnDzk W/nYmulSN9d/Wk1LLvGrUt8bFMRfJlGdfDG8HICHXkKjXyBW75q+IBsLXpigP+LDkPaSRWUZF8T1c U7Uo1mLtCUY6x45JLEZJcJPW66LwVnc0r433QGAqJerzINMpJ56ETc+Nlmn6eALrcMo4XJGEMKkJL Mod9fOWnQ77Yyc1PGIFi+QNCHjvCB2KkTXfpsRHlrCNMsoTWma/AsiY5kcoCXw1FX6xhFRP3lJnK5 LrOEd/9OA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lhBfw-005eJd-KM; Thu, 13 May 2021 13:46:52 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lhBfl-005eIj-NT for linux-arm-kernel@desiato.infradead.org; Thu, 13 May 2021 13:46:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:CC:To:From:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=flRwSlD3DTRrQQWdUyrcvfAenRCVTlA71wuTlzMX4Vs=; b=m6mYSg3txy2PWdKWwRXR9MPzfG 9+6YKv3tpWAa7Nivx08Vy+83ImBkEZHkBWUUpe9hNxN7RVd0v+y421wT9n1gmnn2P3m52rylVcvEo n+PrbC8xfwi/+LO2IGH2dp5mXJvGOgzwOcVWWAU44fM8XrYCR+CbrSk+aHSV/tLI7dAgaXHLEV8qM sdYDFlQ2ijiyatCnkLgVSUV8HK1zdUu6KO6DwuIf41+pHdVH13RVN0Ycj5TetFzvZqR/mA7tcTXxh g2r+nkt4znyoKPFu5qs3Kl9p9pi2fUaODlCBfsPmEARGSvCgah1EpP6PYiM0D7GgLyIUSKHd3CJzN Xd3jGTkw==; Received: from szxga05-in.huawei.com ([45.249.212.191]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lhBfi-00BHqJ-Gv for linux-arm-kernel@lists.infradead.org; Thu, 13 May 2021 13:46:40 +0000 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FgtD400ydzsRCP; Thu, 13 May 2021 21:43:47 +0800 (CST) Received: from A2006125610.china.huawei.com (10.47.81.63) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Thu, 13 May 2021 21:46:22 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , , Subject: [PATCH v4 1/8] ACPI/IORT: Add support for RMR node parsing Date: Thu, 13 May 2021 14:45:43 +0100 Message-ID: <20210513134550.2117-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> References: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.81.63] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210513_064638_921988_3D2A231A X-CRM114-Status: GOOD ( 16.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for parsing RMR node information from ACPI. Find associated stream id and smmu node info from the RMR node and populate a linked list with RMR memory descriptors. Signed-off-by: Shameer Kolothum --- drivers/acpi/arm64/iort.c | 104 +++++++++++++++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 3912a1f6058e..fea1ffaedf3b 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -40,6 +40,19 @@ struct iort_fwnode { static LIST_HEAD(iort_fwnode_list); static DEFINE_SPINLOCK(iort_fwnode_lock); +/* + * One entry for IORT RMR. + */ +struct iort_rmr_entry { + struct list_head list; + u32 sid; + struct acpi_iort_node *smmu; + struct acpi_iort_rmr_desc *rmr_desc; + u32 flags; +}; + +static LIST_HEAD(iort_rmr_list); /* list of RMR regions from ACPI */ + /** * iort_set_fwnode() - Create iort_fwnode and use it to register * iommu data in the iort_fwnode_list @@ -393,7 +406,8 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node, if (node->type == ACPI_IORT_NODE_NAMED_COMPONENT || node->type == ACPI_IORT_NODE_PCI_ROOT_COMPLEX || node->type == ACPI_IORT_NODE_SMMU_V3 || - node->type == ACPI_IORT_NODE_PMCG) { + node->type == ACPI_IORT_NODE_PMCG || + node->type == ACPI_IORT_NODE_RMR) { *id_out = map->output_base; return parent; } @@ -1660,6 +1674,91 @@ static void __init iort_enable_acs(struct acpi_iort_node *iort_node) #else static inline void iort_enable_acs(struct acpi_iort_node *iort_node) { } #endif +static int iort_rmr_desc_valid(struct acpi_iort_rmr_desc *desc, u32 count) +{ + int i, j; + + for (i = 0; i < count; i++) { + u64 end, start = desc[i].base_address, length = desc[i].length; + + if (!IS_ALIGNED(start, SZ_64K) || !IS_ALIGNED(length, SZ_64K)) + return -EINVAL; + + end = start + length - 1; + + /* Check for address overlap */ + for (j = i + 1; j < count; j++) { + u64 e_start = desc[j].base_address; + u64 e_end = e_start + desc[j].length - 1; + + if (start <= e_end && end >= e_start) + return -EINVAL; + } + } + + return 0; +} + +static int __init iort_parse_rmr(struct acpi_iort_node *iort_node) +{ + struct acpi_iort_node *smmu; + struct iort_rmr_entry *e; + struct acpi_iort_rmr *rmr; + struct acpi_iort_rmr_desc *rmr_desc; + u32 map_count = iort_node->mapping_count; + u32 sid; + int i, ret = 0; + + if (iort_node->type != ACPI_IORT_NODE_RMR) + return 0; + + if (!iort_node->mapping_offset || map_count != 1) { + pr_err(FW_BUG "Invalid ID mapping, skipping RMR node %p\n", + iort_node); + return -EINVAL; + } + + /* Retrieve associated smmu and stream id */ + smmu = iort_node_get_id(iort_node, &sid, 0); + if (!smmu) { + pr_err(FW_BUG "Invalid SMMU reference, skipping RMR node %p\n", + iort_node); + return -EINVAL; + } + + /* Retrieve RMR data */ + rmr = (struct acpi_iort_rmr *)iort_node->node_data; + if (!rmr->rmr_offset || !rmr->rmr_count) { + pr_err(FW_BUG "Invalid RMR descriptor array, skipping RMR node %p\n", + iort_node); + return -EINVAL; + } + + rmr_desc = ACPI_ADD_PTR(struct acpi_iort_rmr_desc, iort_node, + rmr->rmr_offset); + + ret = iort_rmr_desc_valid(rmr_desc, rmr->rmr_count); + if (ret) { + pr_err(FW_BUG "Invalid RMR descriptor[%d] for node %p, skipping...\n", + i, iort_node); + return ret; + } + + for (i = 0; i < rmr->rmr_count; i++, rmr_desc++) { + e = kmalloc(sizeof(*e), GFP_KERNEL); + if (!e) + return -ENOMEM; + + e->sid = sid; + e->smmu = smmu; + e->rmr_desc = rmr_desc; + e->flags = rmr->flags; + + list_add_tail(&e->list, &iort_rmr_list); + } + + return 0; +} static void __init iort_init_platform_devices(void) { @@ -1689,6 +1788,9 @@ static void __init iort_init_platform_devices(void) iort_enable_acs(iort_node); + if (iort_table->revision == 3) + iort_parse_rmr(iort_node); + ops = iort_get_dev_cfg(iort_node); if (ops) { fwnode = acpi_alloc_fwnode_static(); From patchwork Thu May 13 13:45:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 12255851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9094EC433ED for ; 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bh=LhC7FEfFFueMlo0Oj0z8A9hkVQlZ5ToqeydOvKY+6mU=; b=EZ5P1vl+AIaiFkSZjJQTxuDC9n 0k4MTacQS8aTyMdRDUvFvlOFw8kcxkAiEOtr78YGcFdTTMUdp3YZq7QQQjbWM7sO8fwt658uszxYV MWnXXChgDiESKCSeEpCnPNvQPhKVUngEKSXzCQgZ3CMseSF96+j6C+Ok3o01Pl+Gn87x0yYr7+cU2 e0ezgIEj2kD4OWbOsuGQm+HEBw02SABbP6IwCdtDFG0XQjNmeS2q9d92ie4JkQT9hhR584RGuJwVG pVabm9kR7G65p1eMJeaiaid6wrqbZbHRm5MCTliiqJGoFE/rFFTg+s8dgsLZeREOh7RoHkrs3MZuX Ig7wILng==; Received: from szxga04-in.huawei.com ([45.249.212.190]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lhBfi-00BHqz-W8 for linux-arm-kernel@lists.infradead.org; Thu, 13 May 2021 13:46:41 +0000 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FgtD86xGHz16Njp; Thu, 13 May 2021 21:43:52 +0800 (CST) Received: from A2006125610.china.huawei.com (10.47.81.63) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Thu, 13 May 2021 21:46:27 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , , Subject: [PATCH v4 2/8] iommu/dma: Introduce generic helper to retrieve RMR info Date: Thu, 13 May 2021 14:45:44 +0100 Message-ID: <20210513134550.2117-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> References: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.81.63] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210513_064639_378085_2D881774 X-CRM114-Status: GOOD ( 13.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Reserved Memory Regions(RMR) associated with an IOMMU can be described through ACPI IORT tables in systems with devices that require a unity mapping or bypass for those regions. Introduce a generic interface so that IOMMU drivers can retrieve and set up necessary mappings. Signed-off-by: Shameer Kolothum --- drivers/iommu/dma-iommu.c | 33 +++++++++++++++++++++++++++++++++ include/linux/dma-iommu.h | 10 ++++++++++ include/linux/iommu.h | 19 +++++++++++++++++++ 3 files changed, 62 insertions(+) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 7bcdd1205535..674bd8815159 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -193,6 +193,39 @@ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) } EXPORT_SYMBOL(iommu_dma_get_resv_regions); +/** + * iommu_dma_get_rmrs - Retrieve Reserved Memory Regions(RMRs) associated + * with a given IOMMU + * @iommu_fwnode: fwnode associated with IOMMU + * @list: RMR list to be populated + * + */ +int iommu_dma_get_rmrs(struct fwnode_handle *iommu_fwnode, + struct list_head *list) +{ + return -EINVAL; +} +EXPORT_SYMBOL(iommu_dma_get_rmrs); + +struct iommu_rmr *iommu_dma_alloc_rmr(u64 base, u64 length, u32 sid, + u32 flags) +{ + struct iommu_rmr *rmr; + + rmr = kzalloc(sizeof(*rmr), GFP_KERNEL); + if (!rmr) + return NULL; + + INIT_LIST_HEAD(&rmr->list); + rmr->base_address = base; + rmr->length = length; + rmr->sid = sid; + rmr->flags = flags; + + return rmr; +} +EXPORT_SYMBOL(iommu_dma_alloc_rmr); + static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, phys_addr_t start, phys_addr_t end) { diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h index 6e75a2d689b4..319f332c279f 100644 --- a/include/linux/dma-iommu.h +++ b/include/linux/dma-iommu.h @@ -42,12 +42,17 @@ void iommu_dma_free_cpu_cached_iovas(unsigned int cpu, extern bool iommu_dma_forcedac; +int iommu_dma_get_rmrs(struct fwnode_handle *iommu, struct list_head *list); +struct iommu_rmr *iommu_dma_alloc_rmr(u64 base, u64 length, u32 sid, u32 flags); + #else /* CONFIG_IOMMU_DMA */ struct iommu_domain; struct msi_desc; struct msi_msg; struct device; +struct fwnode_handle; +struct iommu_rmr; static inline void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size) @@ -83,5 +88,10 @@ static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_he { } +int iommu_dma_get_rmrs(struct fwnode_handle *iommu, struct list_head *list) +{ + return -ENODEV; +} + #endif /* CONFIG_IOMMU_DMA */ #endif /* __DMA_IOMMU_H */ diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 32d448050bf7..73cd2831cb45 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -555,6 +555,25 @@ struct iommu_sva { struct device *dev; }; +/** + * struct iommu_rmr - Reserved Memory Region details per IOMMU + * @list: Linked list pointers to hold RMR region info + * @base_address: base address of Reserved Memory Region + * @length: length of memory region + * @sid: associated stream id + * @flags: flags that apply to the RMR node + */ +struct iommu_rmr { + struct list_head list; + phys_addr_t base_address; + u64 length; + u32 sid; + u32 flags; +}; + +/* RMR Remap permitted */ +#define IOMMU_RMR_REMAP_PERMITTED (1 << 0) + int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops); void iommu_fwspec_free(struct device *dev); From patchwork Thu May 13 13:45:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 12255853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3413EC433B4 for ; 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bh=WR6ijNUUYHwxxb7y3nHXkaEGt03tMduEeHClWr1NQ+k=; b=t4w0c3Bwk5H+nOHlRCV+R0wb9k ep90JA2i10De/tI2Sp8Bv7QpFiGymJmKTkk7SLcQVjCLcg3k1eSY2HQuYJQN1a7CEiwaRoSqGlTiz qHg4d2rvQoa56/Qs6iBO0ajAhLo1SKQrvRXUM7JddfdiDhyYCVWZTJ9VhQesjwUF0F7HZX7q16SH+ tsbA7yuAOSy8HFDJvlX3/45kbX48SqYeEiu5QSXcBIwejKhv4aYc4QnXXZRlHwJ/5bqzFQ8X8MDz3 6ZljCXSXzBcJjiZR0gp0J3AJmIuo8gt7ZRbDodG1zKiD7cWzExe2bImqgG1wbtK3cQz1HWi4l29Sl WZGtkebg==; Received: from szxga05-in.huawei.com ([45.249.212.191]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lhBfq-00BHsj-ST for linux-arm-kernel@lists.infradead.org; Thu, 13 May 2021 13:46:48 +0000 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FgtDM1Y86zsRJ3; Thu, 13 May 2021 21:44:03 +0800 (CST) Received: from A2006125610.china.huawei.com (10.47.81.63) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Thu, 13 May 2021 21:46:33 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , , Subject: [PATCH v4 3/8] ACPI/IORT: Add a helper to retrieve RMR memory regions Date: Thu, 13 May 2021 14:45:45 +0100 Message-ID: <20210513134550.2117-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> References: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.81.63] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210513_064647_283631_A5A09917 X-CRM114-Status: GOOD ( 14.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a helper function that retrieves RMR memory descriptors associated with a given IOMMU. This will be used by IOMMU drivers to setup necessary mappings. Now that we have this, invoke it from the generic helper interface. Signed-off-by: Shameer Kolothum --- drivers/acpi/arm64/iort.c | 40 +++++++++++++++++++++++++++++++++++++++ drivers/iommu/dma-iommu.c | 3 +++ include/linux/acpi_iort.h | 7 +++++++ 3 files changed, 50 insertions(+) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index fea1ffaedf3b..6ca88c38987a 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -837,6 +838,43 @@ static inline int iort_add_device_replay(struct device *dev) return err; } +/** + * iort_iommu_get_rmrs - Helper to retrieve RMR info associated with IOMMU + * @iommu: fwnode for the IOMMU + * @head: RMR list head to be populated + * + * Returns: 0 on success, <0 failure + */ +int iort_iommu_get_rmrs(struct fwnode_handle *iommu_fwnode, + struct list_head *head) +{ + struct iort_rmr_entry *e; + struct acpi_iort_node *iommu; + + iommu = iort_get_iort_node(iommu_fwnode); + if (!iommu) + return -EINVAL; + + list_for_each_entry(e, &iort_rmr_list, list) { + struct acpi_iort_rmr_desc *rmr_desc; + struct iommu_rmr *rmr; + + if (e->smmu != iommu) + continue; + + rmr_desc = e->rmr_desc; + rmr = iommu_dma_alloc_rmr(rmr_desc->base_address, + rmr_desc->length, e->sid, + e->flags); + if (!rmr) + return -ENOMEM; + + list_add_tail(&rmr->list, head); + } + + return 0; +} + /** * iort_iommu_msi_get_resv_regions - Reserved region driver helper * @dev: Device from iommu_get_resv_regions() @@ -1108,6 +1146,8 @@ int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) const struct iommu_ops *iort_iommu_configure_id(struct device *dev, const u32 *input_id) { return NULL; } +int iort_iommu_get_rmrs(struct fwnode_handle *fwnode, struct list_head *head) +{ return -ENODEV; } #endif static int nc_dma_get_range(struct device *dev, u64 *size) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 674bd8815159..2d9caf548a32 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -203,6 +203,9 @@ EXPORT_SYMBOL(iommu_dma_get_resv_regions); int iommu_dma_get_rmrs(struct fwnode_handle *iommu_fwnode, struct list_head *list) { + if (!is_of_node(iommu_fwnode)) + return iort_iommu_get_rmrs(iommu_fwnode, list); + return -EINVAL; } EXPORT_SYMBOL(iommu_dma_get_rmrs); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 1a12baa58e40..e8c45fa59531 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -39,6 +39,8 @@ const struct iommu_ops *iort_iommu_configure_id(struct device *dev, const u32 *id_in); int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head); phys_addr_t acpi_iort_dma_get_max_cpu_address(void); +int iort_iommu_get_rmrs(struct fwnode_handle *iommu_fwnode, + struct list_head *list); #else static inline void acpi_iort_init(void) { } static inline u32 iort_msi_map_id(struct device *dev, u32 id) @@ -59,6 +61,11 @@ int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) static inline phys_addr_t acpi_iort_dma_get_max_cpu_address(void) { return PHYS_ADDR_MAX; } + +static inline +int iort_iommu_get_rmrs(struct fwnode_handle *iommu_fwnode, + struct list_head *list) +{ return -ENODEV; } #endif #endif /* __ACPI_IORT_H__ */ From patchwork Thu May 13 13:45:46 2021 Content-Type: text/plain; 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Received: from szxga05-in.huawei.com ([45.249.212.191]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lhBfu-00BHsz-Mz for linux-arm-kernel@lists.infradead.org; Thu, 13 May 2021 13:46:52 +0000 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FgtDS1vrVzsRJ1; Thu, 13 May 2021 21:44:08 +0800 (CST) Received: from A2006125610.china.huawei.com (10.47.81.63) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Thu, 13 May 2021 21:46:40 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , , Subject: [PATCH v4 4/8] iommu/arm-smmu-v3: Introduce strtab init helper Date: Thu, 13 May 2021 14:45:46 +0100 Message-ID: <20210513134550.2117-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> References: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.81.63] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210513_064650_941067_73E6667F X-CRM114-Status: GOOD ( 12.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce a helper to check the sid range and to init the l2 strtab entries(bypass). This will be useful when we have to initialize the l2 strtab with bypass for RMR SIDs. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +++++++++++---------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 54b2f27b81d4..754bad6092c1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2369,6 +2369,19 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) return sid < limit; } +static int arm_smmu_init_sid_strtab(struct arm_smmu_device *smmu, u32 sid) +{ + /* Check the SIDs are in range of the SMMU and our stream table */ + if (!arm_smmu_sid_in_range(smmu, sid)) + return -ERANGE; + + /* Ensure l2 strtab is initialised */ + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) + return arm_smmu_init_l2_strtab(smmu, sid); + + return 0; +} + static int arm_smmu_insert_master(struct arm_smmu_device *smmu, struct arm_smmu_master *master) { @@ -2392,20 +2405,9 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu, new_stream->id = sid; new_stream->master = master; - /* - * Check the SIDs are in range of the SMMU and our stream table - */ - if (!arm_smmu_sid_in_range(smmu, sid)) { - ret = -ERANGE; + ret = arm_smmu_init_sid_strtab(smmu, sid); + if (ret) break; - } - - /* Ensure l2 strtab is initialised */ - if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { - ret = arm_smmu_init_l2_strtab(smmu, sid); - if (ret) - break; - } /* Insert into SID tree */ new_node = &(smmu->streams.rb_node); From patchwork Thu May 13 13:45:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 12255861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3A12C433B4 for ; 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bh=dLcifpRbpGOOo5l2uyzsGI7847e1bclNUfLumTjbuCo=; b=Kh5rJrPFgtqt4kAWXcxglU5zGU C9aZkPtzicynJnCJFVGI22LzWzdEL8lPQ2BC7wSJSzNVw/e/K6u7VbKZCAWMKWXfWOPubPUZTDH5v ZlRyAyMbzPVqL+JdgYIWxwL41o6iCTLy4kMKCxtiplEShl3cT8pOJL+y5ToUCxhoD78MyofH1rhMo V9/SAxbQ1DlX0VMdeFl0oO+WQIJJmFtBCztIiMs5EzX39zcdqq0yEUn538MxsYBKfq49HxO97ydDD V3w5yyWpFdjNkST0I5+gnlVBzu2HiIHIcASz65M2bIfoUMYZUrJFdOyQzSaG0fIFaP3naiT6/G3yl LWB72ziA==; Received: from szxga04-in.huawei.com ([45.249.212.190]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lhBfz-00BHtX-Nb for linux-arm-kernel@lists.infradead.org; Thu, 13 May 2021 13:46:57 +0000 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FgtDY1Rg6z16LjG; Thu, 13 May 2021 21:44:13 +0800 (CST) Received: from A2006125610.china.huawei.com (10.47.81.63) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Thu, 13 May 2021 21:46:47 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , , Subject: [PATCH v4 5/8] =?utf-8?q?iommu/arm-smmu-v3=3A_Add_bypass_flag_to?= =?utf-8?q?=C2=A0arm=5Fsmmu=5Fwrite=5Fstrtab=5Fent=28=29?= Date: Thu, 13 May 2021 14:45:47 +0100 Message-ID: <20210513134550.2117-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> References: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.81.63] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210513_064655_950734_A0F920DD X-CRM114-Status: GOOD ( 10.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org By default, disable_bypass is set and any dev without an iommu domain installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to install CFG_BYPASS STE for specific SIDs. This will be useful in follow up patch to install bypass for IORT RMR SIDs. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 754bad6092c1..f9195b740f48 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1174,7 +1174,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) } static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, - __le64 *dst) + __le64 *dst, bool bypass) { /* * This is hideously complicated, but we only really care about @@ -1245,7 +1245,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, /* Bypass/fault */ if (!smmu_domain || !(s1_cfg || s2_cfg)) { - if (!smmu_domain && disable_bypass) + if (!smmu_domain && disable_bypass && !bypass) val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); @@ -1320,7 +1320,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent) unsigned int i; for (i = 0; i < nent; ++i) { - arm_smmu_write_strtab_ent(NULL, -1, strtab); + arm_smmu_write_strtab_ent(NULL, -1, strtab, false); strtab += STRTAB_STE_DWORDS; } } @@ -2097,7 +2097,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master) if (j < i) continue; - arm_smmu_write_strtab_ent(master, sid, step); + arm_smmu_write_strtab_ent(master, sid, step, false); } } From patchwork Thu May 13 13:45:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 12255855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5539DC433B4 for ; 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This is to keep any ongoing traffic associated with these devices alive when we enable/reset SMMUv3 during probe(). Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 33 +++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f9195b740f48..c2d2e65b9856 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3574,6 +3574,36 @@ static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t start, return devm_ioremap_resource(dev, &res); } +static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) +{ + struct list_head rmr_list; + struct iommu_rmr *e; + int ret; + + INIT_LIST_HEAD(&rmr_list); + if (iommu_dma_get_rmrs(dev_fwnode(smmu->dev), &rmr_list)) + return; + + /* + * Since, we don't have a mechanism to differentiate the RMR + * SIDs that has an ongoing live stream, install bypass STEs + * for all the reported ones.  + */ + list_for_each_entry(e, &rmr_list, list) { + __le64 *step; + + ret = arm_smmu_init_sid_strtab(smmu, e->sid); + if (ret) { + dev_err(smmu->dev, "RMR bypass(0x%x) failed\n", + e->sid); + continue; + } + + step = arm_smmu_get_step_for_sid(smmu, e->sid); + arm_smmu_write_strtab_ent(NULL, e->sid, step, true); + } +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -3657,6 +3687,9 @@ static int arm_smmu_device_probe(struct platform_device *pdev) /* Record our private device structure */ platform_set_drvdata(pdev, smmu); + /* Check for RMRs and install bypass STEs if any */ + arm_smmu_rmr_install_bypass_ste(smmu); + /* Reset the device */ ret = arm_smmu_device_reset(smmu, bypass); if (ret) From patchwork Thu May 13 13:45:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 12255857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 893E1C43460 for ; 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This is to keep any ongoing traffic associated with these devices alive when we enable/reset SMMU during probe(). Signed-off-by: Jon Nettleton Signed-off-by: Steven Price Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 64 +++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 6f72c4d208ca..f67aeb30b5ef 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -2042,6 +2042,66 @@ err_reset_platform_ops: __maybe_unused; return err; } +static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu) +{ + struct list_head rmr_list; + struct iommu_rmr *e; + int i, cnt = 0; + u32 smr; + u32 reg; + + INIT_LIST_HEAD(&rmr_list); + if (iommu_dma_get_rmrs(dev_fwnode(smmu->dev), &rmr_list)) + return; + + reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); + + if ((reg & ARM_SMMU_sCR0_USFCFG) && !(reg & ARM_SMMU_sCR0_CLIENTPD)) { + /* + * SMMU is already enabled and disallowing bypass, so preserve + * the existing SMRs + */ + for (i = 0; i < smmu->num_mapping_groups; i++) { + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); + if (!FIELD_GET(ARM_SMMU_SMR_VALID, smr)) + continue; + smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); + smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); + smmu->smrs[i].valid = true; + } + } + + list_for_each_entry(e, &rmr_list, list) { + u32 sid = e->sid; + + i = arm_smmu_find_sme(smmu, sid, ~0); + if (i < 0) + continue; + if (smmu->s2crs[i].count == 0) { + smmu->smrs[i].id = sid; + smmu->smrs[i].mask = ~0; + smmu->smrs[i].valid = true; + } + smmu->s2crs[i].count++; + smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = 0xff; + + cnt++; + } + + if ((reg & ARM_SMMU_sCR0_USFCFG) && !(reg & ARM_SMMU_sCR0_CLIENTPD)) { + /* Remove the valid bit for unused SMRs */ + for (i = 0; i < smmu->num_mapping_groups; i++) { + if (smmu->s2crs[i].count == 0) + smmu->smrs[i].valid = false; + } + } + + dev_notice(smmu->dev, "\tpreserved %d boot mapping%s\n", cnt, + cnt == 1 ? "" : "s"); +} + static int arm_smmu_device_probe(struct platform_device *pdev) { struct resource *res; @@ -2168,6 +2228,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, smmu); + + /* Check for RMRs and install bypass SMRs if any */ + arm_smmu_rmr_install_bypass_smr(smmu); + arm_smmu_device_reset(smmu); arm_smmu_test_smr_masks(smmu); From patchwork Thu May 13 13:45:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 12255865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A1C4C433B4 for ; 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Signed-off-by: Shameer Kolothum --- drivers/iommu/dma-iommu.c | 66 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 2d9caf548a32..6838caf3e8ff 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -174,22 +174,78 @@ void iommu_put_dma_cookie(struct iommu_domain *domain) } EXPORT_SYMBOL(iommu_put_dma_cookie); +static bool iommu_dma_dev_has_rmr(struct iommu_fwspec *fwspec, + struct iommu_rmr *e) +{ + int i; + + for (i = 0; i < fwspec->num_ids; i++) { + if (e->sid == fwspec->ids[i]) + return true; + } + + return false; +} + +static void iommu_dma_get_rmr_resv_regions(struct device *dev, + struct list_head *list) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct list_head rmr_list; + struct iommu_rmr *rmr; + + INIT_LIST_HEAD(&rmr_list); + if (iommu_dma_get_rmrs(fwspec->iommu_fwnode, &rmr_list)) + return; + + if (dev_is_pci(dev)) { + struct pci_dev *pdev = to_pci_dev(dev); + struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus); + + if (!host->preserve_config) + return; + } + + list_for_each_entry(rmr, &rmr_list, list) { + int prot = IOMMU_READ | IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + enum iommu_resv_type type; + + if (!iommu_dma_dev_has_rmr(fwspec, rmr)) + continue; + + if (rmr->flags & IOMMU_RMR_REMAP_PERMITTED) + type = IOMMU_RESV_DIRECT_RELAXABLE; + else + type = IOMMU_RESV_DIRECT; + + region = iommu_alloc_resv_region(rmr->base_address, + rmr->length, prot, + type); + if (!region) + return; + + list_add_tail(®ion->list, list); + } +} /** * iommu_dma_get_resv_regions - Reserved region driver helper * @dev: Device from iommu_get_resv_regions() * @list: Reserved region list from iommu_get_resv_regions() * * IOMMU drivers can use this to implement their .get_resv_regions callback - * for general non-IOMMU-specific reservations. Currently, this covers GICv3 - * ITS region reservation on ACPI based ARM platforms that may require HW MSI - * reservation. + * for general non-IOMMU-specific reservations. Currently this covers, + * -GICv3 ITS region reservation on ACPI based ARM platforms that may + * require HW MSI reservation. + * -Any ACPI IORT RMR memory range reservations (IORT spec rev E.b) */ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) { - if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode)) + if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode)) { iort_iommu_msi_get_resv_regions(dev, list); - + iommu_dma_get_rmr_resv_regions(dev, list); + } } EXPORT_SYMBOL(iommu_dma_get_resv_regions);