From patchwork Sat May 15 13:12:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12259825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63C9CC43461 for ; Sat, 15 May 2021 13:12:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42A3661377 for ; Sat, 15 May 2021 13:12:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229704AbhEONNl (ORCPT ); Sat, 15 May 2021 09:13:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229888AbhEONNg (ORCPT ); Sat, 15 May 2021 09:13:36 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24447C06174A for ; Sat, 15 May 2021 06:12:22 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id s25so1700861ljo.11 for ; Sat, 15 May 2021 06:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A+eo1IuREtAfwJtXMuCkTNE64eCLQjhkQV6wBXbLi/8=; b=F9zQbhL6o6UNZTfh/8Y6OhIAjBxFrUTDRaR3caCzlEXoQjFGMP8vK3SZOmK72ONIDi N0B5fNZ5xft0xpsmJl9azKI+xki9rU4sO1koujkWPnKcQsna8HRrk5mqzDFjsbGtfvcG pYTjASIhwWSOOTngKjVHTV8KGrOvHasj+G463XNSPcrDoxlQ8kTo1W2snOaEqTf9v6cH 0xghqLZLdFeDRwFbnmj/A/wtpGPCe9H+CIVD4E1g5ZaV3lrmtZ5aYVjwedFks1Y3DdVf bvJkXQrpU//UdUotbqClhT+ftW7CkXSGlIrBw5mAn8li8C+h+dQphdD8CCI+ztJGrNEa OBEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A+eo1IuREtAfwJtXMuCkTNE64eCLQjhkQV6wBXbLi/8=; b=R73fLy/Cx/Qmr7zfVQv+nqyjj1jCVYpJLs6TEQnGfaL7hQzPSTEugmqUUWn20/lCGn sOwDI9KLaU8Kt0lSNgV5xieLpVpMHSKR9GTpurRV7yVuYiEM4r98P/MsKoktBY93+jNt sswD2+CiJtwVktxh1JAbgnN9gQw3JpFSTXjicfXj5gsVsXFA4jAl0lR9kQD47Xxnrtiu upg+4nshwFtVgblbnI2DfbWIchCUgRf/qpYPeCAH8Y29ho6rpRERVbSV8TWt000//NT4 ZGPHuS3n/vojNTG+lBBBdwStOgC21qRbquDUamtCeoVKg6Ot3kfbVOnpQLtmFXajHKvG BuTA== X-Gm-Message-State: AOAM5339tyxCBdIirbfJtbU1cf/11bMhOQGPLPtLnbt68LDOtVu0GEl9 5bxDxzH1CHGPEuNonyxz3zZ96A== X-Google-Smtp-Source: ABdhPJxTxPDWIM8XWIQpBdMA1KGw4O2/agYmUrbuKwulIa5QOEj6TMgAwhaBfg0cH69mIVl3pmvQtw== X-Received: by 2002:a2e:8086:: with SMTP id i6mr32384059ljg.135.1621084340563; Sat, 15 May 2021 06:12:20 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id m4sm2061865ljp.9.2021.05.15.06.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 May 2021 06:12:19 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 1/8] arm64: dts: qcom: sc7180: assign DSI clock source parents Date: Sat, 15 May 2021 16:12:10 +0300 Message-Id: <20210515131217.1540412-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> References: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 1ea3344ab62c..4e8708cce1cc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3090,6 +3090,9 @@ dsi0: dsi@ae94000 { "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7180_CX>; From patchwork Sat May 15 13:12:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12259821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B2F8C433ED for ; Sat, 15 May 2021 13:12:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 58F52613BE for ; Sat, 15 May 2021 13:12:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229964AbhEONNj (ORCPT ); Sat, 15 May 2021 09:13:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229704AbhEONNg (ORCPT ); Sat, 15 May 2021 09:13:36 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB66CC061756 for ; Sat, 15 May 2021 06:12:22 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id u20so1740438ljo.4 for ; Sat, 15 May 2021 06:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UAQa/+HPZGb9w4gbaD2aOLSU7WxeXPAw6Cdwe97w/Q4=; b=LK6g4A0NilcaAHff+ttJNs/qFPnktIfTdiF89lyBfOvLftuDjoisE5gve2JJsITkfY VfSgKwVjizr4B1B0tgcrePgBnO5tQh2wEfG6HiFN2fvBHLHovX4T11MvrEVO1SoQWoLK 0k/V81rmXl5cbFVQqyyvseuMY4oZ4Xr4SZ71WSX7xZLcUy0bZUfJ6iZ4rXPcZ9JgHZRK hE59Rs1JeIwKD07+ec4z1Luf7UFyVqcEkFC3LCk+QcICWsDzQsxmYPO4HXrxcbQ8VxrA CeOqh09FUaImoFFxugcxXS0WLaCCJ8XAvr6Qj+fOtEqE5/CQGnkfnepvKMkOlzhRps1/ 0ilA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UAQa/+HPZGb9w4gbaD2aOLSU7WxeXPAw6Cdwe97w/Q4=; b=kM6SNVgcs3etoHvSIdApU9J8a8U7PP+E7D1nbYFb7ZNF8W3em2dNowbZgpPHqxHP/K 91SxCEpnQVkHWit7x8NWaMTJLWhDUET9UIjXLC7p1R1PpbV1mpDUZsdOMJh1wDWSKAKZ fz6w6r9o6mXm5WsPgG13tmjdejsnBjWcdTlflKnxXbnBZ2zpxbEOzZZQ+eTCayi2H5X0 CTZv1/7Uld2Az48ImMk7yrd2gJQzcHwyrOEmd00WKTJFoafpLnVI6YG1LsJjIgI2QNCF LJdt919PscU8FIYd6Yj1hckpvoKef5BjPM3noSkzYncrfw0k/vux/Ft/8UYcyIFFZfkt VpKg== X-Gm-Message-State: AOAM5333Bi/yzK2iM8q88hcFbtgSRi1olDMTNrfzdBnrR6lh/jcEEGBR wDjdik3opy654cdQfkvEAowqsw== X-Google-Smtp-Source: ABdhPJxaxa+zajdzVBlvdxIo/Ac8CmlGKHUUOZbnQCs3Jm96rjmWcTjgHXEGCnSdJmVrfaRAdukI6g== X-Received: by 2002:a2e:a607:: with SMTP id v7mr41423565ljp.81.1621084341426; Sat, 15 May 2021 06:12:21 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id m4sm2061865ljp.9.2021.05.15.06.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 May 2021 06:12:21 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 2/8] arm64: dts: qcom: sdm845: assign DSI clock source parents Date: Sat, 15 May 2021 16:12:11 +0300 Message-Id: <20210515131217.1540412-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> References: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 454f794af547..2166549382c1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4113,6 +4113,9 @@ dsi0: dsi@ae94000 { "core", "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; @@ -4179,6 +4182,9 @@ dsi1: dsi@ae96000 { "core", "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; From patchwork Sat May 15 13:12:12 2021 Content-Type: text/plain; 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Sat, 15 May 2021 06:12:21 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 3/8] arm64: dts: qcom: sdm845-mtp: assign DSI clock source parents Date: Sat, 15 May 2021 16:12:12 +0300 Message-Id: <20210515131217.1540412-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> References: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 1372fe8601f5..9e550e3ad678 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -413,6 +413,9 @@ &dsi1 { qcom,dual-dsi-mode; + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + ports { port@1 { endpoint { From patchwork Sat May 15 13:12:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12259827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28FA0C43462 for ; Sat, 15 May 2021 13:12:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04F5A613BE for ; Sat, 15 May 2021 13:12:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230252AbhEONNm (ORCPT ); Sat, 15 May 2021 09:13:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229571AbhEONNi (ORCPT ); Sat, 15 May 2021 09:13:38 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67672C061760 for ; Sat, 15 May 2021 06:12:24 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id c15so1719824ljr.7 for ; Sat, 15 May 2021 06:12:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VZ0geH6BqMBlmbQ30iyES93D0PKaLEePFxddTMOy9xQ=; b=Uv6MazY9XNEXNTEONgwnHe0oOXRGuDo0b633L9TmxeAMKHNMdElnpQxc2m11x78BYE XsSy6yfX2SvK/BgTmrn1J+s2NUMEJKYmoAxYLf0D7JeJl92OGakS/oSEAvVKZL3QByMH gGy/uqAHHAoHnQ9vV8Jt2YXxwltQIDRHJpHVVmtHtoYp5lq04Wo12RpE5dRWHsxR7g9G l+gsLXbS7ua17YOR02tNw+LaE0KKvchfT5UG7lQoFraNajjYCWV4bPbLhP83+qzT0Gzs WyJWGBHoB+CfG9QtkL4n+ROCRcCEn7iR3E33bnvly3COciRyXZSSOiHN+9Wz5ibSU96O QoAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VZ0geH6BqMBlmbQ30iyES93D0PKaLEePFxddTMOy9xQ=; b=eZU8w809PQ4BJDjxGwmaYbVswdM34yRnoYakYSqzcfV1xCQf4ipVYVcKEREAzV+5UL /AmalVPKQJQ3dOSab+S4H0s/e0BfdHBUmR46VS3Nyh+/PbbRHyVJdXo5p0xRA6aHcPl+ IgM6E6JrzSCeefUzZFYXggIJ/NpQeos2RI7Z1nQU7gtVxuOTMLB+OWiECObKQELr0arV K/yPIshv5O1OAM4gNViHJku01Lcr66ZennjnuHHjRzHRAFzuiVlwac3R3pBAlKB9krCs z+HHjQFBW08q3dg8R7398LUeZfJ+cJF6k7t6fzXqxaEHm1KK6wvW+QwKnWJ9fXpy2wbe JBQA== X-Gm-Message-State: AOAM5337cfmGKIEqrVnKVoB2+zt9AgYVZzIwotJy4JMc9TLua8PHBoIE v1qASINtrZtEQ2u/+bsDiDs2jg== X-Google-Smtp-Source: ABdhPJx4JwjGkjf2+ERd282AHyLy6MuHHJwWFDuM056vtz6NXfDNDM1FmZ5MZCoMRJln3Seq4wYFqw== X-Received: by 2002:a2e:7a0f:: with SMTP id v15mr41795283ljc.242.1621084342980; Sat, 15 May 2021 06:12:22 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id m4sm2061865ljp.9.2021.05.15.06.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 May 2021 06:12:22 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 4/8] arm64: dts: qcom: sm8250: assign DSI clock source parents Date: Sat, 15 May 2021 16:12:13 +0300 Message-Id: <20210515131217.1540412-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> References: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 947e1accae3a..b6ed94497e8a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2445,6 +2445,9 @@ dsi0: dsi@ae94000 { "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; @@ -2512,6 +2515,9 @@ dsi1: dsi@ae96000 { "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; From patchwork Sat May 15 13:12:14 2021 Content-Type: text/plain; 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Sat, 15 May 2021 06:12:23 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 5/8] drm/msm/dsi: stop setting clock parents manually Date: Sat, 15 May 2021 16:12:14 +0300 Message-Id: <20210515131217.1540412-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> References: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no reason to set clock parents manually, use device tree to assign DSI/display clock parents to DSI PHY clocks. Dropping this manual setup allows us to drop repeating code and to move registration of hw clock providers to generic place. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/dsi/dsi.h | 2 -- drivers/gpu/drm/msm/dsi/dsi_host.c | 51 --------------------------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 11 ------ 4 files changed, 69 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 7abfeab08165..2041980548f0 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -169,8 +169,6 @@ void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, struct msm_dsi_phy_shared_timings *shared_timing); void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, enum msm_dsi_phy_usecase uc); -int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, - struct clk **byte_clk_provider, struct clk **pixel_clk_provider); void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy); int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 8a10e4343281..1f444101e551 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -2223,57 +2223,6 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, wmb(); } -int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, - struct msm_dsi_phy *src_phy) -{ - struct msm_dsi_host *msm_host = to_msm_dsi_host(host); - struct clk *byte_clk_provider, *pixel_clk_provider; - int ret; - - ret = msm_dsi_phy_get_clk_provider(src_phy, - &byte_clk_provider, &pixel_clk_provider); - if (ret) { - pr_info("%s: can't get provider from pll, don't set parent\n", - __func__); - return 0; - } - - ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); - if (ret) { - pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - - ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); - if (ret) { - pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - - if (msm_host->dsi_clk_src) { - ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); - if (ret) { - pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - } - - if (msm_host->esc_clk_src) { - ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); - if (ret) { - pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", - __func__, ret); - goto exit; - } - } - -exit: - return ret; -} - void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index cd016576e8c5..12efc8c69046 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -78,7 +78,6 @@ static int dsi_mgr_setup_components(int id) return ret; msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); - ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy); } else if (!other_dsi) { ret = 0; } else { @@ -105,10 +104,6 @@ static int dsi_mgr_setup_components(int id) MSM_DSI_PHY_MASTER); msm_dsi_phy_set_usecase(clk_slave_dsi->phy, MSM_DSI_PHY_SLAVE); - ret = msm_dsi_host_set_src_pll(msm_dsi->host, clk_master_dsi->phy); - if (ret) - return ret; - ret = msm_dsi_host_set_src_pll(other_dsi->host, clk_master_dsi->phy); } return ret; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index ff7f2ec42030..f2b5e0f63a16 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -835,17 +835,6 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, phy->usecase = uc; } -int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, - struct clk **byte_clk_provider, struct clk **pixel_clk_provider) -{ - if (byte_clk_provider) - *byte_clk_provider = phy->provided_clocks->hws[DSI_BYTE_PLL_CLK]->clk; - if (pixel_clk_provider) - *pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk; - - return 0; -} - void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy) { if (phy->cfg->ops.save_pll_state) { From patchwork Sat May 15 13:12:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12259833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62617C433B4 for ; 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Sat, 15 May 2021 06:12:24 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id m4sm2061865ljp.9.2021.05.15.06.12.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 May 2021 06:12:24 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 6/8] drm/msm/dsi: phy: use of_device_get_match_data Date: Sat, 15 May 2021 16:12:15 +0300 Message-Id: <20210515131217.1540412-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> References: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use of_device_get_match-data() instead of of_match_node(). Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index f2b5e0f63a16..feaeb34b7071 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -625,17 +625,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) { struct msm_dsi_phy *phy; struct device *dev = &pdev->dev; - const struct of_device_id *match; int ret; phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); if (!phy) return -ENOMEM; - match = of_match_node(dsi_phy_dt_match, dev->of_node); - if (!match) - return -ENODEV; - phy->provided_clocks = devm_kzalloc(dev, struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS), GFP_KERNEL); @@ -644,7 +639,10 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) phy->provided_clocks->num = NUM_PROVIDED_CLKS; - phy->cfg = match->data; + phy->cfg = of_device_get_match_data(&pdev->dev); + if (!phy->cfg) + return -ENODEV; + phy->pdev = pdev; phy->id = dsi_phy_get_id(phy); From patchwork Sat May 15 13:12:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12259835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFCEFC43600 for ; Sat, 15 May 2021 13:12:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C149F613BE for ; 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Sat, 15 May 2021 06:12:25 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 7/8] drm/msm/dsi: drop msm_dsi_phy_get_shared_timings Date: Sat, 15 May 2021 16:12:16 +0300 Message-Id: <20210515131217.1540412-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> References: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Instead of fetching shared timing through an extra function call, get them directly from msm_dsi_phy_enable. This would allow removing phy timings from the struct msm_dsi_phy in the next patch. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/dsi/dsi.h | 5 ++--- drivers/gpu/drm/msm/dsi/dsi_manager.c | 3 +-- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 13 +++++-------- 3 files changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 2041980548f0..84f9900ff878 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -163,10 +163,9 @@ struct msm_dsi_phy_clk_request { void msm_dsi_phy_driver_register(void); void msm_dsi_phy_driver_unregister(void); int msm_dsi_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req); + struct msm_dsi_phy_clk_request *clk_req, + struct msm_dsi_phy_shared_timings *shared_timings); void msm_dsi_phy_disable(struct msm_dsi_phy *phy); -void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, - struct msm_dsi_phy_shared_timings *shared_timing); void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, enum msm_dsi_phy_usecase uc); void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 12efc8c69046..88d56a2bc8ab 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -118,8 +118,7 @@ static int enable_phy(struct msm_dsi *msm_dsi, msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req, is_dual_dsi); - ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req); - msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings); + ret = msm_dsi_phy_enable(msm_dsi->phy, &clk_req, shared_timings); return ret; } diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index feaeb34b7071..53a02c02dd6e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -752,7 +752,8 @@ void __exit msm_dsi_phy_driver_unregister(void) } int msm_dsi_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req) + struct msm_dsi_phy_clk_request *clk_req, + struct msm_dsi_phy_shared_timings *shared_timings) { struct device *dev = &phy->pdev->dev; int ret; @@ -780,6 +781,9 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, goto phy_en_fail; } + memcpy(shared_timings, &phy->timing.shared_timings, + sizeof(*shared_timings)); + /* * Resetting DSI PHY silently changes its PLL registers to reset status, * which will confuse clock driver and result in wrong output rate of @@ -819,13 +823,6 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy) dsi_phy_disable_resource(phy); } -void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy, - struct msm_dsi_phy_shared_timings *shared_timings) -{ - memcpy(shared_timings, &phy->timing.shared_timings, - sizeof(*shared_timings)); -} - void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy, enum msm_dsi_phy_usecase uc) { From patchwork Sat May 15 13:12:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12259837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AD5FC43461 for ; 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Sat, 15 May 2021 06:12:26 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id m4sm2061865ljp.9.2021.05.15.06.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 May 2021 06:12:25 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 8/8] drm/msm/dsi: remove msm_dsi_dphy_timing from msm_dsi_phy Date: Sat, 15 May 2021 16:12:17 +0300 Message-Id: <20210515131217.1540412-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> References: <20210515131217.1540412-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove struct msm_dsi_dphy_timing field from the struct msm_dsi_phy. There is no need to store them. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 18 ++++++++++++++---- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 10 ++++++++-- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 11 +++-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 11 +++-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 10 ++-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 12 ++++-------- .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 10 ++-------- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 13 ++++--------- 8 files changed, 40 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 53a02c02dd6e..47145cab6b55 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -453,6 +453,8 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, tmax = 255; timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin; + timing->bitclk_rate = bit_rate; + DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d", timing->shared_timings.clk_pre, timing->shared_timings.clk_post, timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit, @@ -756,6 +758,7 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, struct msm_dsi_phy_shared_timings *shared_timings) { struct device *dev = &phy->pdev->dev; + struct msm_dsi_dphy_timing timing; int ret; if (!phy || !phy->cfg->ops.enable) @@ -775,15 +778,22 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, goto reg_en_fail; } - ret = phy->cfg->ops.enable(phy, clk_req); + if (!phy->cfg->ops.dphy_timing_calc || + phy->cfg->ops.dphy_timing_calc(&timing, clk_req)) { + DRM_DEV_ERROR(&phy->pdev->dev, + "%s: D-PHY timing calculation failed\n", __func__); + return -EINVAL; + } + + memcpy(shared_timings, &timing.shared_timings, + sizeof(*shared_timings)); + + ret = phy->cfg->ops.enable(phy, &timing); if (ret) { DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret); goto phy_en_fail; } - memcpy(shared_timings, &phy->timing.shared_timings, - sizeof(*shared_timings)); - /* * Resetting DSI PHY silently changes its PLL registers to reset status, * which will confuse clock driver and result in wrong output rate of diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 94a77ac364d3..9ba03a242d24 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -17,10 +17,14 @@ #define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); } #define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); } +struct msm_dsi_dphy_timing; + struct msm_dsi_phy_ops { int (*pll_init)(struct msm_dsi_phy *phy); - int (*enable)(struct msm_dsi_phy *phy, + int (*dphy_timing_calc)(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); + int (*enable)(struct msm_dsi_phy *phy, + struct msm_dsi_dphy_timing *timing); void (*disable)(struct msm_dsi_phy *phy); void (*save_pll_state)(struct msm_dsi_phy *phy); int (*restore_pll_state)(struct msm_dsi_phy *phy); @@ -73,6 +77,9 @@ struct msm_dsi_dphy_timing { u32 hs_prep_dly_ckln; u8 hs_halfbyte_en; u8 hs_halfbyte_en_ckln; + + /* For PHY v4 only */ + unsigned long bitclk_rate; }; #define DSI_BYTE_PLL_CLK 0 @@ -90,7 +97,6 @@ struct msm_dsi_phy { struct clk *ahb_clk; struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; - struct msm_dsi_dphy_timing timing; const struct msm_dsi_phy_cfg *cfg; enum msm_dsi_phy_usecase usecase; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 34bc93548fcf..bc838ee4f9b9 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -789,24 +789,17 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) } static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req) + struct msm_dsi_dphy_timing *timing) { int ret; u32 status; u32 const delay_us = 5; u32 const timeout_us = 1000; - struct msm_dsi_dphy_timing *timing = &phy->timing; void __iomem *base = phy->base; u32 data; DBG(""); - if (msm_dsi_dphy_timing_calc_v3(timing, clk_req)) { - DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); - return -EINVAL; - } - if (dsi_phy_hw_v3_0_is_pll_on(phy)) pr_warn("PLL turned on before configuring PHY\n"); @@ -929,6 +922,7 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc_v3, .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, .pll_init = dsi_pll_10nm_init, @@ -950,6 +944,7 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc_v3, .enable = dsi_10nm_phy_enable, .disable = dsi_10nm_phy_disable, .pll_init = dsi_pll_10nm_init, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 65d68eb9e3cb..5372d741bc76 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -939,9 +939,8 @@ static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, } static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req) + struct msm_dsi_dphy_timing *timing) { - struct msm_dsi_dphy_timing *timing = &phy->timing; u32 data; int i; int ret; @@ -949,12 +948,6 @@ static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, void __iomem *lane_base = phy->lane_base; u32 glbl_test_ctrl; - if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) { - DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); - return -EINVAL; - } - data = 0x1c; if (phy->usecase != MSM_DSI_PHY_STANDALONE) data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32); @@ -1032,6 +1025,7 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc_v2, .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, .pll_init = dsi_pll_14nm_init, @@ -1053,6 +1047,7 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc_v2, .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, .pll_init = dsi_pll_14nm_init, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index e96d789aea18..b953fb19e292 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -64,9 +64,8 @@ static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) } static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req) + struct msm_dsi_dphy_timing *timing) { - struct msm_dsi_dphy_timing *timing = &phy->timing; int i; void __iomem *base = phy->base; u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00}; @@ -74,12 +73,6 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, DBG(""); - if (msm_dsi_dphy_timing_calc(timing, clk_req)) { - DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); - return -EINVAL; - } - dsi_20nm_phy_regulator_ctrl(phy, true); dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); @@ -138,6 +131,7 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc, .enable = dsi_20nm_phy_enable, .disable = dsi_20nm_phy_disable, }, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 3304acda2165..e39801d309ed 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -699,21 +699,14 @@ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) } static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req) + struct msm_dsi_dphy_timing *timing) { - struct msm_dsi_dphy_timing *timing = &phy->timing; int i; void __iomem *base = phy->base; u32 val; DBG(""); - if (msm_dsi_dphy_timing_calc(timing, clk_req)) { - DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); - return -EINVAL; - } - dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff); dsi_28nm_phy_regulator_ctrl(phy, true); @@ -775,6 +768,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc, .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, .pll_init = dsi_pll_28nm_init, @@ -796,6 +790,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc, .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, .pll_init = dsi_pll_28nm_init, @@ -817,6 +812,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc, .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, .pll_init = dsi_pll_28nm_init, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 86e40a0d41a3..7d50822085f2 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -590,19 +590,12 @@ static void dsi_28nm_phy_lane_config(struct msm_dsi_phy *phy) } static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req) + struct msm_dsi_dphy_timing *timing) { - struct msm_dsi_dphy_timing *timing = &phy->timing; void __iomem *base = phy->base; DBG(""); - if (msm_dsi_dphy_timing_calc(timing, clk_req)) { - DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); - return -EINVAL; - } - dsi_28nm_phy_regulator_init(phy); dsi_phy_write(base + REG_DSI_28nm_8960_PHY_LDO_CTRL, 0x04); @@ -654,6 +647,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc, .enable = dsi_28nm_phy_enable, .disable = dsi_28nm_phy_disable, .pll_init = dsi_pll_28nm_8960_init, diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index e76ce40a12ab..993508268a15 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -802,13 +802,12 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) } static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, - struct msm_dsi_phy_clk_request *clk_req) + struct msm_dsi_dphy_timing *timing) { int ret; u32 status; u32 const delay_us = 5; u32 const timeout_us = 1000; - struct msm_dsi_dphy_timing *timing = &phy->timing; void __iomem *base = phy->base; bool less_than_1500_mhz; u32 vreg_ctrl_0, glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0; @@ -817,12 +816,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, DBG(""); - if (msm_dsi_dphy_timing_calc_v4(timing, clk_req)) { - DRM_DEV_ERROR(&phy->pdev->dev, - "%s: D-PHY timing calculation failed\n", __func__); - return -EINVAL; - } - if (dsi_phy_hw_v4_0_is_pll_on(phy)) pr_warn("PLL turned on before configuring PHY\n"); @@ -838,7 +831,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* TODO: CPHY enable path (this is for DPHY only) */ /* Alter PHY configurations if data rate less than 1.5GHZ*/ - less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); + less_than_1500_mhz = (timing->bitclk_rate <= 1500000000); if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; @@ -965,6 +958,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc_v4, .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, .pll_init = dsi_pll_7nm_init, @@ -987,6 +981,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { }, }, .ops = { + .dphy_timing_calc = msm_dsi_dphy_timing_calc_v4, .enable = dsi_7nm_phy_enable, .disable = dsi_7nm_phy_disable, .pll_init = dsi_pll_7nm_init,