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[14.201.155.8]) by smtp.gmail.com with ESMTPSA id l6sm8938955pgc.68.2021.05.16.19.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 May 2021 19:46:58 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [PATCH] target/ppc: Implement ISA v3.1 wait variants Date: Mon, 17 May 2021 12:46:51 +1000 Message-Id: <20210517024651.2200837-1-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=npiggin@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Nicholas Piggin , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" ISA v3.1 adds new variations of wait, specified by the WC field. These are not compatible with the wait 0 implementation, because they add additional conditions that cause the processor to resume, which can cause software to hang or run very slowly. Add the new wait variants with a trivial no-op implementation, which is allowed, as explained in comments: software must not depend on any particular architected WC condition having caused resumption of execution, therefore a no-op implementation is architecturally correct. Signed-off-by: Nicholas Piggin --- Implementing cpu_relax() in Linux with wait 2,0 (pause_short) causes a hang on boot without this patch. target/ppc/translate.c | 39 +++++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a6381208a5..80db450cab 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3619,12 +3619,39 @@ static void gen_sync(DisasContext *ctx) /* wait */ static void gen_wait(DisasContext *ctx) { - TCGv_i32 t0 = tcg_const_i32(1); - tcg_gen_st_i32(t0, cpu_env, - -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); - tcg_temp_free_i32(t0); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); + uint32_t wc = (ctx->opcode >> 21) & 3; + + /* + * wait 0 waits for an exception to occur. + */ + if (wc == 0) { + TCGv_i32 t0 = tcg_const_i32(1); + tcg_gen_st_i32(t0, cpu_env, + -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); + tcg_temp_free_i32(t0); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); + } + + /* + * Other wait types must not wait until an exception occurs because + * ignoring their other wake-up conditions could cause a hang. + * + * wait 1 (waitrsv) waits for an exception or a reservation to be lost. + * This can happen for implementation specific reasons, so it can be + * implemented as a no-op. + * + * wait 2 waits for an exception or an amount of time to pass. This is + * implementation specific so it can be implemented as a no-op. + * + * wait 3 is reserved, so it may be implemented as a no-op. + * + * ISA v3.1 does allow for execution to resume "in the rare case of + * an implementation-dependent event", so in any case software must + * not depend on the architected resumption condition to become + * true, so no-op implementations are architecturally correct (if + * suboptimal). + */ } #if defined(TARGET_PPC64)