From patchwork Tue May 18 19:53:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12265569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6112DC433B4 for ; Tue, 18 May 2021 19:53:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D56E6124C for ; Tue, 18 May 2021 19:53:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1D56E6124C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 931046EC7A; Tue, 18 May 2021 19:53:13 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7D7EF6EC77 for ; Tue, 18 May 2021 19:53:11 +0000 (UTC) IronPort-SDR: JSvAiLuDxWi3Lp8BAZYpbEcCjkRn1NeMNdu9YvwBnrF4mut0ix9HPwQtaBvmwZIiSDv8cTSdFF u2KrrVtSg8NQ== X-IronPort-AV: E=McAfee;i="6200,9189,9988"; a="197715527" X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="197715527" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2021 12:53:09 -0700 IronPort-SDR: Kyu5iLt5Lio7Bt8zode+YFcmrC/DpRqjDytSisCaEzKWi3c45q+nWjuToUD09ytQ54IaSzoMON cNiMZkKM60pg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="394989485" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga006.jf.intel.com with ESMTP; 18 May 2021 12:53:09 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 18 May 2021 12:53:05 -0700 Message-Id: <20210518195309.4917-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20210518195309.4917-1-anusha.srivatsa@intel.com> References: <20210518195309.4917-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [CI 1/5] drm/i915/dmc: s/intel_csr/intel_dmc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No functional change. v2: Chchpatch fixes. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 170 +++++++++--------- .../drm/i915/display/intel_display_debugfs.c | 14 +- .../drm/i915/display/intel_display_power.c | 52 +++--- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/i915_gpu_error.c | 8 +- 6 files changed, 125 insertions(+), 125 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 26a922d34263..a22339ebdffd 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -312,7 +312,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) */ void intel_csr_load_program(struct drm_i915_private *dev_priv) { - u32 *payload = dev_priv->csr.dmc_payload; + u32 *payload = dev_priv->dmc.dmc_payload; u32 i, fw_size; if (!HAS_CSR(dev_priv)) { @@ -321,13 +321,13 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) return; } - if (!dev_priv->csr.dmc_payload) { + if (!dev_priv->dmc.dmc_payload) { drm_err(&dev_priv->drm, "Tried to program CSR with empty payload\n"); return; } - fw_size = dev_priv->csr.dmc_fw_size; + fw_size = dev_priv->dmc.dmc_fw_size; assert_rpm_wakelock_held(&dev_priv->runtime_pm); preempt_disable(); @@ -338,12 +338,12 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) preempt_enable(); - for (i = 0; i < dev_priv->csr.mmio_count; i++) { - intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i], - dev_priv->csr.mmiodata[i]); + for (i = 0; i < dev_priv->dmc.mmio_count; i++) { + intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i], + dev_priv->dmc.mmiodata[i]); } - dev_priv->csr.dc_state = 0; + dev_priv->dmc.dc_state = 0; gen9_set_dc_state_debugmask(dev_priv); } @@ -392,7 +392,7 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info, return dmc_offset; } -static u32 parse_csr_fw_dmc(struct intel_csr *csr, +static u32 parse_csr_fw_dmc(struct intel_dmc *dmc, const struct intel_dmc_header_base *dmc_header, size_t rem_size) { @@ -401,8 +401,8 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr, u32 mmio_count, mmio_count_max; u8 *payload; - BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || - ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); + BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || + ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); /* * Check if we can access common fields, we will checkc again below @@ -464,10 +464,10 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr, mmioaddr[i]); return 0; } - csr->mmioaddr[i] = _MMIO(mmioaddr[i]); - csr->mmiodata[i] = mmiodata[i]; + dmc->mmioaddr[i] = _MMIO(mmioaddr[i]); + dmc->mmiodata[i] = mmiodata[i]; } - csr->mmio_count = mmio_count; + dmc->mmio_count = mmio_count; rem_size -= header_len_bytes; @@ -476,20 +476,20 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr, if (rem_size < payload_size) goto error_truncated; - if (payload_size > csr->max_fw_size) { + if (payload_size > dmc->max_fw_size) { DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size); return 0; } - csr->dmc_fw_size = dmc_header->fw_size; + dmc->dmc_fw_size = dmc_header->fw_size; - csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL); - if (!csr->dmc_payload) { + dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL); + if (!dmc->dmc_payload) { DRM_ERROR("Memory allocation failed for dmc payload\n"); return 0; } payload = (u8 *)(dmc_header) + header_len_bytes; - memcpy(csr->dmc_payload, payload, payload_size); + memcpy(dmc->dmc_payload, payload, payload_size); return header_len_bytes + payload_size; @@ -499,7 +499,7 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr, } static u32 -parse_csr_fw_package(struct intel_csr *csr, +parse_csr_fw_package(struct intel_dmc *dmc, const struct intel_package_header *package_header, const struct stepping_info *si, size_t rem_size) @@ -558,7 +558,7 @@ parse_csr_fw_package(struct intel_csr *csr, } /* Return number of bytes parsed or 0 on error */ -static u32 parse_csr_fw_css(struct intel_csr *csr, +static u32 parse_csr_fw_css(struct intel_dmc *dmc, struct intel_css_header *css_header, size_t rem_size) { @@ -575,18 +575,18 @@ static u32 parse_csr_fw_css(struct intel_csr *csr, return 0; } - if (csr->required_version && - css_header->version != csr->required_version) { + if (dmc->required_version && + css_header->version != dmc->required_version) { DRM_INFO("Refusing to load DMC firmware v%u.%u," " please use v%u.%u\n", CSR_VERSION_MAJOR(css_header->version), CSR_VERSION_MINOR(css_header->version), - CSR_VERSION_MAJOR(csr->required_version), - CSR_VERSION_MINOR(csr->required_version)); + CSR_VERSION_MAJOR(dmc->required_version), + CSR_VERSION_MINOR(dmc->required_version)); return 0; } - csr->version = css_header->version; + dmc->version = css_header->version; return sizeof(struct intel_css_header); } @@ -597,7 +597,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv, struct intel_css_header *css_header; struct intel_package_header *package_header; struct intel_dmc_header_base *dmc_header; - struct intel_csr *csr = &dev_priv->csr; + struct intel_dmc *dmc = &dev_priv->dmc; const struct stepping_info *si = intel_get_stepping_info(dev_priv); u32 readcount = 0; u32 r; @@ -607,7 +607,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv, /* Extract CSS Header information */ css_header = (struct intel_css_header *)fw->data; - r = parse_csr_fw_css(csr, css_header, fw->size); + r = parse_csr_fw_css(dmc, css_header, fw->size); if (!r) return; @@ -615,7 +615,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv, /* Extract Package Header information */ package_header = (struct intel_package_header *)&fw->data[readcount]; - r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount); + r = parse_csr_fw_package(dmc, package_header, si, fw->size - readcount); if (!r) return; @@ -623,20 +623,20 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv, /* Extract dmc_header information */ dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount]; - parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount); + parse_csr_fw_dmc(dmc, dmc_header, fw->size - readcount); } static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv) { - drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref); - dev_priv->csr.wakeref = + drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); + dev_priv->dmc.wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); } static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv) { intel_wakeref_t wakeref __maybe_unused = - fetch_and_zero(&dev_priv->csr.wakeref); + fetch_and_zero(&dev_priv->dmc.wakeref); intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); } @@ -644,28 +644,28 @@ static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv) static void csr_load_work_fn(struct work_struct *work) { struct drm_i915_private *dev_priv; - struct intel_csr *csr; + struct intel_dmc *dmc; const struct firmware *fw = NULL; - dev_priv = container_of(work, typeof(*dev_priv), csr.work); - csr = &dev_priv->csr; + dev_priv = container_of(work, typeof(*dev_priv), dmc.work); + dmc = &dev_priv->dmc; - request_firmware(&fw, dev_priv->csr.fw_path, dev_priv->drm.dev); + request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev); parse_csr_fw(dev_priv, fw); - if (dev_priv->csr.dmc_payload) { + if (dev_priv->dmc.dmc_payload) { intel_csr_load_program(dev_priv); intel_csr_runtime_pm_put(dev_priv); drm_info(&dev_priv->drm, "Finished loading DMC firmware %s (v%u.%u)\n", - dev_priv->csr.fw_path, CSR_VERSION_MAJOR(csr->version), - CSR_VERSION_MINOR(csr->version)); + dev_priv->dmc.fw_path, CSR_VERSION_MAJOR(dmc->version), + CSR_VERSION_MINOR(dmc->version)); } else { drm_notice(&dev_priv->drm, "Failed to load DMC firmware %s." " Disabling runtime power management.\n", - csr->fw_path); + dmc->fw_path); drm_notice(&dev_priv->drm, "DMC firmware homepage: %s", INTEL_UC_FIRMWARE_URL); } @@ -682,9 +682,9 @@ static void csr_load_work_fn(struct work_struct *work) */ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) { - struct intel_csr *csr = &dev_priv->csr; + struct intel_dmc *dmc = &dev_priv->dmc; - INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); + INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn); if (!HAS_CSR(dev_priv)) return; @@ -700,70 +700,70 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) intel_csr_runtime_pm_get(dev_priv); if (IS_ALDERLAKE_S(dev_priv)) { - csr->fw_path = ADLS_CSR_PATH; - csr->required_version = ADLS_CSR_VERSION_REQUIRED; - csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + dmc->fw_path = ADLS_CSR_PATH; + dmc->required_version = ADLS_CSR_VERSION_REQUIRED; + dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE; } else if (IS_DG1(dev_priv)) { - csr->fw_path = DG1_CSR_PATH; - csr->required_version = DG1_CSR_VERSION_REQUIRED; - csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + dmc->fw_path = DG1_CSR_PATH; + dmc->required_version = DG1_CSR_VERSION_REQUIRED; + dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE; } else if (IS_ROCKETLAKE(dev_priv)) { - csr->fw_path = RKL_CSR_PATH; - csr->required_version = RKL_CSR_VERSION_REQUIRED; - csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + dmc->fw_path = RKL_CSR_PATH; + dmc->required_version = RKL_CSR_VERSION_REQUIRED; + dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE; } else if (DISPLAY_VER(dev_priv) >= 12) { - csr->fw_path = TGL_CSR_PATH; - csr->required_version = TGL_CSR_VERSION_REQUIRED; - csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + dmc->fw_path = TGL_CSR_PATH; + dmc->required_version = TGL_CSR_VERSION_REQUIRED; + dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE; } else if (DISPLAY_VER(dev_priv) == 11) { - csr->fw_path = ICL_CSR_PATH; - csr->required_version = ICL_CSR_VERSION_REQUIRED; - csr->max_fw_size = ICL_CSR_MAX_FW_SIZE; + dmc->fw_path = ICL_CSR_PATH; + dmc->required_version = ICL_CSR_VERSION_REQUIRED; + dmc->max_fw_size = ICL_CSR_MAX_FW_SIZE; } else if (IS_CANNONLAKE(dev_priv)) { - csr->fw_path = CNL_CSR_PATH; - csr->required_version = CNL_CSR_VERSION_REQUIRED; - csr->max_fw_size = CNL_CSR_MAX_FW_SIZE; + dmc->fw_path = CNL_CSR_PATH; + dmc->required_version = CNL_CSR_VERSION_REQUIRED; + dmc->max_fw_size = CNL_CSR_MAX_FW_SIZE; } else if (IS_GEMINILAKE(dev_priv)) { - csr->fw_path = GLK_CSR_PATH; - csr->required_version = GLK_CSR_VERSION_REQUIRED; - csr->max_fw_size = GLK_CSR_MAX_FW_SIZE; + dmc->fw_path = GLK_CSR_PATH; + dmc->required_version = GLK_CSR_VERSION_REQUIRED; + dmc->max_fw_size = GLK_CSR_MAX_FW_SIZE; } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { - csr->fw_path = KBL_CSR_PATH; - csr->required_version = KBL_CSR_VERSION_REQUIRED; - csr->max_fw_size = KBL_CSR_MAX_FW_SIZE; + dmc->fw_path = KBL_CSR_PATH; + dmc->required_version = KBL_CSR_VERSION_REQUIRED; + dmc->max_fw_size = KBL_CSR_MAX_FW_SIZE; } else if (IS_SKYLAKE(dev_priv)) { - csr->fw_path = SKL_CSR_PATH; - csr->required_version = SKL_CSR_VERSION_REQUIRED; - csr->max_fw_size = SKL_CSR_MAX_FW_SIZE; + dmc->fw_path = SKL_CSR_PATH; + dmc->required_version = SKL_CSR_VERSION_REQUIRED; + dmc->max_fw_size = SKL_CSR_MAX_FW_SIZE; } else if (IS_BROXTON(dev_priv)) { - csr->fw_path = BXT_CSR_PATH; - csr->required_version = BXT_CSR_VERSION_REQUIRED; - csr->max_fw_size = BXT_CSR_MAX_FW_SIZE; + dmc->fw_path = BXT_CSR_PATH; + dmc->required_version = BXT_CSR_VERSION_REQUIRED; + dmc->max_fw_size = BXT_CSR_MAX_FW_SIZE; } if (dev_priv->params.dmc_firmware_path) { if (strlen(dev_priv->params.dmc_firmware_path) == 0) { - csr->fw_path = NULL; + dmc->fw_path = NULL; drm_info(&dev_priv->drm, - "Disabling CSR firmware and runtime PM\n"); + "Disabling DMC firmware and runtime PM\n"); return; } - csr->fw_path = dev_priv->params.dmc_firmware_path; + dmc->fw_path = dev_priv->params.dmc_firmware_path; /* Bypass version check for firmware override. */ - csr->required_version = 0; + dmc->required_version = 0; } - if (csr->fw_path == NULL) { + if (!dmc->fw_path) { drm_dbg_kms(&dev_priv->drm, - "No known CSR firmware for platform, disabling runtime PM\n"); + "No known DMC firmware for platform, disabling runtime PM\n"); return; } - drm_dbg_kms(&dev_priv->drm, "Loading %s\n", csr->fw_path); - schedule_work(&dev_priv->csr.work); + drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path); + schedule_work(&dev_priv->dmc.work); } /** @@ -779,10 +779,10 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) if (!HAS_CSR(dev_priv)) return; - flush_work(&dev_priv->csr.work); + flush_work(&dev_priv->dmc.work); /* Drop the reference held in case DMC isn't loaded. */ - if (!dev_priv->csr.dmc_payload) + if (!dev_priv->dmc.dmc_payload) intel_csr_runtime_pm_put(dev_priv); } @@ -802,7 +802,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) * Reacquire the reference to keep RPM disabled in case DMC isn't * loaded. */ - if (!dev_priv->csr.dmc_payload) + if (!dev_priv->dmc.dmc_payload) intel_csr_runtime_pm_get(dev_priv); } @@ -819,7 +819,7 @@ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) return; intel_csr_ucode_suspend(dev_priv); - drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref); + drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); - kfree(dev_priv->csr.dmc_payload); + kfree(dev_priv->dmc.dmc_payload); } diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d77a0ab5cacf..a875f3c9b358 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -532,24 +532,24 @@ static int i915_dmc_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); intel_wakeref_t wakeref; - struct intel_csr *csr; + struct intel_dmc *dmc; i915_reg_t dc5_reg, dc6_reg = {}; if (!HAS_CSR(dev_priv)) return -ENODEV; - csr = &dev_priv->csr; + dmc = &dev_priv->dmc; wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); - seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); - seq_printf(m, "path: %s\n", csr->fw_path); + seq_printf(m, "fw loaded: %s\n", yesno(dmc->dmc_payload)); + seq_printf(m, "path: %s\n", dmc->fw_path); - if (!csr->dmc_payload) + if (!dmc->dmc_payload) goto out; - seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), - CSR_VERSION_MINOR(csr->version)); + seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(dmc->version), + CSR_VERSION_MINOR(dmc->version)); if (DISPLAY_VER(dev_priv) >= 12) { if (IS_DGFX(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 54c6d65011ee..0a05d0f90f28 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -829,8 +829,8 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) drm_dbg_kms(&dev_priv->drm, "Resetting DC state tracking from %02x to %02x\n", - dev_priv->csr.dc_state, val); - dev_priv->csr.dc_state = val; + dev_priv->dmc.dc_state, val); + dev_priv->dmc.dc_state = val; } /** @@ -865,8 +865,8 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) return; if (drm_WARN_ON_ONCE(&dev_priv->drm, - state & ~dev_priv->csr.allowed_dc_mask)) - state &= dev_priv->csr.allowed_dc_mask; + state & ~dev_priv->dmc.allowed_dc_mask)) + state &= dev_priv->dmc.allowed_dc_mask; val = intel_de_read(dev_priv, DC_STATE_EN); mask = gen9_dc_mask(dev_priv); @@ -874,16 +874,16 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) val & mask, state); /* Check if DMC is ignoring our DC state requests */ - if ((val & mask) != dev_priv->csr.dc_state) + if ((val & mask) != dev_priv->dmc.dc_state) drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n", - dev_priv->csr.dc_state, val & mask); + dev_priv->dmc.dc_state, val & mask); val &= ~mask; val |= state; gen9_write_dc_state(dev_priv, val); - dev_priv->csr.dc_state = val & mask; + dev_priv->dmc.dc_state = val & mask; } static u32 @@ -902,7 +902,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv, if (target_dc_state != states[i]) continue; - if (dev_priv->csr.allowed_dc_mask & target_dc_state) + if (dev_priv->dmc.allowed_dc_mask & target_dc_state) break; target_dc_state = states[i + 1]; @@ -1016,7 +1016,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, state = sanitize_target_dc_state(dev_priv, state); - if (state == dev_priv->csr.target_dc_state) + if (state == dev_priv->dmc.target_dc_state) goto unlock; dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv, @@ -1028,7 +1028,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, if (!dc_off_enabled) power_well->desc->ops->enable(dev_priv, power_well); - dev_priv->csr.target_dc_state = state; + dev_priv->dmc.target_dc_state = state; if (!dc_off_enabled) power_well->desc->ops->disable(dev_priv, power_well); @@ -1181,7 +1181,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) { struct intel_cdclk_config cdclk_config = {}; - if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) { + if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) { tgl_disable_dc3co(dev_priv); return; } @@ -1220,10 +1220,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - if (!dev_priv->csr.dmc_payload) + if (!dev_priv->dmc.dmc_payload) return; - switch (dev_priv->csr.target_dc_state) { + switch (dev_priv->dmc.target_dc_state) { case DC_STATE_EN_DC3CO: tgl_enable_dc3co(dev_priv); break; @@ -5090,10 +5090,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) dev_priv->params.disable_power_well = sanitize_disable_power_well_option(dev_priv, dev_priv->params.disable_power_well); - dev_priv->csr.allowed_dc_mask = + dev_priv->dmc.allowed_dc_mask = get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc); - dev_priv->csr.target_dc_state = + dev_priv->dmc.target_dc_state = sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); BUILD_BUG_ON(POWER_DOMAIN_NUM > 64); @@ -5573,7 +5573,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, gen9_dbuf_enable(dev_priv); - if (resume && dev_priv->csr.dmc_payload) + if (resume && dev_priv->dmc.dmc_payload) intel_csr_load_program(dev_priv); } @@ -5640,7 +5640,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume gen9_dbuf_enable(dev_priv); - if (resume && dev_priv->csr.dmc_payload) + if (resume && dev_priv->dmc.dmc_payload) intel_csr_load_program(dev_priv); } @@ -5706,7 +5706,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume /* 6. Enable DBUF */ gen9_dbuf_enable(dev_priv); - if (resume && dev_priv->csr.dmc_payload) + if (resume && dev_priv->dmc.dmc_payload) intel_csr_load_program(dev_priv); } @@ -5863,7 +5863,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, if (DISPLAY_VER(dev_priv) >= 12) tgl_bw_buddy_init(dev_priv); - if (resume && dev_priv->csr.dmc_payload) + if (resume && dev_priv->dmc.dmc_payload) intel_csr_load_program(dev_priv); /* Wa_14011508470 */ @@ -6222,9 +6222,9 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, * resources as required and also enable deeper system power states * that would be blocked if the firmware was inactive. */ - if (!(i915->csr.allowed_dc_mask & DC_STATE_EN_DC9) && + if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) && suspend_mode == I915_DRM_SUSPEND_IDLE && - i915->csr.dmc_payload) { + i915->dmc.dmc_payload) { intel_display_power_flush_work(i915); intel_power_domains_verify_state(i915); return; @@ -6414,19 +6414,19 @@ void intel_display_power_resume(struct drm_i915_private *i915) if (DISPLAY_VER(i915) >= 11) { bxt_disable_dc9(i915); icl_display_core_init(i915, true); - if (i915->csr.dmc_payload) { - if (i915->csr.allowed_dc_mask & + if (i915->dmc.dmc_payload) { + if (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) skl_enable_dc6(i915); - else if (i915->csr.allowed_dc_mask & + else if (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) gen9_enable_dc5(i915); } } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { bxt_disable_dc9(i915); bxt_display_core_init(i915, true); - if (i915->csr.dmc_payload && - (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) + if (i915->dmc.dmc_payload && + (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) gen9_enable_dc5(i915); } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { hsw_disable_pc8(i915); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index acaf3d459821..0905386b2270 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -669,7 +669,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, if (crtc_state->enable_psr2_sel_fetch) return; - if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) + if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) return; /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9aee6a045590..3c9f6bbb5dd7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -328,7 +328,7 @@ struct drm_i915_display_funcs { void (*read_luts)(struct intel_crtc_state *crtc_state); }; -struct intel_csr { +struct intel_dmc { struct work_struct work; const char *fw_path; u32 required_version; @@ -824,7 +824,7 @@ struct drm_i915_private { struct intel_wopcm wopcm; - struct intel_csr csr; + struct intel_dmc dmc; struct intel_gmbus gmbus[GMBUS_NUM_PINS]; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 99ca242ec13b..03d1221de13b 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -789,13 +789,13 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, err_printf(m, "IOMMU enabled?: %d\n", error->iommu); if (HAS_CSR(m->i915)) { - struct intel_csr *csr = &m->i915->csr; + struct intel_dmc *dmc = &m->i915->dmc; err_printf(m, "DMC loaded: %s\n", - yesno(csr->dmc_payload != NULL)); + yesno(dmc->dmc_payload)); err_printf(m, "DMC fw version: %d.%d\n", - CSR_VERSION_MAJOR(csr->version), - CSR_VERSION_MINOR(csr->version)); + CSR_VERSION_MAJOR(dmc->version), + CSR_VERSION_MINOR(dmc->version)); } err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); From patchwork Tue May 18 19:53:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12265573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91544C433ED for ; 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a="197715531" X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="197715531" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2021 12:53:10 -0700 IronPort-SDR: 4bxBsdlmrd/FNOZQqWeTHzPKqqLG6ywnq+HpT1w8gkyQKqj+Cx06JlFbjjsaMeVr+1CX9sXkLH 3j4X/e8unVWw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="394989486" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga006.jf.intel.com with ESMTP; 18 May 2021 12:53:09 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 18 May 2021 12:53:06 -0700 Message-Id: <20210518195309.4917-3-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20210518195309.4917-1-anusha.srivatsa@intel.com> References: <20210518195309.4917-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [CI 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No functional change. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 12 ++++++------ drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 4 ++-- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_device_info.h | 2 +- 7 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index a22339ebdffd..5ed286dc6720 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -315,9 +315,9 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) u32 *payload = dev_priv->dmc.dmc_payload; u32 i, fw_size; - if (!HAS_CSR(dev_priv)) { + if (!HAS_DMC(dev_priv)) { drm_err(&dev_priv->drm, - "No CSR support available for this platform\n"); + "No DMC support available for this platform\n"); return; } @@ -686,7 +686,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn); - if (!HAS_CSR(dev_priv)) + if (!HAS_DMC(dev_priv)) return; /* @@ -776,7 +776,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) */ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) { - if (!HAS_CSR(dev_priv)) + if (!HAS_DMC(dev_priv)) return; flush_work(&dev_priv->dmc.work); @@ -795,7 +795,7 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) */ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) { - if (!HAS_CSR(dev_priv)) + if (!HAS_DMC(dev_priv)) return; /* @@ -815,7 +815,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) */ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) { - if (!HAS_CSR(dev_priv)) + if (!HAS_DMC(dev_priv)) return; intel_csr_ucode_suspend(dev_priv); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index a875f3c9b358..6cd7f8c1724f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -535,7 +535,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) struct intel_dmc *dmc; i915_reg_t dc5_reg, dc6_reg = {}; - if (!HAS_CSR(dev_priv)) + if (!HAS_DMC(dev_priv)) return -ENODEV; dmc = &dev_priv->dmc; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3c9f6bbb5dd7..469783003309 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1662,7 +1662,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) -#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) +#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc) #define HAS_MSO(i915) (INTEL_GEN(i915) >= 12) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 03d1221de13b..06828ff90ccf 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -788,7 +788,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, err_printf(m, "IOMMU enabled?: %d\n", error->iommu); - if (HAS_CSR(m->i915)) { + if (HAS_DMC(m->i915)) { struct intel_dmc *dmc = &m->i915->dmc; err_printf(m, "DMC loaded: %s\n", diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 574881c0e339..97c98f4fb265 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -643,7 +643,7 @@ static const struct intel_device_info chv_info = { GEN8_FEATURES, \ GEN(9), \ GEN9_DEFAULT_PAGE_SIZES, \ - .display.has_csr = 1, \ + .display.has_dmc = 1, \ .has_gt_uc = 1, \ .display.has_hdcp = 1, \ .display.has_ipc = 1, \ @@ -698,7 +698,7 @@ static const struct intel_device_info skl_gt4_info = { .display.has_psr = 1, \ .display.has_psr_hw_tracking = 1, \ .has_runtime_pm = 1, \ - .display.has_csr = 1, \ + .display.has_dmc = 1, \ .has_rc6 = 1, \ .has_rps = true, \ .display.has_dp_mst = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 8cb58a238c68..e16599b67b83 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -353,7 +353,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) info->display.has_fbc = 0; if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) - info->display.has_csr = 0; + info->display.has_dmc = 0; if (INTEL_GEN(dev_priv) >= 10 && (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index e98b36959736..1390fad5ec06 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -141,7 +141,7 @@ enum intel_ppgtt_type { #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ - func(has_csr); \ + func(has_dmc); \ func(has_ddi); \ func(has_dp_mst); \ func(has_dsb); \ From patchwork Tue May 18 19:53:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12265567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0DD1C43460 for ; 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a="197715528" X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="197715528" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2021 12:53:09 -0700 IronPort-SDR: 3BZ0usez796Na1aP67a62vFpHXicJlX4vvnYKb6nxB5bQwnvpsmYbTMkQSpMwba5ebJSz07WYK WBT7GBzJ0opg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="394989487" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga006.jf.intel.com with ESMTP; 18 May 2021 12:53:09 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 18 May 2021 12:53:07 -0700 Message-Id: <20210518195309.4917-4-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20210518195309.4917-1-anusha.srivatsa@intel.com> References: <20210518195309.4917-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Rename all occurences of CSR_* with DMC_* Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 167 +++++++++--------- drivers/gpu/drm/i915/display/intel_csr.h | 6 +- .../drm/i915/display/intel_display_debugfs.c | 16 +- .../drm/i915/display/intel_display_power.c | 14 +- drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- drivers/gpu/drm/i915/i915_reg.h | 28 +-- 6 files changed, 117 insertions(+), 118 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 5ed286dc6720..f2124796ce77 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -30,10 +30,9 @@ #include "intel_de.h" /** - * DOC: csr support for dmc + * DOC: DMC firmware support * - * Display Context Save and Restore (CSR) firmware support added from gen9 - * onwards to drive newly added DMC (Display microcontroller) in display + * From gen9 onwards we have newly added DMC (Display microcontroller) in display * engine to save and restore the state of display engine when it enter into * low-power state and comes back to normal. */ @@ -44,55 +43,55 @@ __stringify(major) "_" \ __stringify(minor) ".bin" -#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE +#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE -#define ADLS_CSR_PATH DMC_PATH(adls, 2, 01) -#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1) -MODULE_FIRMWARE(ADLS_CSR_PATH); +#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) +#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) +MODULE_FIRMWARE(ADLS_DMC_PATH); -#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02) -#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) -MODULE_FIRMWARE(DG1_CSR_PATH); +#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) +#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +MODULE_FIRMWARE(DG1_DMC_PATH); -#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02) -#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) -MODULE_FIRMWARE(RKL_CSR_PATH); +#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02) +#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +MODULE_FIRMWARE(RKL_DMC_PATH); -#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08) -#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8) -MODULE_FIRMWARE(TGL_CSR_PATH); +#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08) +#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) +MODULE_FIRMWARE(TGL_DMC_PATH); -#define ICL_CSR_PATH DMC_PATH(icl, 1, 09) -#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9) -#define ICL_CSR_MAX_FW_SIZE 0x6000 -MODULE_FIRMWARE(ICL_CSR_PATH); +#define ICL_DMC_PATH DMC_PATH(icl, 1, 09) +#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) +#define ICL_DMC_MAX_FW_SIZE 0x6000 +MODULE_FIRMWARE(ICL_DMC_PATH); -#define CNL_CSR_PATH DMC_PATH(cnl, 1, 07) -#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) -#define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(CNL_CSR_PATH); +#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07) +#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) +#define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(CNL_DMC_PATH); -#define GLK_CSR_PATH DMC_PATH(glk, 1, 04) -#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define GLK_CSR_MAX_FW_SIZE 0x4000 -MODULE_FIRMWARE(GLK_CSR_PATH); +#define GLK_DMC_PATH DMC_PATH(glk, 1, 04) +#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) +#define GLK_DMC_MAX_FW_SIZE 0x4000 +MODULE_FIRMWARE(GLK_DMC_PATH); -#define KBL_CSR_PATH DMC_PATH(kbl, 1, 04) -#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) -#define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(KBL_CSR_PATH); +#define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) +#define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) +#define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(KBL_DMC_PATH); -#define SKL_CSR_PATH DMC_PATH(skl, 1, 27) -#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27) -#define SKL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE -MODULE_FIRMWARE(SKL_CSR_PATH); +#define SKL_DMC_PATH DMC_PATH(skl, 1, 27) +#define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) +#define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE +MODULE_FIRMWARE(SKL_DMC_PATH); -#define BXT_CSR_PATH DMC_PATH(bxt, 1, 07) -#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) -#define BXT_CSR_MAX_FW_SIZE 0x3000 -MODULE_FIRMWARE(BXT_CSR_PATH); +#define BXT_DMC_PATH DMC_PATH(bxt, 1, 07) +#define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) +#define BXT_DMC_MAX_FW_SIZE 0x3000 +MODULE_FIRMWARE(BXT_DMC_PATH); -#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF +#define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF #define PACKAGE_MAX_FW_INFO_ENTRIES 20 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 #define DMC_V1_MAX_MMIO_COUNT 8 @@ -333,7 +332,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) preempt_disable(); for (i = 0; i < fw_size; i++) - intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i), + intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i), payload[i]); preempt_enable(); @@ -357,7 +356,7 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info, const struct stepping_info *si, u8 package_ver) { - u32 dmc_offset = CSR_DEFAULT_FW_OFFSET; + u32 dmc_offset = DMC_DEFAULT_FW_OFFSET; unsigned int i; for (i = 0; i < num_entries; i++) { @@ -458,8 +457,8 @@ static u32 parse_csr_fw_dmc(struct intel_dmc *dmc, } for (i = 0; i < mmio_count; i++) { - if (mmioaddr[i] < CSR_MMIO_START_RANGE || - mmioaddr[i] > CSR_MMIO_END_RANGE) { + if (mmioaddr[i] < DMC_MMIO_START_RANGE || + mmioaddr[i] > DMC_MMIO_END_RANGE) { DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n", mmioaddr[i]); return 0; @@ -543,7 +542,7 @@ parse_csr_fw_package(struct intel_dmc *dmc, ((u8 *)package_header + sizeof(*package_header)); dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si, package_header->header_ver); - if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { + if (dmc_offset == DMC_DEFAULT_FW_OFFSET) { DRM_ERROR("DMC firmware not supported for %c stepping\n", si->stepping); return 0; @@ -579,10 +578,10 @@ static u32 parse_csr_fw_css(struct intel_dmc *dmc, css_header->version != dmc->required_version) { DRM_INFO("Refusing to load DMC firmware v%u.%u," " please use v%u.%u\n", - CSR_VERSION_MAJOR(css_header->version), - CSR_VERSION_MINOR(css_header->version), - CSR_VERSION_MAJOR(dmc->required_version), - CSR_VERSION_MINOR(dmc->required_version)); + DMC_VERSION_MAJOR(css_header->version), + DMC_VERSION_MINOR(css_header->version), + DMC_VERSION_MAJOR(dmc->required_version), + DMC_VERSION_MINOR(dmc->required_version)); return 0; } @@ -659,8 +658,8 @@ static void csr_load_work_fn(struct work_struct *work) drm_info(&dev_priv->drm, "Finished loading DMC firmware %s (v%u.%u)\n", - dev_priv->dmc.fw_path, CSR_VERSION_MAJOR(dmc->version), - CSR_VERSION_MINOR(dmc->version)); + dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version), + DMC_VERSION_MINOR(dmc->version)); } else { drm_notice(&dev_priv->drm, "Failed to load DMC firmware %s." @@ -690,57 +689,57 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) return; /* - * Obtain a runtime pm reference, until CSR is loaded, to avoid entering + * Obtain a runtime pm reference, until DMC is loaded, to avoid entering * runtime-suspend. * * On error, we return with the rpm wakeref held to prevent runtime - * suspend as runtime suspend *requires* a working CSR for whatever + * suspend as runtime suspend *requires* a working DMC for whatever * reason. */ intel_csr_runtime_pm_get(dev_priv); if (IS_ALDERLAKE_S(dev_priv)) { - dmc->fw_path = ADLS_CSR_PATH; - dmc->required_version = ADLS_CSR_VERSION_REQUIRED; - dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + dmc->fw_path = ADLS_DMC_PATH; + dmc->required_version = ADLS_DMC_VERSION_REQUIRED; + dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; } else if (IS_DG1(dev_priv)) { - dmc->fw_path = DG1_CSR_PATH; - dmc->required_version = DG1_CSR_VERSION_REQUIRED; - dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + dmc->fw_path = DG1_DMC_PATH; + dmc->required_version = DG1_DMC_VERSION_REQUIRED; + dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; } else if (IS_ROCKETLAKE(dev_priv)) { - dmc->fw_path = RKL_CSR_PATH; - dmc->required_version = RKL_CSR_VERSION_REQUIRED; - dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + dmc->fw_path = RKL_DMC_PATH; + dmc->required_version = RKL_DMC_VERSION_REQUIRED; + dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; } else if (DISPLAY_VER(dev_priv) >= 12) { - dmc->fw_path = TGL_CSR_PATH; - dmc->required_version = TGL_CSR_VERSION_REQUIRED; - dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + dmc->fw_path = TGL_DMC_PATH; + dmc->required_version = TGL_DMC_VERSION_REQUIRED; + dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; } else if (DISPLAY_VER(dev_priv) == 11) { - dmc->fw_path = ICL_CSR_PATH; - dmc->required_version = ICL_CSR_VERSION_REQUIRED; - dmc->max_fw_size = ICL_CSR_MAX_FW_SIZE; + dmc->fw_path = ICL_DMC_PATH; + dmc->required_version = ICL_DMC_VERSION_REQUIRED; + dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; } else if (IS_CANNONLAKE(dev_priv)) { - dmc->fw_path = CNL_CSR_PATH; - dmc->required_version = CNL_CSR_VERSION_REQUIRED; - dmc->max_fw_size = CNL_CSR_MAX_FW_SIZE; + dmc->fw_path = CNL_DMC_PATH; + dmc->required_version = CNL_DMC_VERSION_REQUIRED; + dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE; } else if (IS_GEMINILAKE(dev_priv)) { - dmc->fw_path = GLK_CSR_PATH; - dmc->required_version = GLK_CSR_VERSION_REQUIRED; - dmc->max_fw_size = GLK_CSR_MAX_FW_SIZE; + dmc->fw_path = GLK_DMC_PATH; + dmc->required_version = GLK_DMC_VERSION_REQUIRED; + dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { - dmc->fw_path = KBL_CSR_PATH; - dmc->required_version = KBL_CSR_VERSION_REQUIRED; - dmc->max_fw_size = KBL_CSR_MAX_FW_SIZE; + dmc->fw_path = KBL_DMC_PATH; + dmc->required_version = KBL_DMC_VERSION_REQUIRED; + dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; } else if (IS_SKYLAKE(dev_priv)) { - dmc->fw_path = SKL_CSR_PATH; - dmc->required_version = SKL_CSR_VERSION_REQUIRED; - dmc->max_fw_size = SKL_CSR_MAX_FW_SIZE; + dmc->fw_path = SKL_DMC_PATH; + dmc->required_version = SKL_DMC_VERSION_REQUIRED; + dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; } else if (IS_BROXTON(dev_priv)) { - dmc->fw_path = BXT_CSR_PATH; - dmc->required_version = BXT_CSR_VERSION_REQUIRED; - dmc->max_fw_size = BXT_CSR_MAX_FW_SIZE; + dmc->fw_path = BXT_DMC_PATH; + dmc->required_version = BXT_DMC_VERSION_REQUIRED; + dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; } if (dev_priv->params.dmc_firmware_path) { diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h index 03c64f8af7ab..984e9fb250f8 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.h +++ b/drivers/gpu/drm/i915/display/intel_csr.h @@ -8,9 +8,9 @@ struct drm_i915_private; -#define CSR_VERSION(major, minor) ((major) << 16 | (minor)) -#define CSR_VERSION_MAJOR(version) ((version) >> 16) -#define CSR_VERSION_MINOR(version) ((version) & 0xffff) +#define DMC_VERSION(major, minor) ((major) << 16 | (minor)) +#define DMC_VERSION_MAJOR(version) ((version) >> 16) +#define DMC_VERSION_MINOR(version) ((version) & 0xffff) void intel_csr_ucode_init(struct drm_i915_private *i915); void intel_csr_load_program(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 6cd7f8c1724f..e43abdf0e3d9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -548,8 +548,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused) if (!dmc->dmc_payload) goto out; - seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(dmc->version), - CSR_VERSION_MINOR(dmc->version)); + seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), + DMC_VERSION_MINOR(dmc->version)); if (DISPLAY_VER(dev_priv) >= 12) { if (IS_DGFX(dev_priv)) { @@ -568,10 +568,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused) seq_printf(m, "DC3CO count: %d\n", intel_de_read(dev_priv, DMC_DEBUG3)); } else { - dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : - SKL_CSR_DC3_DC5_COUNT; + dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT : + SKL_DMC_DC3_DC5_COUNT; if (!IS_GEMINILAKE(dev_priv) && !IS_BROXTON(dev_priv)) - dc6_reg = SKL_CSR_DC5_DC6_COUNT; + dc6_reg = SKL_DMC_DC5_DC6_COUNT; } seq_printf(m, "DC3 -> DC5 count: %d\n", @@ -582,10 +582,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused) out: seq_printf(m, "program base: 0x%08x\n", - intel_de_read(dev_priv, CSR_PROGRAM(0))); + intel_de_read(dev_priv, DMC_PROGRAM(0))); seq_printf(m, "ssp base: 0x%08x\n", - intel_de_read(dev_priv, CSR_SSP_BASE)); - seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL)); + intel_de_read(dev_priv, DMC_SSP_BASE)); + seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL)); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 0a05d0f90f28..de58abdd838b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -961,12 +961,12 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv) static void assert_csr_loaded(struct drm_i915_private *dev_priv) { drm_WARN_ONCE(&dev_priv->drm, - !intel_de_read(dev_priv, CSR_PROGRAM(0)), - "CSR program storage start is NULL\n"); - drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_SSP_BASE), - "CSR SSP Base Not fine\n"); - drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_HTP_SKL), - "CSR HTP Not fine\n"); + !intel_de_read(dev_priv, DMC_PROGRAM(0)), + "DMC program storage start is NULL\n"); + drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE), + "DMC SSP Base Not fine\n"); + drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL), + "DMC HTP Not fine\n"); } static struct i915_power_well * @@ -6218,7 +6218,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, /* * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 * support don't manually deinit the power domains. This also means the - * CSR/DMC firmware will stay active, it will power down any HW + * DMC firmware will stay active, it will power down any HW * resources as required and also enable deeper system power states * that would be blocked if the firmware was inactive. */ diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 06828ff90ccf..edd108d41318 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -794,8 +794,8 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, err_printf(m, "DMC loaded: %s\n", yesno(dmc->dmc_payload)); err_printf(m, "DMC fw version: %d.%d\n", - CSR_VERSION_MAJOR(dmc->version), - CSR_VERSION_MINOR(dmc->version)); + DMC_VERSION_MAJOR(dmc->version), + DMC_VERSION_MINOR(dmc->version)); } err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 089b5a59bed3..73a33ffc0559 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7686,20 +7686,20 @@ enum { #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ -/* DMC/CSR */ -#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) -#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 -#define CSR_HTP_ADDR_SKL 0x00500034 -#define CSR_SSP_BASE _MMIO(0x8F074) -#define CSR_HTP_SKL _MMIO(0x8F004) -#define CSR_LAST_WRITE _MMIO(0x8F034) -#define CSR_LAST_WRITE_VALUE 0xc003b400 -/* MMIO address range for CSR program (0x80000 - 0x82FFF) */ -#define CSR_MMIO_START_RANGE 0x80000 -#define CSR_MMIO_END_RANGE 0x8FFFF -#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) -#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) -#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) +/* DMC */ +#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4) +#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0 +#define DMC_HTP_ADDR_SKL 0x00500034 +#define DMC_SSP_BASE _MMIO(0x8F074) +#define DMC_HTP_SKL _MMIO(0x8F004) +#define DMC_LAST_WRITE _MMIO(0x8F034) +#define DMC_LAST_WRITE_VALUE 0xc003b400 +/* MMIO address range for DMC program (0x80000 - 0x82FFF) */ +#define DMC_MMIO_START_RANGE 0x80000 +#define DMC_MMIO_END_RANGE 0x8FFFF +#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030) +#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C) +#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038) #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154) From patchwork Tue May 18 19:53:08 2021 Content-Type: text/plain; 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dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF3956EC7D; Tue, 18 May 2021 19:53:13 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA7A26EC7C for ; Tue, 18 May 2021 19:53:11 +0000 (UTC) IronPort-SDR: UgI3SctwW25gVSL3uToVxLw74BeZ1cuZU6bYawMYG4MuBQX4DBlShsdRCURiwQXhcD7dlBsEnr BUEudJ6yfK2Q== X-IronPort-AV: E=McAfee;i="6200,9189,9988"; a="197715529" X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="197715529" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2021 12:53:09 -0700 IronPort-SDR: fO7QWDm5eq4som+5glFkZs0DHGGfJ4CUdnEtn5h2xvd2gY7bNIH5QNOVMFJf5DQE2qk/GmQ0FM 7fuYpHBoH+Vg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="394989488" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga006.jf.intel.com with ESMTP; 18 May 2021 12:53:09 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 18 May 2021 12:53:08 -0700 Message-Id: <20210518195309.4917-5-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20210518195309.4917-1-anusha.srivatsa@intel.com> References: <20210518195309.4917-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [CI 4/5] drm/i915/dmc: Rename functions names having "csr" X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No functional change. Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_csr.c | 64 +++++++++---------- drivers/gpu/drm/i915/display/intel_csr.h | 10 +-- drivers/gpu/drm/i915/display/intel_display.c | 14 ++-- .../drm/i915/display/intel_display_power.c | 14 ++-- drivers/gpu/drm/i915/i915_drv.c | 6 +- 5 files changed, 54 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index f2124796ce77..ae1dfafaff9a 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -302,14 +302,14 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) } /** - * intel_csr_load_program() - write the firmware from memory to register. + * intel_dmc_load_program() - write the firmware from memory to register. * @dev_priv: i915 drm device. * - * CSR firmware is read from a .bin file and kept in internal memory one time. + * DMC firmware is read from a .bin file and kept in internal memory one time. * Everytime display comes back from low power state this function is called to * copy the firmware from internal memory to registers. */ -void intel_csr_load_program(struct drm_i915_private *dev_priv) +void intel_dmc_load_program(struct drm_i915_private *dev_priv) { u32 *payload = dev_priv->dmc.dmc_payload; u32 i, fw_size; @@ -391,9 +391,9 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info, return dmc_offset; } -static u32 parse_csr_fw_dmc(struct intel_dmc *dmc, - const struct intel_dmc_header_base *dmc_header, - size_t rem_size) +static u32 parse_dmc_fw_header(struct intel_dmc *dmc, + const struct intel_dmc_header_base *dmc_header, + size_t rem_size) { unsigned int header_len_bytes, dmc_header_size, payload_size, i; const u32 *mmioaddr, *mmiodata; @@ -498,7 +498,7 @@ static u32 parse_csr_fw_dmc(struct intel_dmc *dmc, } static u32 -parse_csr_fw_package(struct intel_dmc *dmc, +parse_dmc_fw_package(struct intel_dmc *dmc, const struct intel_package_header *package_header, const struct stepping_info *si, size_t rem_size) @@ -557,7 +557,7 @@ parse_csr_fw_package(struct intel_dmc *dmc, } /* Return number of bytes parsed or 0 on error */ -static u32 parse_csr_fw_css(struct intel_dmc *dmc, +static u32 parse_dmc_fw_css(struct intel_dmc *dmc, struct intel_css_header *css_header, size_t rem_size) { @@ -590,7 +590,7 @@ static u32 parse_csr_fw_css(struct intel_dmc *dmc, return sizeof(struct intel_css_header); } -static void parse_csr_fw(struct drm_i915_private *dev_priv, +static void parse_dmc_fw(struct drm_i915_private *dev_priv, const struct firmware *fw) { struct intel_css_header *css_header; @@ -606,7 +606,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv, /* Extract CSS Header information */ css_header = (struct intel_css_header *)fw->data; - r = parse_csr_fw_css(dmc, css_header, fw->size); + r = parse_dmc_fw_css(dmc, css_header, fw->size); if (!r) return; @@ -614,7 +614,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv, /* Extract Package Header information */ package_header = (struct intel_package_header *)&fw->data[readcount]; - r = parse_csr_fw_package(dmc, package_header, si, fw->size - readcount); + r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); if (!r) return; @@ -622,17 +622,17 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv, /* Extract dmc_header information */ dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount]; - parse_csr_fw_dmc(dmc, dmc_header, fw->size - readcount); + parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount); } -static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv) +static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv) { drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); dev_priv->dmc.wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); } -static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv) +static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv) { intel_wakeref_t wakeref __maybe_unused = fetch_and_zero(&dev_priv->dmc.wakeref); @@ -640,7 +640,7 @@ static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv) intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); } -static void csr_load_work_fn(struct work_struct *work) +static void dmc_load_work_fn(struct work_struct *work) { struct drm_i915_private *dev_priv; struct intel_dmc *dmc; @@ -650,11 +650,11 @@ static void csr_load_work_fn(struct work_struct *work) dmc = &dev_priv->dmc; request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev); - parse_csr_fw(dev_priv, fw); + parse_dmc_fw(dev_priv, fw); if (dev_priv->dmc.dmc_payload) { - intel_csr_load_program(dev_priv); - intel_csr_runtime_pm_put(dev_priv); + intel_dmc_load_program(dev_priv); + intel_dmc_runtime_pm_put(dev_priv); drm_info(&dev_priv->drm, "Finished loading DMC firmware %s (v%u.%u)\n", @@ -673,17 +673,17 @@ static void csr_load_work_fn(struct work_struct *work) } /** - * intel_csr_ucode_init() - initialize the firmware loading. + * intel_dmc_ucode_init() - initialize the firmware loading. * @dev_priv: i915 drm device. * * This function is called at the time of loading the display driver to read * firmware from a .bin file and copied into a internal memory. */ -void intel_csr_ucode_init(struct drm_i915_private *dev_priv) +void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) { struct intel_dmc *dmc = &dev_priv->dmc; - INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn); + INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn); if (!HAS_DMC(dev_priv)) return; @@ -696,7 +696,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) * suspend as runtime suspend *requires* a working DMC for whatever * reason. */ - intel_csr_runtime_pm_get(dev_priv); + intel_dmc_runtime_pm_get(dev_priv); if (IS_ALDERLAKE_S(dev_priv)) { dmc->fw_path = ADLS_DMC_PATH; @@ -766,14 +766,14 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) } /** - * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend + * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend * @dev_priv: i915 drm device * * Prepare the DMC firmware before entering system suspend. This includes * flushing pending work items and releasing any resources acquired during * init. */ -void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) +void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv) { if (!HAS_DMC(dev_priv)) return; @@ -782,17 +782,17 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) /* Drop the reference held in case DMC isn't loaded. */ if (!dev_priv->dmc.dmc_payload) - intel_csr_runtime_pm_put(dev_priv); + intel_dmc_runtime_pm_put(dev_priv); } /** - * intel_csr_ucode_resume() - init CSR firmware during system resume + * intel_dmc_ucode_resume() - init DMC firmware during system resume * @dev_priv: i915 drm device * * Reinitialize the DMC firmware during system resume, reacquiring any - * resources released in intel_csr_ucode_suspend(). + * resources released in intel_dmc_ucode_suspend(). */ -void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) +void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv) { if (!HAS_DMC(dev_priv)) return; @@ -802,22 +802,22 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) * loaded. */ if (!dev_priv->dmc.dmc_payload) - intel_csr_runtime_pm_get(dev_priv); + intel_dmc_runtime_pm_get(dev_priv); } /** - * intel_csr_ucode_fini() - unload the CSR firmware. + * intel_dmc_ucode_fini() - unload the DMC firmware. * @dev_priv: i915 drm device. * * Firmmware unloading includes freeing the internal memory and reset the * firmware loading status. */ -void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) +void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv) { if (!HAS_DMC(dev_priv)) return; - intel_csr_ucode_suspend(dev_priv); + intel_dmc_ucode_suspend(dev_priv); drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); kfree(dev_priv->dmc.dmc_payload); diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h index 984e9fb250f8..fc4960b91686 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.h +++ b/drivers/gpu/drm/i915/display/intel_csr.h @@ -12,10 +12,10 @@ struct drm_i915_private; #define DMC_VERSION_MAJOR(version) ((version) >> 16) #define DMC_VERSION_MINOR(version) ((version) & 0xffff) -void intel_csr_ucode_init(struct drm_i915_private *i915); -void intel_csr_load_program(struct drm_i915_private *i915); -void intel_csr_ucode_fini(struct drm_i915_private *i915); -void intel_csr_ucode_suspend(struct drm_i915_private *i915); -void intel_csr_ucode_resume(struct drm_i915_private *i915); +void intel_dmc_ucode_init(struct drm_i915_private *i915); +void intel_dmc_load_program(struct drm_i915_private *i915); +void intel_dmc_ucode_fini(struct drm_i915_private *i915); +void intel_dmc_ucode_suspend(struct drm_i915_private *i915); +void intel_dmc_ucode_resume(struct drm_i915_private *i915); #endif /* __INTEL_CSR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 422b59ebf6dc..39c9c49b378b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -12192,7 +12192,7 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915) if (!HAS_DISPLAY(i915)) return 0; - intel_csr_ucode_init(i915); + intel_dmc_ucode_init(i915); i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI | @@ -12204,15 +12204,15 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915) ret = intel_cdclk_init(i915); if (ret) - goto cleanup_vga_client_pw_domain_csr; + goto cleanup_vga_client_pw_domain_dmc; ret = intel_dbuf_init(i915); if (ret) - goto cleanup_vga_client_pw_domain_csr; + goto cleanup_vga_client_pw_domain_dmc; ret = intel_bw_init(i915); if (ret) - goto cleanup_vga_client_pw_domain_csr; + goto cleanup_vga_client_pw_domain_dmc; init_llist_head(&i915->atomic_helper.free_list); INIT_WORK(&i915->atomic_helper.free_work, @@ -12224,8 +12224,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915) return 0; -cleanup_vga_client_pw_domain_csr: - intel_csr_ucode_fini(i915); +cleanup_vga_client_pw_domain_dmc: + intel_dmc_ucode_fini(i915); intel_power_domains_driver_remove(i915); intel_vga_unregister(i915); cleanup_bios: @@ -13304,7 +13304,7 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) /* part #3: call after gem init */ void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915) { - intel_csr_ucode_fini(i915); + intel_dmc_ucode_fini(i915); intel_power_domains_driver_remove(i915); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index de58abdd838b..cbba41d3e6cf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -958,7 +958,7 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv) intel_pps_unlock_regs_wa(dev_priv); } -static void assert_csr_loaded(struct drm_i915_private *dev_priv) +static void assert_dmc_loaded(struct drm_i915_private *dev_priv) { drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_PROGRAM(0)), @@ -1057,7 +1057,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) "DC5 already programmed to be enabled.\n"); assert_rpm_wakelock_held(&dev_priv->runtime_pm); - assert_csr_loaded(dev_priv); + assert_dmc_loaded(dev_priv); } static void gen9_enable_dc5(struct drm_i915_private *dev_priv) @@ -1084,7 +1084,7 @@ static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) DC_STATE_EN_UPTO_DC6), "DC6 already programmed to be enabled.\n"); - assert_csr_loaded(dev_priv); + assert_dmc_loaded(dev_priv); } static void skl_enable_dc6(struct drm_i915_private *dev_priv) @@ -5574,7 +5574,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, gen9_dbuf_enable(dev_priv); if (resume && dev_priv->dmc.dmc_payload) - intel_csr_load_program(dev_priv); + intel_dmc_load_program(dev_priv); } static void skl_display_core_uninit(struct drm_i915_private *dev_priv) @@ -5641,7 +5641,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume gen9_dbuf_enable(dev_priv); if (resume && dev_priv->dmc.dmc_payload) - intel_csr_load_program(dev_priv); + intel_dmc_load_program(dev_priv); } static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) @@ -5707,7 +5707,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume gen9_dbuf_enable(dev_priv); if (resume && dev_priv->dmc.dmc_payload) - intel_csr_load_program(dev_priv); + intel_dmc_load_program(dev_priv); } static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) @@ -5864,7 +5864,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, tgl_bw_buddy_init(dev_priv); if (resume && dev_priv->dmc.dmc_payload) - intel_csr_load_program(dev_priv); + intel_dmc_load_program(dev_priv); /* Wa_14011508470 */ if (DISPLAY_VER(dev_priv) == 12) { diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5118dc8386b2..f2a9583dfecc 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1043,7 +1043,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915) intel_suspend_encoders(i915); intel_shutdown_encoders(i915); - intel_csr_ucode_suspend(i915); + intel_dmc_ucode_suspend(i915); /* * The only requirement is to reboot with display DC states disabled, @@ -1124,7 +1124,7 @@ static int i915_drm_suspend(struct drm_device *dev) dev_priv->suspend_count++; - intel_csr_ucode_suspend(dev_priv); + intel_dmc_ucode_suspend(dev_priv); enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); @@ -1226,7 +1226,7 @@ static int i915_drm_resume(struct drm_device *dev) i915_ggtt_resume(&dev_priv->ggtt); - intel_csr_ucode_resume(dev_priv); + intel_dmc_ucode_resume(dev_priv); i915_restore_display(dev_priv); intel_pps_unlock_regs_wa(dev_priv); From patchwork Tue May 18 19:53:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12265565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 963F6C433ED for ; Tue, 18 May 2021 19:53:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2F19F6124C for ; Tue, 18 May 2021 19:53:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2F19F6124C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCE026EC77; Tue, 18 May 2021 19:53:11 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 047BC6EC77 for ; Tue, 18 May 2021 19:53:10 +0000 (UTC) IronPort-SDR: tq00JEe8WBMY2Sjy+SUkqhZgHV/AYZDLeGvGzuQDb6OsqyNIIdzPbRPxJivo/zwq0pOpyBSOZz IyrUMvhx6z5Q== X-IronPort-AV: E=McAfee;i="6200,9189,9988"; a="197715530" X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="197715530" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2021 12:53:09 -0700 IronPort-SDR: GT9JZuaerAIuI74zoqZ/ElouyGhPyfGQ89p3Jd2zPCXvo6ZcwzFqJ3/U45WKTyKb60u6y+6toQ d5ydzuGFfeKw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,310,1613462400"; d="scan'208";a="394989489" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga006.jf.intel.com with ESMTP; 18 May 2021 12:53:09 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 18 May 2021 12:53:09 -0700 Message-Id: <20210518195309.4917-6-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20210518195309.4917-1-anusha.srivatsa@intel.com> References: <20210518195309.4917-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [CI 5/5] drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Finally, rename the header and source file from csr to dmc. v2: Add file rename in Documentation. - Place headers in orders. (Jani) Cc: Jani Nikula Signed-off-by: Anusha Srivatsa --- Documentation/gpu/i915.rst | 10 +++++----- drivers/gpu/drm/i915/Makefile | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- .../gpu/drm/i915/display/{intel_csr.c => intel_dmc.c} | 4 ++-- .../gpu/drm/i915/display/{intel_csr.h => intel_dmc.h} | 6 +++--- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 9 files changed, 16 insertions(+), 16 deletions(-) rename drivers/gpu/drm/i915/display/{intel_csr.c => intel_dmc.c} (99%) rename drivers/gpu/drm/i915/display/{intel_csr.h => intel_dmc.h} (88%) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 486c720f3890..308bb283f468 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -210,13 +210,13 @@ DPIO .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c :doc: DPIO -CSR firmware support for DMC ----------------------------- +DMC Firmware Support +-------------------- -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c - :doc: csr support for dmc +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c + :doc: DMC Firmware Support -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c :internal: Video BIOS Table (VBT) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index d0d936d9137b..2da5bae8fa03 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -201,10 +201,10 @@ i915-y += \ display/intel_combo_phy.o \ display/intel_connector.o \ display/intel_crtc.o \ - display/intel_csr.o \ display/intel_cursor.o \ display/intel_display.o \ display/intel_display_power.o \ + display/intel_dmc.o \ display/intel_dpio_phy.o \ display/intel_dpll.o \ display/intel_dpll_mgr.o \ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 39c9c49b378b..d98a314bb974 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -79,9 +79,9 @@ #include "intel_cdclk.h" #include "intel_color.h" #include "intel_crtc.h" -#include "intel_csr.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dmc.h" #include "intel_dp_link_training.h" #include "intel_fbc.h" #include "intel_fdi.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index e43abdf0e3d9..94e5cbd86e77 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -7,11 +7,11 @@ #include #include "i915_debugfs.h" -#include "intel_csr.h" #include "intel_display_debugfs.h" #include "intel_display_power.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dmc.h" #include "intel_dp.h" #include "intel_fbc.h" #include "intel_hdcp.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index cbba41d3e6cf..e8fcc3d02d01 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -9,10 +9,10 @@ #include "i915_irq.h" #include "intel_cdclk.h" #include "intel_combo_phy.h" -#include "intel_csr.h" #include "intel_display_power.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dmc.h" #include "intel_dpio_phy.h" #include "intel_hotplug.h" #include "intel_pm.h" diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_dmc.c similarity index 99% rename from drivers/gpu/drm/i915/display/intel_csr.c rename to drivers/gpu/drm/i915/display/intel_dmc.c index ae1dfafaff9a..560574dd929a 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -26,11 +26,11 @@ #include "i915_drv.h" #include "i915_reg.h" -#include "intel_csr.h" #include "intel_de.h" +#include "intel_dmc.h" /** - * DOC: DMC firmware support + * DOC: DMC Firmware Support * * From gen9 onwards we have newly added DMC (Display microcontroller) in display * engine to save and restore the state of display engine when it enter into diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_dmc.h similarity index 88% rename from drivers/gpu/drm/i915/display/intel_csr.h rename to drivers/gpu/drm/i915/display/intel_dmc.h index fc4960b91686..57dd99da0ced 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.h +++ b/drivers/gpu/drm/i915/display/intel_dmc.h @@ -3,8 +3,8 @@ * Copyright © 2019 Intel Corporation */ -#ifndef __INTEL_CSR_H__ -#define __INTEL_CSR_H__ +#ifndef __INTEL_DMC_H__ +#define __INTEL_DMC_H__ struct drm_i915_private; @@ -18,4 +18,4 @@ void intel_dmc_ucode_fini(struct drm_i915_private *i915); void intel_dmc_ucode_suspend(struct drm_i915_private *i915); void intel_dmc_ucode_resume(struct drm_i915_private *i915); -#endif /* __INTEL_CSR_H__ */ +#endif /* __INTEL_DMC_H__ */ diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index f2a9583dfecc..2f06bb7b3ed2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -49,7 +49,7 @@ #include "display/intel_acpi.h" #include "display/intel_bw.h" #include "display/intel_cdclk.h" -#include "display/intel_csr.h" +#include "display/intel_dmc.h" #include "display/intel_display_types.h" #include "display/intel_dp.h" #include "display/intel_fbdev.h" diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index edd108d41318..8b964e355cb5 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -36,7 +36,7 @@ #include -#include "display/intel_csr.h" +#include "display/intel_dmc.h" #include "display/intel_overlay.h" #include "gem/i915_gem_context.h"