From patchwork Tue May 25 06:25:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12277987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DB9CC2B9F8 for ; Tue, 25 May 2021 06:28:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 115D8613F7 for ; Tue, 25 May 2021 06:28:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 115D8613F7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YU52vQB1TDgw835mH/3VQo1u3RzMrihH54vPbRBjsQQ=; b=qZhrdPQ3HS02Id 1dEAVZJxKIhFDmJ9SsjYvxiguAB77NH2fBZB9Dr9cnd9QzqTZP5Vjs1tyNVKxnqkyZDxhXrBfNgZg 760ZwUDbSdY5bOq4xvEc7Ens/LVel9/AuhDwG6qqqqWjtAPoOrouxPOswi0jC9VCezhogxJ6Y+hTM Ru4slpgIuIjGodPgDvy75NVWQhS8g9lWJlCItAqMAPW9VrzjWCmlFGXpFlzg5I6FuR77lyG+Jv4sG j7wQKvhpWSehivOEUMvwocQoOrHTNquMGRLauWworFucC52mJIMvaWDfIw9HsPAEunp977i3UlrmI K0ZFsDjIax7dBCX8I42w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVm-003bvu-6b; Tue, 25 May 2021 06:25:54 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVU-003bqg-Uq for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 06:25:38 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB86F101E; Mon, 24 May 2021 23:25:31 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 026AA3F73D; Mon, 24 May 2021 23:25:29 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v3 1/8] Decouple V2M_SYS config by auto-detect dtb node Date: Tue, 25 May 2021 14:25:02 +0800 Message-Id: <20210525062509.201464-2-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525062509.201464-1-jaxson.han@arm.com> References: <20210525062509.201464-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_232537_063247_36101FDF X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org An auto-detect switch is added to make it an option to enable/disable 'arm,vexpress-sysreg', because not all platforms support this feature. But the auto-detection generates the side-effect of printing a warning message about the missing node: No matching devices found at ./findbase.pl line 37. In this case, to drop the warning message, add "2> /dev/null" at the end of the findbase.pl call. Signed-off-by: Jaxson Han Reviewed-by: Andre Przywara --- Makefile.am | 4 ++-- platform.c | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile.am b/Makefile.am index af694b7..ef6b793 100644 --- a/Makefile.am +++ b/Makefile.am @@ -10,7 +10,7 @@ # VE PHYS_OFFSET := $(shell perl -I $(top_srcdir) $(top_srcdir)/findmem.pl $(KERNEL_DTB)) UART_BASE := $(shell perl -I $(top_srcdir) $(top_srcdir)/findbase.pl $(KERNEL_DTB) 0 'arm,pl011') -SYSREGS_BASE := $(shell perl -I $(top_srcdir) $(top_srcdir)/findbase.pl $(KERNEL_DTB) 0 'arm,vexpress-sysreg') +SYSREGS_BASE := $(shell perl -I $(top_srcdir) $(top_srcdir)/findbase.pl $(KERNEL_DTB) 0 'arm,vexpress-sysreg' 2> /dev/null) CNTFRQ := 0x01800000 # 24Mhz CPU_IDS := $(shell perl -I $(top_srcdir) $(top_srcdir)/findcpuids.pl $(KERNEL_DTB)) @@ -19,7 +19,7 @@ NR_CPUS := $(shell echo $(CPU_IDS) | tr ',' ' ' | wc -w) DEFINES = -DCNTFRQ=$(CNTFRQ) DEFINES += -DCPU_IDS=$(CPU_IDS) DEFINES += -DNR_CPUS=$(NR_CPUS) -DEFINES += -DSYSREGS_BASE=$(SYSREGS_BASE) +DEFINES += $(if $(SYSREGS_BASE), -DSYSREGS_BASE=$(SYSREGS_BASE), ) DEFINES += -DUART_BASE=$(UART_BASE) DEFINES += -DSTACK_SIZE=256 diff --git a/platform.c b/platform.c index a528a55..d11f568 100644 --- a/platform.c +++ b/platform.c @@ -23,10 +23,12 @@ #define PL011(reg) ((void *)UART_BASE + PL011_##reg) +#ifdef SYSREGS_BASE #define V2M_SYS_CFGDATA 0xa0 #define V2M_SYS_CFGCTRL 0xa4 #define V2M_SYS(reg) ((void *)SYSREGS_BASE + V2M_SYS_##reg) +#endif static void print_string(const char *str) { @@ -59,6 +61,7 @@ void init_platform(void) print_string("Boot-wrapper v0.2\r\n\r\n"); +#ifdef SYSREGS_BASE /* * CLCD output site MB */ @@ -66,4 +69,5 @@ void init_platform(void) /* START | WRITE | MUXFPGA | SITE_MB */ raw_writel((1 << 31) | (1 << 30) | (7 << 20) | (0 << 16), V2M_SYS(CFGCTRL)); +#endif } From patchwork Tue May 25 06:25:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12277981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC453C4707F for ; Tue, 25 May 2021 06:28:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A528061413 for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQWI-003c0w-59; Tue, 25 May 2021 06:26:26 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVU-003bqr-UC for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 06:25:39 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2857C1042; Mon, 24 May 2021 23:25:34 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 51B1D3F73D; Mon, 24 May 2021 23:25:32 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v3 2/8] aarch64: Rename labels and prepare for lower EL booting Date: Tue, 25 May 2021 14:25:03 +0800 Message-Id: <20210525062509.201464-3-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525062509.201464-1-jaxson.han@arm.com> References: <20210525062509.201464-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_232537_107203_EB8C30D2 X-CRM114-Status: GOOD ( 10.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Prepare for booting from lower EL. Rename *_el3 relavant labels with *_el_max and *_no_el3 with *_keep_el. Since the original _no_el3 means "We neither do init sequence at this highest EL nor drop to lower EL when entering to kernel", we rename it with _keep_el to make it more clear for lower EL initialisation. Signed-off-by: Jaxson Han Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 31 +++++++++++++++++++++---------- arch/aarch64/psci.S | 13 +++++++------ arch/aarch64/spin.S | 8 ++++---- 3 files changed, 32 insertions(+), 20 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index a9264de..1a5da35 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -12,7 +12,7 @@ .section .init .globl _start - .globl jump_kernel + .globl jump_kernel _start: cpuid x0, x1 @@ -22,20 +22,31 @@ _start: bl setup_stack /* - * EL3 initialisation + * Boot sequence + * If CurrentEL == EL3, then goto EL3 initialisation and drop to + * lower EL before entering the kernel. + * Else, no initialisation and keep the current EL before + * entering the kernel. */ mrs x0, CurrentEL cmp x0, #CURRENTEL_EL3 - b.eq 1f + beq el3_init + /* + * We stay in the current EL for entering the kernel + */ mov w0, #1 - ldr x1, =flag_no_el3 + ldr x1, =flag_keep_el str w0, [x1] bl setup_stack - b start_no_el3 + b start_keep_el -1: mov x0, #0x30 // RES1 + /* + * EL3 initialisation + */ +el3_init: + mov x0, #0x30 // RES1 orr x0, x0, #(1 << 0) // Non-secure EL1 orr x0, x0, #(1 << 8) // HVC enable @@ -114,7 +125,7 @@ _start: bl gic_secure_init - b start_el3 + b start_el_max err_invalid_id: b . @@ -141,7 +152,7 @@ jump_kernel: bl find_logical_id bl setup_stack // Reset stack pointer - ldr w0, flag_no_el3 + ldr w0, flag_keep_el cmp w0, #0 // Prepare Z flag mov x0, x20 @@ -150,7 +161,7 @@ jump_kernel: mov x3, x23 b.eq 1f - br x19 // No EL3 + br x19 // Keep current EL 1: mov x4, #SPSR_KERNEL @@ -168,5 +179,5 @@ jump_kernel: .data .align 3 -flag_no_el3: +flag_keep_el: .long 0 diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S index 01ebe7d..ae02fd6 100644 --- a/arch/aarch64/psci.S +++ b/arch/aarch64/psci.S @@ -45,8 +45,8 @@ vector: .text - .globl start_no_el3 - .globl start_el3 + .globl start_keep_el + .globl start_el_max err_exception: b err_exception @@ -101,7 +101,7 @@ smc_exit: eret -start_el3: +start_el_max: ldr x0, =vector bl setup_vector @@ -111,10 +111,11 @@ start_el3: b psci_first_spin /* - * This PSCI implementation requires EL3. Without EL3 we'll only boot the - * primary cpu, all others will be trapped in an infinite loop. + * This PSCI implementation requires the highest EL(EL3 or Armv8-R EL2). + * Without the highest EL, we'll only boot the primary cpu, all others + * will be trapped in an infinite loop. */ -start_no_el3: +start_keep_el: cpuid x0, x1 bl find_logical_id cbz x0, psci_first_spin diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S index 72603cf..533177c 100644 --- a/arch/aarch64/spin.S +++ b/arch/aarch64/spin.S @@ -11,11 +11,11 @@ .text - .globl start_no_el3 - .globl start_el3 + .globl start_keep_el + .globl start_el_max -start_el3: -start_no_el3: +start_el_max: +start_keep_el: cpuid x0, x1 bl find_logical_id From patchwork Tue May 25 06:25:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12277985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74B6CC4707F for ; Tue, 25 May 2021 06:28:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3CF59610FC for ; Tue, 25 May 2021 06:28:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3CF59610FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xYKmyjx9cyC1dJf+bnLuDw9ieA24XhKqeXInRcpB1xU=; b=ch5HB8tks6YAmE lFIS9uoUab98YQlJb28id/xij+risvaIqm/BAtWowqIJkT57lIHY4qydxfanWzAOlGOh04OVSe3w+ 89rGqc6vt7U3D17ejMqMfpy3UaUY9NbitUs6i7tfLRD8VuS7jFTinZQFydyzBXoQeO1Q6M9LSNP3R 3wnC0myiM04Mx6jmsz7GTaupLIu9gkYgt5CzUeuoBqXmIsGpAjo0q6LeUvKPxpViOVsUWV87wL3No b041xXl7VVu16lvwiqJHeQ3ENApg1sBR2Ww0uIr0CHebLp6hOn2zseGCyfA+DgEcUvSHFMaZH/wKG hfzE6TL9scFVbbdv7nuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVz-003bxu-S6; Tue, 25 May 2021 06:26:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVV-003brM-8o for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 06:25:39 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8162211D4; Mon, 24 May 2021 23:25:36 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A2C553F73D; Mon, 24 May 2021 23:25:34 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v3 3/8] aarch64: Remove the redundant setup_stack Date: Tue, 25 May 2021 14:25:04 +0800 Message-Id: <20210525062509.201464-4-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525062509.201464-1-jaxson.han@arm.com> References: <20210525062509.201464-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_232537_408159_9E3D69CF X-CRM114-Status: UNSURE ( 8.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since we already have set up a stack above, there is no need to do it again. Also, in fact it's a bug: setup_stack expects the logical CPU ID in w0, and here we always call it with w0 being 1. Signed-off-by: Jaxson Han Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 1a5da35..1cdeb1b 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -39,7 +39,6 @@ _start: ldr x1, =flag_keep_el str w0, [x1] - bl setup_stack b start_keep_el /* From patchwork Tue May 25 06:25:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12277991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E476C2B9F8 for ; Tue, 25 May 2021 06:29:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DADFC613F7 for ; Tue, 25 May 2021 06:29:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DADFC613F7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3tLerXH2dG3MvuN6ad+doV9hCWOdR+FNEsCl4sIttIU=; b=JtW4wN6m6nqVxM YWj3vQMjDuPZtIU2U2fHSsQffGC1irhln9QSO4r3JgooHekoaJx5I4gmIuuTwkaVnKbBvd6dpYVMR 0bgsOgxTkCiyCOT6TmYQAs8LqbmLnvcsXKGOBCNA1XZbZzupeV76o7RLOQv0edlkP5utPlC7koHVJ 092s4cMsCKBhlG75GnDHYdTK3VCmiUDU3UWopFtKt52uliWnC9vKixAyJdWXQndGenBW6EBJhiRqN SaKkHmN01S8mt81+Jn+dU2zlrqVNVaxplnzneqmvqaw1iyLswDPupSZKHwT3JrmIBpo8Z7PwZdZMI k23GPxxGkhqg/gtP9egQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQWX-003c3i-Cx; Tue, 25 May 2021 06:26:41 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVa-003bsz-6b for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 06:25:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DA747D6E; Mon, 24 May 2021 23:25:38 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 078243F73D; Mon, 24 May 2021 23:25:36 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v3 4/8] aarch64: Prepare for EL1 booting Date: Tue, 25 May 2021 14:25:05 +0800 Message-Id: <20210525062509.201464-5-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525062509.201464-1-jaxson.han@arm.com> References: <20210525062509.201464-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_232542_326669_DC9A5306 X-CRM114-Status: UNSURE ( 8.87 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When booting from EL1, add a check and skip the init of sctlr_el2 in jump_kernel Signed-off-by: Jaxson Han Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 6 +++++- arch/aarch64/include/asm/cpu.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 1cdeb1b..8a0219b 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -144,10 +144,14 @@ jump_kernel: ldr x0, =SCTLR_EL1_RESET msr sctlr_el1, x0 + mrs x0, CurrentEL + cmp x0, #CURRENTEL_EL2 + b.lt 1f + ldr x0, =SCTLR_EL2_RESET msr sctlr_el2, x0 - cpuid x0, x1 +1: cpuid x0, x1 bl find_logical_id bl setup_stack // Reset stack pointer diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index ccb5397..3c1ba4b 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -11,6 +11,7 @@ #define MPIDR_ID_BITS 0xff00ffffff +#define CURRENTEL_EL2 (2 << 2) #define CURRENTEL_EL3 (3 << 2) /* From patchwork Tue May 25 06:25:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12277993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AEFDC2B9F8 for ; Tue, 25 May 2021 06:29:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5BDF8610FC for ; Tue, 25 May 2021 06:29:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5BDF8610FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Sa4j/ZOUBqcaWwPfGjOvCyhTr+SeB+qo5Rdog7X/ztA=; b=Qvxs8cC7OVf+xu /hdNtuwEWYjL8uibMDn9em3cvO4r0vcmgKcXflrjeCSvdJeXm0SkijT0dFMHSkRWksc5ynUDt0KA1 ZrWAANOo4jg9hDdK0mFnm2bQOzpMXhPDc6ViEMRxLD4HOcqoMM0jMONUdHfIULMLeeCbZl1dw5Rn2 02pa0AVT7ti1c8sHPtC8sb9OzLYDDpoM2FpteguQrnGO1eihrACbBR3Na0RRT+olix1XHDzoqf8GR EOwabLNUDN1XooRSjs66otydKcXVEF2S5hNmv/HCQlchlW6jD3x/wW14KMMV247z/rmnoH3b2JauN K/1JhNYAnztZpGaNclsQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQXE-003cFH-4g; Tue, 25 May 2021 06:27:24 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVe-003buG-J6 for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 06:25:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 41B09101E; Mon, 24 May 2021 23:25:41 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 60F903F73D; Mon, 24 May 2021 23:25:39 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v3 5/8] aarch64: Prepare for lower EL booting Date: Tue, 25 May 2021 14:25:06 +0800 Message-Id: <20210525062509.201464-6-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525062509.201464-1-jaxson.han@arm.com> References: <20210525062509.201464-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_232546_712363_B5B0A33E X-CRM114-Status: UNSURE ( 8.86 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Save SPSR_KERNEL into spsr_to_elx during el3_init. The jump_kernel will load spsr_to_elx into spsr_el3. This change will make it easier to control whether drop to lower EL before jumping to the kernel. Signed-off-by: Jaxson Han Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 8a0219b..5600859 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -118,7 +118,16 @@ el3_init: mov x0, #ZCR_EL3_LEN_MASK // SVE: Enable full vector len msr ZCR_EL3, x0 // for EL2. -1: + /* + * Save SPSR_KERNEL into spsr_to_elx. + * The jump_kernel will load spsr_to_elx into spsr_el3 + */ +1: mov w0, #SPSR_KERNEL + ldr x1, =spsr_to_elx + str w0, [x1] + b el_max_init + +el_max_init: ldr x0, =CNTFRQ msr cntfrq_el0, x0 @@ -166,7 +175,7 @@ jump_kernel: b.eq 1f br x19 // Keep current EL -1: mov x4, #SPSR_KERNEL +1: ldr w4, spsr_to_elx /* * If bit 0 of the kernel address is set, we're entering in AArch32 @@ -184,3 +193,5 @@ jump_kernel: .align 3 flag_keep_el: .long 0 +spsr_to_elx: + .long 0 From patchwork Tue May 25 06:25:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12277989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 779D9C2B9F8 for ; Tue, 25 May 2021 06:28:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42981610FC for ; Tue, 25 May 2021 06:28:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42981610FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2fzdSpVP95tTn8hcut7al3ftfUj825L47GNZ0gGpChQ=; b=RjeEuJZZXnsMSb enoYsw1bIJue7WMzyatjpgRrxNeOG4gvyZOCVEGFgUYswBsi8dhbgRxSqS09kZW2ct0gScWF8kvWd tET5MGCZeC0N3zrW4F6fNnAKOpl4CrDqIE1Shk/NQKcDjb2iNXBrv/M1qZL90nxEvbZxGIShK9z8X NRczYKTsg+mPXBHGObDKsDOU2/df+JV6KW+ZhjG5EHXJoy7X8wkY+GR1qbRC7QumUfkoBHHDaKD2Y c/6wFH1ubOHH223CBr7+Vi34S+7xBgXsfNLhI4KDw2t0Ris7s3as9H74cKCTUV1J0z6iJ566fdmxX 9wHrn5UvKk58ISqVIYlg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQWo-003c7p-W8; Tue, 25 May 2021 06:26:59 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVd-003btr-Db for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 06:25:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9175E1042; Mon, 24 May 2021 23:25:43 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BB0C93F73D; Mon, 24 May 2021 23:25:41 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v3 6/8] gic-v3: Prepare for gicv3 with EL2 Date: Tue, 25 May 2021 14:25:07 +0800 Message-Id: <20210525062509.201464-7-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525062509.201464-1-jaxson.han@arm.com> References: <20210525062509.201464-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_232545_579772_DA000FF7 X-CRM114-Status: GOOD ( 11.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a preparation for allowing boot-wrapper configuring the gicv3 with EL2. When confiuring with EL2, since there is no ICC_CTLR_EL2, the ICC_CTLR_EL3 cannot be replaced with ICC_CTLR_EL2 simply. See [https://developer.arm.com/documentation/ihi0069/latest/]. As the caller, gic_secure_init expects the ICC_CTLR to be written, we change the function into gic_init_icc_ctlr(). In the GIC spec, the r/w bits in this register ([6:0]) either affect EL3 IRQ routing (not applicable since no EL3), non-secure IRQ handling (not applicable since only secure state in Armv8-R aarch64), or are aliased to ICC_CTLR_EL1 bits. So, based on this, the new gic_init_icc_ctlr() would be: When currentEL is EL3, init ICC_CTLR_EL3 as before. When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET. Signed-off-by: Jaxson Han Reviewed-by: Andre Przywara --- arch/aarch32/include/asm/gic-v3.h | 7 ++++++ arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++--- gic-v3.c | 2 +- 3 files changed, 43 insertions(+), 4 deletions(-) diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h index ec9a327..86abe09 100644 --- a/arch/aarch32/include/asm/gic-v3.h +++ b/arch/aarch32/include/asm/gic-v3.h @@ -9,6 +9,8 @@ #ifndef __ASM_AARCH32_GICV3_H #define __ASM_AARCH32_GICV3_H +#define ICC_CTLR_RESET (0UL) + static inline uint32_t gic_read_icc_sre(void) { uint32_t val; @@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val) asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val)); } +static inline void gic_init_icc_ctlr() +{ + gic_write_icc_ctlr(ICC_CTLR_RESET); +} + #endif diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h index e743c02..b3dfbd3 100644 --- a/arch/aarch64/include/asm/gic-v3.h +++ b/arch/aarch64/include/asm/gic-v3.h @@ -15,21 +15,53 @@ #define ICC_CTLR_EL3 "S3_6_C12_C12_4" #define ICC_PMR_EL1 "S3_0_C4_C6_0" +#define ICC_CTLR_EL3_RESET (0UL) +#define ICC_CTLR_EL1_RESET (0UL) + +static inline uint32_t current_el(void) +{ + uint32_t val; + + asm volatile ("mrs %0, CurrentEL" : "=r" (val)); + return val; +} + static inline uint32_t gic_read_icc_sre(void) { uint32_t val; - asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val)); + + if(current_el() == CURRENTEL_EL3) + asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val)); + else + asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val)); + return val; } static inline void gic_write_icc_sre(uint32_t val) { - asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); + if(current_el() == CURRENTEL_EL3) + asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); + else + asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val)); } -static inline void gic_write_icc_ctlr(uint32_t val) +static inline void gic_write_icc_ctlr_el3(uint32_t val) { asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val)); } +static inline void gic_write_icc_ctlr_el1(uint32_t val) +{ + asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val)); +} + +static inline void gic_init_icc_ctlr() +{ + if(current_el() == CURRENTEL_EL3) + gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET); + else + gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET); +} + #endif diff --git a/gic-v3.c b/gic-v3.c index ae2d2bc..4850572 100644 --- a/gic-v3.c +++ b/gic-v3.c @@ -121,6 +121,6 @@ void gic_secure_init(void) gic_write_icc_sre(sre); isb(); - gic_write_icc_ctlr(0); + gic_init_icc_ctlr(); isb(); } From patchwork Tue May 25 06:25:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12277995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5274CC2B9F8 for ; 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Mon, 24 May 2021 23:25:43 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v3 7/8] aarch64: Prepare for booting with EL2 Date: Tue, 25 May 2021 14:25:08 +0800 Message-Id: <20210525062509.201464-8-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525062509.201464-1-jaxson.han@arm.com> References: <20210525062509.201464-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_232546_738607_19407D38 X-CRM114-Status: UNSURE ( 8.67 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Prepare for allowing boot-wrapper to be entered in EL2. Detect current EL and set the corresponding EL registers. Signed-off-by: Jaxson Han Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 8 ++++++++ arch/aarch64/utils.S | 10 +++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 5600859..14fd9cf 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -183,10 +183,18 @@ jump_kernel: */ bfi x4, x19, #5, #1 + mrs x5, CurrentEL + cmp x5, #CURRENTEL_EL2 + b.eq 1f + msr elr_el3, x19 msr spsr_el3, x4 eret +1: msr elr_el2, x19 + msr spsr_el2, x4 + eret + .ltorg .data diff --git a/arch/aarch64/utils.S b/arch/aarch64/utils.S index ae22ea7..94e9931 100644 --- a/arch/aarch64/utils.S +++ b/arch/aarch64/utils.S @@ -37,10 +37,18 @@ find_logical_id: ret /* - * Setup EL3 vectors + * Setup EL3/EL2 vectors * x0: vector address */ setup_vector: + mrs x1, CurrentEL + cmp x1, #CURRENTEL_EL2 + b.eq 1f + msr VBAR_EL3, x0 isb ret + +1: msr VBAR_EL2, x0 + isb + ret From patchwork Tue May 25 06:25:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12277997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF004C2B9F8 for ; Tue, 25 May 2021 06:30:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 86D07613F7 for ; Tue, 25 May 2021 06:30:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 86D07613F7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8k9Wx5x4/YyGVTvIBvN2NXbjBbO5CC5yAUm/MUpjqls=; b=IhJp6j766I9BeD buEtoHKLl5QottAYTjOpFX4sbqDPdlEoP8xX+ARZeWz6U8CKwUCuYAfR65ft3t3xn4Gl6EvPQBNi3 n+c4fAvbJEI3IpJHR5k6cQwu0DHk4sFqXbqZSCcIu6q7ofb8HEfhi3cDBsxzETue6ac+sza9wg/bt chaVpOJqEZ4zzoNot9w4YoBEbEraAY6kbfPdKcMBRTZeEDr7ftuJ0RKPtUwAtZCPhgsHqcq9ZDGPX 2sdv80saJ/rU5/rs4sPs+215NzBqKxMAA+/5+CETISBv3X+yub834hdwpboQCoiCAglUkMZc1GrpX uaJqxtkrBC6Zu50khhjA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQYa-003cf4-Pl; Tue, 25 May 2021 06:28:49 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVg-003btr-IY for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 06:25:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4754B101E; Mon, 24 May 2021 23:25:48 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 71A7F3F73D; Mon, 24 May 2021 23:25:46 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v3 8/8] aarch64: Introduce EL2 boot code for Armv8-R AArch64 Date: Tue, 25 May 2021 14:25:09 +0800 Message-Id: <20210525062509.201464-9-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525062509.201464-1-jaxson.han@arm.com> References: <20210525062509.201464-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_232548_752220_858B4B68 X-CRM114-Status: GOOD ( 18.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Armv8-R AArch64 profile does not support the EL3 exception level. The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU at EL1, which allows to run off-the-shelf Linux. However EL2 only supports a PMSA, which is not supported by Linux, so we need to drop into EL1 before entering the kernel. We add a new err_invalid_arch symbol as a dead loop. If we detect the current Armv8-R aarch64 only supports with PMSA, meaning we cannot boot Linux anymore, then we jump to err_invalid_arch. During Armv8-R aarch64 init, to make sure nothing unexpected traps into EL2, we auto-detect and config FIEN and EnSCXT in HCR_EL2. The boot sequence is: If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL before entering the kernel. If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64), if id_aa64mmfr0_el1.MSA_frac == 0x2, then goto Armv8-R AArch64 initialisation and drop to EL1 before entering the kernel. else, which means VMSA unsupported and cannot boot Linux, goto err_invalid_arch (dead loop). Else, no initialisation and keep the current EL before entering the kernel. Signed-off-by: Jaxson Han Reviewed-by: Andre Przywara --- arch/aarch64/boot.S | 92 +++++++++++++++++++++++++++++++++- arch/aarch64/include/asm/cpu.h | 2 + 2 files changed, 92 insertions(+), 2 deletions(-) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 14fd9cf..461e927 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -25,16 +25,24 @@ _start: * Boot sequence * If CurrentEL == EL3, then goto EL3 initialisation and drop to * lower EL before entering the kernel. + * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf, then + * If id_aa64mmfr0_el1.MSA_frac == 0x2, then goto + * Armv8-R AArch64 initialisation and drop to EL1 before + * entering the kernel. + * Else, which means VMSA unsupported and cannot boot Linux, + * goto err_invalid_arch (dead loop). * Else, no initialisation and keep the current EL before * entering the kernel. */ mrs x0, CurrentEL - cmp x0, #CURRENTEL_EL3 - beq el3_init + cmp x0, #CURRENTEL_EL2 + bgt el3_init + beq el2_init /* * We stay in the current EL for entering the kernel */ +keep_el: mov w0, #1 ldr x1, =flag_keep_el str w0, [x1] @@ -127,6 +135,85 @@ el3_init: str w0, [x1] b el_max_init + /* + * EL2 Armv8-R AArch64 initialisation + */ +el2_init: + /* Detect Armv8-R AArch64 */ + mrs x1, id_aa64mmfr0_el1 + /* + * Check MSA, bits [51:48]: + * 0xf means Armv8-R AArch64. + * If not 0xf, proceed in Armv8-A EL2. + */ + ubfx x0, x1, #48, #4 // MSA + cmp x0, 0xf + bne keep_el + /* + * Check MSA_frac, bits [55:52]: + * 0x2 means EL1&0 translation regime also supports VMSAv8-64. + */ + ubfx x0, x1, #52, #4 // MSA_frac + cmp x0, 0x2 + /* + * If not 0x2, no VMSA, so cannot boot Linux and dead loop. + * Also, since the architecture guarantees that those CPUID + * fields never lose features when the value in a field + * increases, we use blt to cover it. + */ + blt err_invalid_arch + + mrs x0, midr_el1 + msr vpidr_el2, x0 + + mrs x0, mpidr_el1 + msr vmpidr_el2, x0 + + mov x0, #(1 << 31) // VTCR_MSA: VMSAv8-64 support + msr vtcr_el2, x0 + + /* Init HCR_EL2 */ + mov x0, #(1 << 31) // RES1: Armv8-R aarch64 only + + mrs x1, id_aa64pfr0_el1 + ubfx x2, x1, #56, 4 // ID_AA64PFR0_EL1.CSV2 + cmp x2, 0x2 + b.lt 1f + /* + * Disable trap when accessing SCTXNUM_EL0 or SCTXNUM_EL1 + * if FEAT_CSV2. + */ + orr x0, x0, #(1 << 53) // HCR_EL2.EnSCXT + +1: ubfx x2, x1, #28, 4 // ID_AA64PFR0_EL1.RAS + cmp x2, 0x2 + b.lt 1f + /* Disable trap when accessing ERXPFGCDN_EL1 if FEAT_RASv1p1. */ + orr x0, x0, #(1 << 47) // HCR_EL2.FIEN + + /* Enable pointer authentication if present */ +1: mrs x1, id_aa64isar1_el1 + /* + * If ID_AA64ISAR1_EL1.{GPI, GPA, API, APA} == {0000, 0000, 0000, 0000} + * then HCR_EL2.APK and HCR_EL2.API are RES 0. + * Else + * set HCR_EL2.APK and HCR_EL2.API. + */ + ldr x2, =(((0xff) << 24) | (0xff << 4)) + and x1, x1, x2 + cbz x1, 1f + + orr x0, x0, #(1 << 40) // HCR_EL2.APK + orr x0, x0, #(1 << 41) // HCR_EL2.API + +1: msr hcr_el2, x0 + isb + + mov w0, #SPSR_KERNEL_EL1 + ldr x1, =spsr_to_elx + str w0, [x1] + // fall through + el_max_init: ldr x0, =CNTFRQ msr cntfrq_el0, x0 @@ -136,6 +223,7 @@ el_max_init: b start_el_max err_invalid_id: +err_invalid_arch: b . /* diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 3c1ba4b..2b3a0a4 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -25,6 +25,7 @@ #define SPSR_I (1 << 7) /* IRQ masked */ #define SPSR_F (1 << 6) /* FIQ masked */ #define SPSR_T (1 << 5) /* Thumb */ +#define SPSR_EL1H (5 << 0) /* EL1 Handler mode */ #define SPSR_EL2H (9 << 0) /* EL2 Handler mode */ #define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */ @@ -43,6 +44,7 @@ #else #define SCTLR_EL1_RESET SCTLR_EL1_RES1 #define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H) +#define SPSR_KERNEL_EL1 (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H) #endif #ifndef __ASSEMBLY__