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Tue, 25 May 2021 02:01:09 -0700 (PDT) Received: from localhost ([82.44.17.50]) by smtp.gmail.com with ESMTPSA id o21sm10250665wmr.44.2021.05.25.02.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 May 2021 02:01:08 -0700 (PDT) From: Jamie Iles To: qemu-arm@nongnu.org Subject: [PATCHv2] target/arm: make pointer authentication a switchable feature Date: Tue, 25 May 2021 10:01:04 +0100 Message-Id: <20210525090104.1761645-1-jamie@nuviainc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=jamie@nuviainc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jamie Iles , leif@nuviainc.com, Richard Henderson , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Rather than having pointer authentication properties be specific to the max CPU type, turn this into a generic feature that can be set for each CPU model. This means that for future CPU types the feature can be set without having the ID_AA64ISAR1 bits clobbered in arm_cpu_pauth_finalize. This also makes it possible for real CPU models to use the impdef algorithm for improved performance by setting pauth-impdef=on on the command line. Cc: Richard Henderson Cc: Peter Maydell Signed-off-by: Jamie Iles --- Following Richard's suggestion to make impdef selectable for all CPUs where pointer auth is supported, I've moved this up to a full feature and then any future CPUs supporting pointer auth can just set ARM_FEATURE_PAUTH. target/arm/cpu.h | 2 ++ target/arm/cpu64.c | 13 +++++++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 272fde83ca4e..f724744c4f2b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -969,6 +969,7 @@ struct ARMCPU { */ bool prop_pauth; bool prop_pauth_impdef; + bool has_pauth; /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint32_t dcz_blocksize; @@ -2115,6 +2116,7 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ + ARM_FEATURE_PAUTH, /* has pointer authentication support */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f42803ecaf1d..5a4386ce9218 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -760,10 +760,7 @@ static void aarch64_max_initfn(Object *obj) cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ #endif - - /* Default to PAUTH on, with the architected algorithm. */ - qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); - qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); + set_feature(&cpu->env, ARM_FEATURE_PAUTH); } aarch64_add_sve_properties(obj); @@ -835,8 +832,16 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) static void aarch64_cpu_instance_init(Object *obj) { ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); + ARMCPU *cpu = ARM_CPU(obj); acc->info->initfn(obj); + + /* Default to PAUTH on, with the architected algorithm. */ + if (arm_feature(&cpu->env, ARM_FEATURE_PAUTH)) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); + } + arm_cpu_post_init(obj); }