From patchwork Thu May 27 09:00:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12283801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD850C47089 for ; Thu, 27 May 2021 09:03:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EF5BA61355 for ; Thu, 27 May 2021 09:03:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EF5BA61355 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:51178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lmBvV-00075D-3U for qemu-devel@archiver.kernel.org; Thu, 27 May 2021 05:03:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lmBtI-0005nO-I5; Thu, 27 May 2021 05:01:20 -0400 Received: from out28-53.mail.aliyun.com ([115.124.28.53]:46155) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lmBtF-0006sX-FO; Thu, 27 May 2021 05:01:20 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07481217|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.117662-0.000361685-0.881976; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047203; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KJUGf1T_1622106065; Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KJUGf1T_1622106065) by smtp.aliyun-inc.com(10.147.41.178); Thu, 27 May 2021 17:01:05 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 1/1] target/riscv: Fix vsip vsie CSR ops in M and HS mode Date: Thu, 27 May 2021 17:00:51 +0800 Message-Id: <20210527090051.1837256-1-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: none client-ip=115.124.28.53; envelope-from=zhiwei_liu@c-sky.com; helo=out28-53.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair.Francis@wdc.com, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When V=1, instructions that normally read or modify a supervisor CSR shall instead access the corresponding VS CSR. And the VS CSRs can be accessed as themselves from M-mode or HS-mode. In M and HS mode, VSIP or VSIE should be written normally instead of shift by 1. Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fe5628fea6..0cce474d3d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -837,16 +837,16 @@ static RISCVException read_sie(CPURISCVState *env, int csrno, static RISCVException write_vsie(CPURISCVState *env, int csrno, target_ulong val) { - /* Shift the S bits to their VS bit location in mie */ target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | - ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS); + (val & env->hideleg & VS_MODE_INTERRUPTS); return write_mie(env, CSR_MIE, newval); } static int write_sie(CPURISCVState *env, int csrno, target_ulong val) { if (riscv_cpu_virt_enabled(env)) { - write_vsie(env, CSR_VSIE, val); + /* Shift the S bits to their VS bit location in mie */ + write_vsie(env, CSR_VSIE, val << 1); } else { target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS); @@ -950,12 +950,9 @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - /* Shift the S bits to their VS bit location in mip */ - int ret = rmw_mip(env, 0, ret_value, new_value << 1, - (write_mask << 1) & vsip_writable_mask & env->hideleg); + int ret = rmw_mip(env, 0, ret_value, new_value, + write_mask & vsip_writable_mask & env->hideleg); *ret_value &= VS_MODE_INTERRUPTS; - /* Shift the VS bits to their S bit location in vsip */ - *ret_value >>= 1; return ret; } @@ -966,7 +963,11 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno, int ret; if (riscv_cpu_virt_enabled(env)) { - ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); + /* Shift the S bits to their VS bit location in mip */ + ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value << 1, + write_mask << 1); + /* Shift the VS bits to their S bit location in vsip */ + *ret_value >>= 1; } else { ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask);