From patchwork Fri May 28 14:07:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12287085 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7034C2B9F7 for ; Fri, 28 May 2021 14:08:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 828DC613D1 for ; Fri, 28 May 2021 14:08:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236497AbhE1OJr (ORCPT ); Fri, 28 May 2021 10:09:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236502AbhE1OJn (ORCPT ); Fri, 28 May 2021 10:09:43 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC349C06174A; Fri, 28 May 2021 07:08:07 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id v13-20020a17090abb8db029015f9f7d7290so7325119pjr.0; Fri, 28 May 2021 07:08:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vS7pC/Zrqej82Rga5YQdc9qfSyupzEHK9rNj2l815Fo=; b=DD3YUrNELDiWKFad0IM5uQtj0QbMNcUyFT2NXEe3t7HQcCo1k7SwkPwKn/gk0ymcLg arxW0KkjQagzR172S6xS0MJQQwvDFyH07Zfa+VEsT0mzpizFLFlwma8MqHiQux+wsJbH hAAdekeE5cdNNIq5WPQtBgoUFxvEYYIpODTAQiaa8GUvwWII27bTf3sdoXUac5TDbCBT piKaZAAvh6yHvpFSGiV7lTWRnOSlX0LGwTELfRPix6xWqpCyMAc41qQjxmafk2m5v7mh OFCQUZ/0CJsQZNd1r5F0qKc7I33aog26QRHSLrWwfCX+61M7hnyNyFXr3ZDWXCFmj8Gc gsvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vS7pC/Zrqej82Rga5YQdc9qfSyupzEHK9rNj2l815Fo=; b=jUlmWkMGmrc6+cxFjil1hqei/pE62ATlqeuLynDJqew8KJnEe6t4Qku2VpZzXXS+z8 YCMnAeHmaV+txAOYt/EcnGjhlNdhxspF4WztNKMLgmZURY6zX4/rkhC4urv9l906Crl4 lkX3EByPgwtKNr5X7AdOPzFS7UiG59RYmFitHXjlrGHiQ1bs1mKYizX24SPTzkPUQUe7 +K2qc4msH75GNORHeSjxMYP8iWij+L27p6S4ug87rt1HWiPSMI+VGRYJI2/EQqGHxqWW /b/xlWzOQJ8gHDZvrZaYZzDBdkR+AGd7/xXeer70LmLD8P8sQTfcxrrfF/dwpt5jPsZO GFig== X-Gm-Message-State: AOAM531NqMxuKCHKN1ZsFzkS0Q8TbVlBh9lXPUdsxHfkvfmbKIUpC+KZ w6I7tATIJAR7VmH1LrE1K9c= X-Google-Smtp-Source: ABdhPJwFgsRmSPM4sJJTutVezieVao6rCCVr9iqHt5e0sFeDtC5nPiBqxi6ODzgNBuyC9ZxP0ZETdA== X-Received: by 2002:a17:90a:4a92:: with SMTP id f18mr4758982pjh.49.1622210887470; Fri, 28 May 2021 07:08:07 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.164]) by smtp.googlemail.com with ESMTPSA id j3sm4607841pfe.98.2021.05.28.07.08.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 07:08:07 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v4 1/7] PCI: Add pcie_reset_flr to follow calling convention of other reset methods Date: Fri, 28 May 2021 19:37:49 +0530 Message-Id: <20210528140755.7044-2-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210528140755.7044-1-ameynarkhede03@gmail.com> References: <20210528140755.7044-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Currently there is separate function pcie_has_flr to probe if pcie flr is supported by the device which does not match the calling convention followed by reset methods which use second function argument to decide whether to probe or not. Add new function pcie_reset_flr that follows the calling convention of reset methods. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/crypto/cavium/nitrox/nitrox_main.c | 4 +- drivers/pci/pci.c | 62 ++++++++++++---------- drivers/pci/pcie/aer.c | 12 ++--- drivers/pci/quirks.c | 9 ++-- include/linux/pci.h | 2 +- 5 files changed, 43 insertions(+), 46 deletions(-) diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c index facc8e6bc..15d6c8452 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_main.c +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c @@ -306,9 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev) return -ENOMEM; } - /* check flr support */ - if (pcie_has_flr(pdev)) - pcie_flr(pdev); + pcie_reset_flr(pdev, 0); pci_restore_state(pdev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8f79804c6..7cacb6d21 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4573,32 +4573,12 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev) } EXPORT_SYMBOL(pci_wait_for_pending_transaction); -/** - * pcie_has_flr - check if a device supports function level resets - * @dev: device to check - * - * Returns true if the device advertises support for PCIe function level - * resets. - */ -bool pcie_has_flr(struct pci_dev *dev) -{ - u32 cap; - - if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) - return false; - - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); - return cap & PCI_EXP_DEVCAP_FLR; -} -EXPORT_SYMBOL_GPL(pcie_has_flr); - /** * pcie_flr - initiate a PCIe function level reset * @dev: device to reset * - * Initiate a function level reset on @dev. The caller should ensure the - * device supports FLR before calling this function, e.g. by using the - * pcie_has_flr() helper. + * Initiate a function level reset unconditionally on @dev without + * checking any flags and DEVCAP */ int pcie_flr(struct pci_dev *dev) { @@ -4621,6 +4601,31 @@ int pcie_flr(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pcie_flr); +/** + * pcie_reset_flr - initiate a PCIe function level reset + * @dev: device to reset + * @probe: If set, only check if the device can be reset this way. + * + * Initiate a function level reset on @dev. + */ +int pcie_reset_flr(struct pci_dev *dev, int probe) +{ + u32 cap; + + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) + return -ENOTTY; + + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + if (!(cap & PCI_EXP_DEVCAP_FLR)) + return -ENOTTY; + + if (probe) + return 0; + + return pcie_flr(dev); +} +EXPORT_SYMBOL_GPL(pcie_reset_flr); + static int pci_af_flr(struct pci_dev *dev, int probe) { int pos; @@ -5100,11 +5105,9 @@ int __pci_reset_function_locked(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 0); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - if (rc != -ENOTTY) - return rc; - } + rc = pcie_reset_flr(dev, 0); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 0); if (rc != -ENOTTY) return rc; @@ -5135,8 +5138,9 @@ int pci_probe_reset_function(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 1); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) - return 0; + rc = pcie_reset_flr(dev, 1); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 1); if (rc != -ENOTTY) return rc; diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index ba2238834..f4e891bd5 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1405,13 +1405,11 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) } if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - pci_info(dev, "has been reset (%d)\n", rc); - } else { - pci_info(dev, "not reset (no FLR support)\n"); - rc = -ENOTTY; - } + rc = pcie_reset_flr(dev, 0); + if (!rc) + pci_info(dev, "has been reset\n"); + else + pci_info(dev, "not reset (no FLR support: %d)\n", rc); } else { rc = pci_bus_error_reset(dev); pci_info(dev, "%s Port link has been reset (%d)\n", diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 653660e3b..5318833f3 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3831,7 +3831,7 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) u32 cfg; if (dev->class != PCI_CLASS_STORAGE_EXPRESS || - !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) + pcie_reset_flr(dev, 1) || !pci_resource_start(dev, 0)) return -ENOTTY; if (probe) @@ -3900,13 +3900,10 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) */ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) { - if (!pcie_has_flr(dev)) - return -ENOTTY; + int ret = pcie_reset_flr(dev, probe); if (probe) - return 0; - - pcie_flr(dev); + return ret; msleep(250); diff --git a/include/linux/pci.h b/include/linux/pci.h index 86c799c97..35c8e9e7e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1217,7 +1217,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); void pcie_print_link_status(struct pci_dev *dev); -bool pcie_has_flr(struct pci_dev *dev); +int pcie_reset_flr(struct pci_dev *dev, int probe); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); From patchwork Fri May 28 14:07:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12287087 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12FC3C4708C for ; Fri, 28 May 2021 14:08:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E5460613B6 for ; Fri, 28 May 2021 14:08:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236502AbhE1OJt (ORCPT ); Fri, 28 May 2021 10:09:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236281AbhE1OJq (ORCPT ); Fri, 28 May 2021 10:09:46 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76B77C061763; Fri, 28 May 2021 07:08:11 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id v13so1670244ple.9; Fri, 28 May 2021 07:08:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sb4vaVbLXqrF4pGm+Dy3hXkAmePJygTBSkU6zsnjJc0=; b=u2L9Y6ZskZLbuJK/FB66mjS4a5SWhByGITBM1YIdMN/64BN3LJzjjaZcoUYKEqooyi avl+Wg6FhKrFd4XLnd+UueLNvJDtXxGJiHqPMZSxJCYwu3wW1sRiURnJ1HUZQ8r2i8mr Xtf6dIUdaoLqC/DbeqOBO7BmkLFeJmPOpXnkltUEqwWOUSF9z9bo4VA5ZDDZp1hxnexw grKYMFBpjhiDjOQz2T7D95sY8FP8yqR7/2cfkxH/5ObRpXvIySfyrEnrw3C2lAXJeRf9 a7wfqt7LEY0ecsPwOT6Ml8LX6AWZGohjuO/pg222jcXDsI2/M88NvAhFaQOfY/by6o42 5bNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sb4vaVbLXqrF4pGm+Dy3hXkAmePJygTBSkU6zsnjJc0=; b=diGag8iwr41s6/B+zoVfzY6ophM0zBeIzkSjf06UYilERUbqlzEbtf/H8pJxkJM9Aj zII/8KDLKmbUobyGhFZ8+rAJTEmg3t75bPLlyV+ddV72wrEa+en2y8TpzUp1vVhsZtcL dgxbTrq8X1CoLiIqOPyL9+4Lpgv09fZypQPi9ewDLtCzD0jRdtFpdB9/SH2AJyQXk9Re v4wwms6BFyySCcYpAQVC6zVQLhGcQ0O8ymKS3mU9COr/af0mQ+cpZvFdz96IyNiEsZ3q qg5dtFraOEgBBdQNlttH77fxjVOjVxSgr1o7jWtn/nrPGBh+DMh/cuVGz305Ck/l9x0Y iN+w== X-Gm-Message-State: AOAM5321M81XIcAJgbKB5ng7kwSAEirA2hu4jIWZkbnUs4jsmPxu2jgQ uUWlCa0dYF7VbG1QMN9UvFY= X-Google-Smtp-Source: ABdhPJxJol9aqhHeIF2sxDCKGRXRF5dXkJGK4S4JwXjiEKxvY0MyufwCv1PeAwCdZx4rJ14DqKP6sw== X-Received: by 2002:a17:90b:1b0a:: with SMTP id nu10mr4587527pjb.70.1622210890940; Fri, 28 May 2021 07:08:10 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.164]) by smtp.googlemail.com with ESMTPSA id j3sm4607841pfe.98.2021.05.28.07.08.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 07:08:10 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v4 2/7] PCI: Add new array for keeping track of ordering of reset methods Date: Fri, 28 May 2021 19:37:50 +0530 Message-Id: <20210528140755.7044-3-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210528140755.7044-1-ameynarkhede03@gmail.com> References: <20210528140755.7044-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Introduce a new array reset_methods in struct pci_dev to keep track of reset mechanisms supported by the device and their ordering. Also refactor probing and reset functions to take advantage of calling convention of reset functions. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/pci/pci.c | 107 ++++++++++++++++++++++++++------------------ drivers/pci/pci.h | 8 +++- drivers/pci/probe.c | 5 +-- include/linux/pci.h | 7 +++ 4 files changed, 80 insertions(+), 47 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7cacb6d21..cbdb5bd0d 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -72,6 +72,14 @@ static void pci_dev_d3_sleep(struct pci_dev *dev) msleep(delay); } +bool pci_reset_supported(struct pci_dev *dev) +{ + u8 null_reset_methods[PCI_RESET_METHODS_NUM] = { 0 }; + + return memcmp(null_reset_methods, + dev->reset_methods, PCI_RESET_METHODS_NUM); +} + #ifdef CONFIG_PCI_DOMAINS int pci_domains_supported = 1; #endif @@ -5068,6 +5076,19 @@ static void pci_dev_restore(struct pci_dev *dev) err_handler->reset_done(dev); } +/* + * The ordering for functions in pci_reset_fn_methods + * is required for reset_methods byte array defined + * in struct pci_dev. + */ +const struct pci_reset_fn_method pci_reset_fn_methods[] = { + { &pci_dev_specific_reset, .name = "device_specific" }, + { &pcie_reset_flr, .name = "flr" }, + { &pci_af_flr, .name = "af_flr" }, + { &pci_pm_reset, .name = "pm" }, + { &pci_reset_bus_function, .name = "bus" }, +}; + /** * __pci_reset_function_locked - reset a PCI device function while holding * the @dev mutex lock. @@ -5090,65 +5111,65 @@ static void pci_dev_restore(struct pci_dev *dev) */ int __pci_reset_function_locked(struct pci_dev *dev) { - int rc; + int i, rc = -ENOTTY; + u8 prio; might_sleep(); - /* - * A reset method returns -ENOTTY if it doesn't support this device - * and we should try the next method. - * - * If it returns 0 (success), we're finished. If it returns any - * other error, we're also finished: this indicates that further - * reset mechanisms might be broken on the device. - */ - rc = pci_dev_specific_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - return pci_reset_bus_function(dev, 0); + for (prio = PCI_RESET_METHODS_NUM; prio; prio--) { + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { + if (dev->reset_methods[i] == prio) { + /* + * A reset method returns -ENOTTY if it doesn't support this device + * and we should try the next method. + * + * If it returns 0 (success), we're finished. If it returns any + * other error, we're also finished: this indicates that further + * reset mechanisms might be broken on the device. + */ + rc = pci_reset_fn_methods[i].reset_fn(dev, 0); + if (rc != -ENOTTY) + return rc; + break; + } + } + if (i == PCI_RESET_METHODS_NUM) + break; + } + return rc; } EXPORT_SYMBOL_GPL(__pci_reset_function_locked); /** - * pci_probe_reset_function - check whether the device can be safely reset - * @dev: PCI device to reset + * pci_init_reset_methods - check whether device can be safely reset + * and store supported reset mechanisms. + * @dev: PCI device to check for reset mechanisms * * Some devices allow an individual function to be reset without affecting * other functions in the same device. The PCI device must be responsive - * to PCI config space in order to use this function. + * to reads and writes to its PCI config space in order to use this function. * - * Returns 0 if the device function can be reset or negative if the - * device doesn't support resetting a single function. + * Stores reset mechanisms supported by device in reset_methods byte array + * which is a member of struct pci_dev. */ -int pci_probe_reset_function(struct pci_dev *dev) +void pci_init_reset_methods(struct pci_dev *dev) { - int rc; + int i, rc; + u8 prio = PCI_RESET_METHODS_NUM; + u8 reset_methods[PCI_RESET_METHODS_NUM] = { 0 }; - might_sleep(); + BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_RESET_METHODS_NUM); - rc = pci_dev_specific_reset(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 1); - if (rc != -ENOTTY) - return rc; + might_sleep(); - return pci_reset_bus_function(dev, 1); + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { + rc = pci_reset_fn_methods[i].reset_fn(dev, 1); + if (!rc) + reset_methods[i] = prio--; + else if (rc != -ENOTTY) + break; + } + memcpy(dev->reset_methods, reset_methods, sizeof(reset_methods)); } /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index ef7c46613..1b3ba3116 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -39,7 +39,7 @@ enum pci_mmap_api { int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, enum pci_mmap_api mmap_api); -int pci_probe_reset_function(struct pci_dev *dev); +void pci_init_reset_methods(struct pci_dev *dev); int pci_bridge_secondary_bus_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev); @@ -612,6 +612,12 @@ struct pci_dev_reset_methods { int (*reset)(struct pci_dev *dev, int probe); }; +struct pci_reset_fn_method { + int (*reset_fn)(struct pci_dev *, int probe); + char *name; +}; + +extern const struct pci_reset_fn_method pci_reset_fn_methods[]; #ifdef CONFIG_PCI_QUIRKS int pci_dev_specific_reset(struct pci_dev *dev, int probe); #else diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 953f15abc..c5cfdd239 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2403,9 +2403,8 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rcec_init(dev); /* Root Complex Event Collector */ pcie_report_downtraining(dev); - - if (pci_probe_reset_function(dev) == 0) - dev->reset_fn = 1; + pci_init_reset_methods(dev); + dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/include/linux/pci.h b/include/linux/pci.h index 35c8e9e7e..738c0cadb 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -49,6 +49,8 @@ PCI_STATUS_SIG_TARGET_ABORT | \ PCI_STATUS_PARITY) +#define PCI_RESET_METHODS_NUM 5 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -506,6 +508,10 @@ struct pci_dev { char *driver_override; /* Driver name to force a match */ unsigned long priv_flags; /* Private flags for the PCI driver */ + /* + * See pci_reset_fn_methods array in pci.c for ordering. + */ + u8 reset_methods[PCI_RESET_METHODS_NUM]; /* Reset methods ordered by priority */ }; static inline struct pci_dev *pci_physfn(struct pci_dev *dev) @@ -1219,6 +1225,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, void pcie_print_link_status(struct pci_dev *dev); int pcie_reset_flr(struct pci_dev *dev, int probe); int pcie_flr(struct pci_dev *dev); +bool pci_reset_supported(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); int pci_reset_function_locked(struct pci_dev *dev); From patchwork Fri May 28 14:07:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12287089 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33F53C2B9F7 for ; Fri, 28 May 2021 14:08:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 16A3F613B6 for ; Fri, 28 May 2021 14:08:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236593AbhE1OJ4 (ORCPT ); Fri, 28 May 2021 10:09:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236525AbhE1OJu (ORCPT ); Fri, 28 May 2021 10:09:50 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A024C061574; Fri, 28 May 2021 07:08:14 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id 22so3307979pfv.11; Fri, 28 May 2021 07:08:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=akBlPiWHD54eFlP2beyMx41zh4qBgkL9tchdaD+JxHE=; b=Wr3MfgTtC3S+LO1as/bdIrVxuqG5cEOduuR4004WGgHXYIjg3tQOykRUiLGwhiUXL5 /ubPLr4xPm2GgRO+iIxaQFQlZzwnVwUtNuaGW0FxjJ3dJTjOHhf/FR/KdvvhBRezg6Ca JEdAZm2B8P5jo27rP49sfwIrezERJYKWBIHt2d+CbpwRP4HOT7VkCK2LhV53uuMJM9OU llup7+gQlqgIfp3lOQiLc66KYrsET6Tyf/6AtGc7uxFBHT7XnioGNjBExX1jqdLCZxvW cAuPz1yfuzHfrvBFYLPLMYu13TLhBJA6apWAnnlZLH1PR9dAlQC6KtjyroLg8r/tPmtq VO2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=akBlPiWHD54eFlP2beyMx41zh4qBgkL9tchdaD+JxHE=; b=Iuii591T/u+dJ6w7LInJHLHreACgtZt1mpACciLeStPHhJI8saSUMrAuNdEQk1u9i5 laBBRf/Osj30sBZyznDCZGcp06y79n/2Os3bFcvdcGHFyOzg1gzUlvny2wMN3VSjllYs d3J36V1K1LxzvJfNdvtqu9mqBgNXXU5VxgbzIWJCcFwGEUr4DIciM+llh6DtXIJzo3SH hDS8ta2cYfbg4XsHdbjfvxg7y2h6M104Dr2Eiz1lqWzlpiQacYoBXaBPdV9PVVJRF9Qu 5a9IqzqEBTsRd172K6539lVkPIXWm+LyIB22+vuMgCbsBk2BF4mE6LT8TeOmqL1pSeEy Lz3w== X-Gm-Message-State: AOAM530g5AWtcyvhM6Efo7INOUc/bMIsPn34B9gt9XciXQw+TE+Oprq1 cO3Jz1N0Vyd2jNr4zD0inn8= X-Google-Smtp-Source: ABdhPJwKmKrdthwVjSDM57qdkCu8M+LwOtWPt8kOwMyQ3XjdIjclgQndtJQPzT1bE5A9QUp4JtrpdA== X-Received: by 2002:a63:514f:: with SMTP id r15mr9009206pgl.374.1622210894169; Fri, 28 May 2021 07:08:14 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.164]) by smtp.googlemail.com with ESMTPSA id j3sm4607841pfe.98.2021.05.28.07.08.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 07:08:13 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v4 3/7] PCI: Remove reset_fn field from pci_dev Date: Fri, 28 May 2021 19:37:51 +0530 Message-Id: <20210528140755.7044-4-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210528140755.7044-1-ameynarkhede03@gmail.com> References: <20210528140755.7044-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org reset_fn field is used to indicate whether the device supports any reset mechanism or not. Deprecate use of reset_fn in favor of new reset_methods array which can be used to keep track of all supported reset mechanisms of a device and their ordering. The octeon driver is incorrectly using reset_fn field to detect if the device supports FLR or not. Use pcie_reset_flr to probe whether it supports FLR or not. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/net/ethernet/cavium/liquidio/lio_vf_main.c | 2 +- drivers/pci/pci-sysfs.c | 6 ++---- drivers/pci/pci.c | 6 +++--- drivers/pci/probe.c | 1 - drivers/pci/quirks.c | 2 +- include/linux/pci.h | 1 - 6 files changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c index 516f166ce..336d149ee 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c @@ -526,7 +526,7 @@ static void octeon_destroy_resources(struct octeon_device *oct) oct->irq_name_storage = NULL; } /* Soft reset the octeon device before exiting */ - if (oct->pci_dev->reset_fn) + if (!pcie_reset_flr(oct->pci_dev, 1)) octeon_pci_flr(oct); else cn23xx_vf_ask_pf_to_do_flr(oct); diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index f8afd54ca..388895099 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1334,7 +1334,7 @@ static int pci_create_capabilities_sysfs(struct pci_dev *dev) pcie_vpd_create_sysfs_dev_files(dev); - if (dev->reset_fn) { + if (pci_reset_supported(dev)) { retval = device_create_file(&dev->dev, &dev_attr_reset); if (retval) goto error; @@ -1417,10 +1417,8 @@ int __must_check pci_create_sysfs_dev_files(struct pci_dev *pdev) static void pci_remove_capabilities_sysfs(struct pci_dev *dev) { pcie_vpd_remove_sysfs_dev_files(dev); - if (dev->reset_fn) { + if (pci_reset_supported(dev)) device_remove_file(&dev->dev, &dev_attr_reset); - dev->reset_fn = 0; - } } /** diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index cbdb5bd0d..fad209c5f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5192,7 +5192,7 @@ int pci_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_lock(dev); @@ -5228,7 +5228,7 @@ int pci_reset_function_locked(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_save_and_disable(dev); @@ -5251,7 +5251,7 @@ int pci_try_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; if (!pci_dev_trylock(dev)) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index c5cfdd239..4764e031a 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2404,7 +2404,6 @@ static void pci_init_capabilities(struct pci_dev *dev) pcie_report_downtraining(dev); pci_init_reset_methods(dev); - dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 5318833f3..8f47d139c 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5535,7 +5535,7 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || pdev->subsystem_device != 0x222e || - !pdev->reset_fn) + !pci_reset_supported(pdev)) return; if (pci_enable_device_mem(pdev)) diff --git a/include/linux/pci.h b/include/linux/pci.h index 738c0cadb..e9603d638 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -429,7 +429,6 @@ struct pci_dev { unsigned int state_saved:1; unsigned int is_physfn:1; unsigned int is_virtfn:1; - unsigned int reset_fn:1; unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ From patchwork Fri May 28 14:07:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12287091 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4201EC47087 for ; Fri, 28 May 2021 14:08:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1FCF0613B6 for ; Fri, 28 May 2021 14:08:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236598AbhE1OJ5 (ORCPT ); Fri, 28 May 2021 10:09:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236564AbhE1OJw (ORCPT ); Fri, 28 May 2021 10:09:52 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAC3FC061763; Fri, 28 May 2021 07:08:17 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id u7so1688944plq.4; Fri, 28 May 2021 07:08:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nu1k1tGDq0snirEw7ma5Tb6EEXyl6eSPsLQoQU6sDGs=; b=gWBChIjxkhzZ6vyp35//4UkPzaUHFwStUa0JHUxswYe1aI5Z/OzmQNnyxhRaDWfFX3 BtJpGKwAY3h3XAHfXkDguRD9MGiCUvybQ70JebK58C669mtSa3jUJbAtpAO363UEhA/u FFB8QeySX0jRf+Wod/HXRtmQWTr4kI+Q28XvtA8nXsHhLo7/esGowBZRHuAStYe+EcTZ 54kOBEmz2o4/MbrDwy/XvPeqPZin6wuuUsnxuwVg1IgNaftCrIdD04Jn+ulXVnKp/PJB 6j2gvQvZx2cbOnRRYFcUGgasehhPBUburHcyffXU43JwbsJpYcAGCteAvWngaVeZoSE0 B6rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nu1k1tGDq0snirEw7ma5Tb6EEXyl6eSPsLQoQU6sDGs=; b=QzfB2DRyNIBprL/eE5tKrWZhzxZCECEouui6xAx7a3fslfJ4gfEya0X8geUQmz9rSQ aTaC5tyDn4VrZKxoIjtbEpyBmPuW//S1xmamjOx3mRHOVEEbUCsQdeckF6CGdu3miJ8p qRDTbbcOdsO/ZR6S296nHudE2IVF5sNJdXXXoPxnW5GBCyzv+yH23169u8Ni0Cr3XVJW 6yZSCn0lSAt1+++3hDOnSamuwzmjeArkq5EgOHS9hmtq+ESvyFW/fgHlYsSq90X6Lgix B/IxK7T28Jt4nnK0nAqXwXW+oLz+Db1TgTuZWSPSsVoFcdfITRnTDErK/MvSpChDSpy4 rvAA== X-Gm-Message-State: AOAM533/ckJcjNsTQ7tNsv9QPle/kNetsOxBYIn6j6lfTXPwWhQ+jXgE 84Xy7gxbcGmO98PXbXRDUB0= X-Google-Smtp-Source: ABdhPJyT99+g9MUc01FczSveF5/WicBH4THTektQhejGnXcGyCK04CeO0ocXuxBfYV8MA+yGyEf+EQ== X-Received: by 2002:a17:90a:549:: with SMTP id h9mr4880480pjf.158.1622210897339; Fri, 28 May 2021 07:08:17 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.164]) by smtp.googlemail.com with ESMTPSA id j3sm4607841pfe.98.2021.05.28.07.08.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 07:08:17 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v4 4/7] PCI/sysfs: Allow userspace to query and set device reset mechanism Date: Fri, 28 May 2021 19:37:52 +0530 Message-Id: <20210528140755.7044-5-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210528140755.7044-1-ameynarkhede03@gmail.com> References: <20210528140755.7044-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add reset_method sysfs attribute to enable user to query and set user preferred device reset methods and their ordering. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- Documentation/ABI/testing/sysfs-bus-pci | 16 +++++ drivers/pci/pci-sysfs.c | 96 ++++++++++++++++++++++++- 2 files changed, 109 insertions(+), 3 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index 25c9c3977..36fba7ebf 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -121,6 +121,22 @@ Description: child buses, and re-discover devices removed earlier from this part of the device tree. +What: /sys/bus/pci/devices/.../reset_method +Date: March 2021 +Contact: Amey Narkhede +Description: + Some devices allow an individual function to be reset + without affecting other functions in the same slot. + For devices that have this support, a file named reset_method + will be present in sysfs. Reading this file will give names + of the device supported reset methods and their ordering. + Writing the name or comma separated list of names of any of + the device supported reset methods to this file will set the + reset methods and their ordering to be used when resetting + the device. Writing empty string to this file will disable + ability to reset the device and writing "default" will return + to the original value. + What: /sys/bus/pci/devices/.../reset Date: July 2009 Contact: Michael S. Tsirkin diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 388895099..1c715b262 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1304,6 +1304,89 @@ static const struct bin_attribute pcie_config_attr = { .write = pci_write_config, }; +static ssize_t reset_method_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + ssize_t len = 0; + int i, prio; + + for (prio = PCI_RESET_METHODS_NUM; prio; prio--) { + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { + if (prio == pdev->reset_methods[i]) { + len += sysfs_emit_at(buf, len, "%s%s", + len ? "," : "", + pci_reset_fn_methods[i].name); + break; + } + } + + if (i == PCI_RESET_METHODS_NUM) + break; + } + + return len; +} + +static ssize_t reset_method_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u8 reset_methods[PCI_RESET_METHODS_NUM]; + struct pci_dev *pdev = to_pci_dev(dev); + u8 prio = PCI_RESET_METHODS_NUM; + char *name; + int i; + + /* + * Initialize reset_method such that 0xff indicates + * supported but not currently enabled reset methods + * as we only use priority values which are within + * the range of PCI_RESET_FN_METHODS array size + */ + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) + reset_methods[i] = pdev->reset_methods[i] ? 0xff : 0; + + if (sysfs_streq(buf, "")) { + pci_warn(pdev, "All device reset methods disabled by user"); + goto set_reset_methods; + } + + if (sysfs_streq(buf, "default")) { + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) + reset_methods[i] = reset_methods[i] ? prio-- : 0; + goto set_reset_methods; + } + + while ((name = strsep((char **)&buf, ",")) != NULL) { + if (!strlen(name)) + continue; + + name = strim(name); + + for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { + if (reset_methods[i] && + sysfs_streq(name, pci_reset_fn_methods[i].name)) { + reset_methods[i] = prio--; + break; + } + } + if (i == PCI_RESET_METHODS_NUM) + return -EINVAL; + } + + if (reset_methods[0] && + reset_methods[0] != PCI_RESET_METHODS_NUM) + pci_warn(pdev, "Device specific reset disabled/de-prioritized by user"); + +set_reset_methods: + memcpy(pdev->reset_methods, reset_methods, sizeof(reset_methods)); + return count; +} + +static DEVICE_ATTR_RW(reset_method); + static ssize_t reset_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -1337,11 +1420,16 @@ static int pci_create_capabilities_sysfs(struct pci_dev *dev) if (pci_reset_supported(dev)) { retval = device_create_file(&dev->dev, &dev_attr_reset); if (retval) - goto error; + goto err_reset; + retval = device_create_file(&dev->dev, &dev_attr_reset_method); + if (retval) + goto err_method; } return 0; -error: +err_method: + device_remove_file(&dev->dev, &dev_attr_reset); +err_reset: pcie_vpd_remove_sysfs_dev_files(dev); return retval; } @@ -1417,8 +1505,10 @@ int __must_check pci_create_sysfs_dev_files(struct pci_dev *pdev) static void pci_remove_capabilities_sysfs(struct pci_dev *dev) { pcie_vpd_remove_sysfs_dev_files(dev); - if (pci_reset_supported(dev)) + if (pci_reset_supported(dev)) { device_remove_file(&dev->dev, &dev_attr_reset); + device_remove_file(&dev->dev, &dev_attr_reset_method); + } } /** From patchwork Fri May 28 14:07:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12287093 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C9B4C4708C for ; Fri, 28 May 2021 14:08:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E99CC611CA for ; Fri, 28 May 2021 14:08:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236602AbhE1OJ7 (ORCPT ); Fri, 28 May 2021 10:09:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236589AbhE1OJz (ORCPT ); Fri, 28 May 2021 10:09:55 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0699C06138B; Fri, 28 May 2021 07:08:20 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id z4so1671626plg.8; Fri, 28 May 2021 07:08:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+kjX7vYmWzq1R7BiwbLx/rhOeELktigh7hpXVvkPMNY=; b=M+rVx+dkVP1vUeMpsr3lOGvUkiEkAWDTmytwA/1aSCM0Gq6G11rlHFqFl2xY2zUyvW uvY/s0AMgQ0v7hjE7YTbri3uq67NUEq0aI3FaPKC2OLhKJyO/QBbZ989Bs4B4qcTtzA1 fpOzEJSga93LcFdQ/o/TT7nq+FoiH45Rn9sKwiazDm5SXHQzcpiRCHOCrPC6olbAAq/W 0b9DY5ybDyvJubogGHvCbxOAoBkEx3m3X6bT0+57OGciviiHpHdsuzFcWABGkYq/Kg8H l93bNEgXSwl0L6ukAvNj0Rxyr9got9wxRNbe0xyN9cXgXgeHIY92mFSSQEiR3wfuS3mk Mykw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+kjX7vYmWzq1R7BiwbLx/rhOeELktigh7hpXVvkPMNY=; b=Cr+NG2FzHIKFzTeXhHXS/+im0cMn02OHytvngP61ERTcIQN1mjMhllVYzw9KG3Sqaz QbnjctnUvFHHOIPQ7BilddNP2KdBNP3H3DDWo3GXS4WmfjSoroSxbfIMuJ6sr4JRerUe I+SaLkQ4K6/NBw13ggRENS7FWwk1hx5SVLkNYs7KBaET+gYbhSMV+KV3Z3s4wcSXHonS fonWjMpD/8tMwVCUqEMoa9vPwIPWYSx7UXHHNfezv7I7cS1nsriAvFkYyL0AbYfI6+GT HzVSwYYxu9/0kjF2JQLY12oVxe9V2PjdjUJGDkRoCA/BtUdfXH4JZVK8L1KL7s0G+AF8 iFEw== X-Gm-Message-State: AOAM533mJe/Nm7oBLJkGaIn2T1uwAJzteOeIenVHceFm0KoJdxioVC7k Vl1OSpS1uCv+JqcZ2O4FMtA= X-Google-Smtp-Source: ABdhPJxIyWOF5cMnlxq8QgYXZ4P0pfmCenTjjdt7mBHHcpLlPW5B8J1uJ6OwsgDHd/HQpWfTlJUd7Q== X-Received: by 2002:a17:90a:e391:: with SMTP id b17mr4546463pjz.75.1622210900254; Fri, 28 May 2021 07:08:20 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.164]) by smtp.googlemail.com with ESMTPSA id j3sm4607841pfe.98.2021.05.28.07.08.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 07:08:20 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya Subject: [PATCH v4 5/7] PCI: Add support for a function level reset based on _RST method Date: Fri, 28 May 2021 19:37:53 +0530 Message-Id: <20210528140755.7044-6-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210528140755.7044-1-ameynarkhede03@gmail.com> References: <20210528140755.7044-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Shanker Donthineni The _RST is a standard method specified in the ACPI specification. It provides a function level reset when it is described in the acpi_device context associated with PCI-device. Implement a new reset function pci_dev_acpi_reset() for probing RST method and execute if it is defined in the firmware. The ACPI binding information is available only after calling device_add(), so move pci_init_reset_methods() to end of the pci_device_add(). The default priority of the acpi reset is set to below device-specific and above hardware resets. Signed-off-by: Shanker Donthineni Reviewed-by: Sinan Kaya --- drivers/pci/pci.c | 30 ++++++++++++++++++++++++++++++ drivers/pci/probe.c | 2 +- include/linux/pci.h | 2 +- 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index fad209c5f..1d859b100 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5076,6 +5076,35 @@ static void pci_dev_restore(struct pci_dev *dev) err_handler->reset_done(dev); } +/** + * pci_dev_acpi_reset - do a function level reset using _RST method + * @dev: device to reset + * @probe: check if _RST method is included in the acpi_device context. + */ +static int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +{ +#ifdef CONFIG_ACPI + acpi_handle handle = ACPI_HANDLE(&dev->dev); + + /* Return -ENOTTY if _RST method is not included in the dev context */ + if (!handle || !acpi_has_method(handle, "_RST")) + return -ENOTTY; + + /* Return 0 for probe phase indicating that we can reset this device */ + if (probe) + return 0; + + /* Invoke _RST() method to perform a function level reset */ + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { + pci_warn(dev, "Failed to reset the device\n"); + return -EINVAL; + } + return 0; +#else + return -ENOTTY; +#endif +} + /* * The ordering for functions in pci_reset_fn_methods * is required for reset_methods byte array defined @@ -5083,6 +5112,7 @@ static void pci_dev_restore(struct pci_dev *dev) */ const struct pci_reset_fn_method pci_reset_fn_methods[] = { { &pci_dev_specific_reset, .name = "device_specific" }, + { &pci_dev_acpi_reset, .name = "acpi" }, { &pcie_reset_flr, .name = "flr" }, { &pci_af_flr, .name = "af_flr" }, { &pci_pm_reset, .name = "pm" }, diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4764e031a..d4becd6ff 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2403,7 +2403,6 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rcec_init(dev); /* Root Complex Event Collector */ pcie_report_downtraining(dev); - pci_init_reset_methods(dev); } /* @@ -2494,6 +2493,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) dev->match_driver = false; ret = device_add(&dev->dev); WARN_ON(ret < 0); + pci_init_reset_methods(dev); } struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) diff --git a/include/linux/pci.h b/include/linux/pci.h index e9603d638..9bec3c616 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -49,7 +49,7 @@ PCI_STATUS_SIG_TARGET_ABORT | \ PCI_STATUS_PARITY) -#define PCI_RESET_METHODS_NUM 5 +#define PCI_RESET_METHODS_NUM 6 /* * The PCI interface treats multi-function devices as independent From patchwork Fri May 28 14:07:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12287095 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3AAAC2B9F7 for ; Fri, 28 May 2021 14:08:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B36B4611CA for ; Fri, 28 May 2021 14:08:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236623AbhE1OKC (ORCPT ); Fri, 28 May 2021 10:10:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236573AbhE1OJ6 (ORCPT ); Fri, 28 May 2021 10:09:58 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95635C06174A; Fri, 28 May 2021 07:08:23 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id g24so2588538pji.4; Fri, 28 May 2021 07:08:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3JYP5XsOiLfJxNy8HHCt4jYw4Wi2NfvdBjfhoJ7nFYY=; b=tUliXJXbMmG/pH8QpmThjV+2lRvC3rsw5IZsYmZozdvlmUxvEkQZwQEz6eter9Qe0H QPzUchiCRgwlDAwjN9IOGRTzvGXk3prGPj/+Qg5alh38Ap/AsfXgNL+2O+KADAPJiael 9vT1fTrt++3sR3yMX6Sq60M4fBoMFHooLO6ROHumSPv9glLwmkz9raM19dTZZVWGkvkf OV+aZGuGTj6BwnnDm1kXH3n74HGtKtKQThnW4VOHTyCCVSUGM/M8KduGHJ5ZD/Uhm/QO cvPxuASfa+YlbTjzyQ4Ajqm4o1kGK/I8kbylolglTVw0jAxI+wB+Ld+71SVytAbTmWSl F9dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3JYP5XsOiLfJxNy8HHCt4jYw4Wi2NfvdBjfhoJ7nFYY=; b=PlC24n/9/1ywVD2A0g+pyah8aehd0Gr98dFH3OiVGAhazRmXL8/w4eDzl/hycvVkNb mh/A4rJ0JRES9nMcrHNCHRKU2e+KqjXNqN0j/aM702TMgUNdzk8ZZgZPwiFozdknE/AO nWXBt6X8eLew2QvAKCeL/ZdHSWgkzzkttjBSuqpfzQja8shGXc1N+NzfdjE1F07LCRJb eVygFiqSrVUaOz0N5ukZZ0rlFAv8jOueZOVN34FIz/tcZepqn6AyFgqOwyVUqZ0k3YZq dmV1GWO6Pu03Ni4JgHJzATOU+142zez5/94OkxFfYQNGx5lqHRZhzpI1gtMQoJeqqj/m Ajnw== X-Gm-Message-State: AOAM530Bg6j3BBOrAOf1liFVJ+fIcGKo3lPWyjka3jFX6B3VjrM5WADJ jDhWI7KxkNnDQnZdM9Gb3mA= X-Google-Smtp-Source: ABdhPJwI31Xx6M47HXYNvDg7dl4oW7DLRRnIdWwF0Ubp78Fe/uQuJ3nvoTUfdvkwvuKqtXSEa+mA8Q== X-Received: by 2002:a17:902:ba88:b029:ee:f232:d13a with SMTP id k8-20020a170902ba88b02900eef232d13amr8467668pls.44.1622210903181; Fri, 28 May 2021 07:08:23 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.164]) by smtp.googlemail.com with ESMTPSA id j3sm4607841pfe.98.2021.05.28.07.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 07:08:22 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya Subject: [PATCH v4 6/7] PCI: Enable NO_BUS_RESET quirk for Nvidia GPUs Date: Fri, 28 May 2021 19:37:54 +0530 Message-Id: <20210528140755.7044-7-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210528140755.7044-1-ameynarkhede03@gmail.com> References: <20210528140755.7044-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Shanker Donthineni On select platforms, some Nvidia GPU devices do not work with SBR. Triggering SBR would leave the device inoperable for the current system boot. It requires a system hard-reboot to get the GPU device back to normal operating condition post-SBR. For the affected devices, enable NO_BUS_RESET quirk to fix the issue. This issue will be fixed in the next generation of hardware. Signed-off-by: Shanker Donthineni Reviewed-by: Sinan Kaya --- drivers/pci/quirks.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 8f47d139c..ceec67342 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3558,6 +3558,18 @@ static void quirk_no_bus_reset(struct pci_dev *dev) dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; } +/* + * Some Nvidia GPU devices do not work with bus reset, SBR needs to be + * prevented for those affected devices. + */ +static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) +{ + if ((dev->device & 0xffc0) == 0x2340) + quirk_no_bus_reset(dev); +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + quirk_nvidia_no_bus_reset); + /* * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. * The device will throw a Link Down error on AER-capable systems and From patchwork Fri May 28 14:07:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: ameynarkhede03 X-Patchwork-Id: 12287097 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4C0CC4708C for ; Fri, 28 May 2021 14:08:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96AFF611CA for ; Fri, 28 May 2021 14:08:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236542AbhE1OKM (ORCPT ); Fri, 28 May 2021 10:10:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236547AbhE1OKC (ORCPT ); Fri, 28 May 2021 10:10:02 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4595AC06174A; Fri, 28 May 2021 07:08:27 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id d16so3297693pfn.12; Fri, 28 May 2021 07:08:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=isJ9z6ugfRoVnDfFAPww9F4VNE0zuJxBi+y99gFCu4c=; b=HguWFbmsBEX+rj18bK0k0ZsLmV5FWg4Q3qMOq4smXmBXRT9WTFff+hwOVnEMg3i42M +UwR2Dl3C9WhVhK3G5avLHtQGQ1V3VpoblhxZBcTabqV379Ya63Y7bywdzCSMH2oV371 GpMZMWDZ4fDwv/+5yKuUgORH7qWvrwSjf2Zl0hWqxiI+8TogRiIdptU+mnPOyktNmK59 EObEYa8bQ8a4+zbGMYmG49tFNpZ8KZw2p8sGyFQb+O60+nuyOxH+E8M7dbQ9kJ41VQsr ILaJPUJtMhEQzPNG5bdzUGZS5yAlELgdIE/elr+u0nrw/j+Eg76oL2pJN/o2S6p2MN4V oqWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=isJ9z6ugfRoVnDfFAPww9F4VNE0zuJxBi+y99gFCu4c=; b=ieaU7QTrmDe/wotZ8m6VLqxlnzX3WLdcxaG91Wtx5jVF15NzjhzrsJcS/JZTIkrDXd iDYAunKszFT555iCU+INc9yK7exc4FNSnKDTR6+UgfpQlXE00n0gBF25ATJCrYuBpo1G DdhCRUeidP6hFsIQeCvDXjzcIZgmgIwpUTR6zzWmSHbfB9DnzvUgWgvZdreg4yINMiU+ u9odnNK3Or6xiQdm/kUf03HbB+B9M1Mx5h0r6WFbkdkHDmF8bFReNoQNK462ddEZJ9Oi rIpQnRL2flrsl1gQDY2x53TpyS0gKyRyevcD4+CVAbdBwddR9awEuYtX0ANJFYjlETj1 9mkw== X-Gm-Message-State: AOAM5334BDXPy+ZdXxNDDD1+cIKOy89MfSGZFpFPypEPAAsD6gFzo5Jg 8SGE9l6s0vitjCm1lE93pYQ= X-Google-Smtp-Source: ABdhPJyhgHI201e6yYuLKf5q8lOuZT02z3I0W9nXrJrb9Tbzoysbj1MLjpiOOAuaRiPXdNoUitZbfw== X-Received: by 2002:a63:e20b:: with SMTP id q11mr9073404pgh.307.1622210906682; Fri, 28 May 2021 07:08:26 -0700 (PDT) Received: from localhost.localdomain ([103.248.31.164]) by smtp.googlemail.com with ESMTPSA id j3sm4607841pfe.98.2021.05.28.07.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 07:08:26 -0700 (PDT) From: Amey Narkhede To: Bjorn Helgaas Cc: alex.williamson@redhat.com, Raphael Norwitz , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kw@linux.com, Shanker Donthineni , Sinan Kaya , Amey Narkhede Subject: [PATCH v4 7/7] PCI: Change the type of probe argument in reset functions Date: Fri, 28 May 2021 19:37:55 +0530 Message-Id: <20210528140755.7044-8-ameynarkhede03@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210528140755.7044-1-ameynarkhede03@gmail.com> References: <20210528140755.7044-1-ameynarkhede03@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Introduce a new enum pci_reset_mode_t to make the context of probe argument in reset functions clear and the code easier to read. Change the type of probe argument in functions which implement reset methods from int to pci_reset_mode_t to make the intent clear. Add a new line in return statement of pci_reset_bus_function. Suggested-by: Alex Williamson Suggested-by: Krzysztof Wilczyński Signed-off-by: Amey Narkhede --- drivers/crypto/cavium/nitrox/nitrox_main.c | 2 +- .../ethernet/cavium/liquidio/lio_vf_main.c | 2 +- drivers/pci/hotplug/pciehp.h | 2 +- drivers/pci/hotplug/pciehp_hpc.c | 7 +- drivers/pci/pci.c | 95 ++++++++++++------- drivers/pci/pci.h | 8 +- drivers/pci/pcie/aer.c | 2 +- drivers/pci/quirks.c | 33 ++++--- include/linux/pci.h | 8 +- include/linux/pci_hotplug.h | 2 +- 10 files changed, 103 insertions(+), 58 deletions(-) -- 2.31.1 diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c index 15d6c8452..f97fa8e99 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_main.c +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c @@ -306,7 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev) return -ENOMEM; } - pcie_reset_flr(pdev, 0); + pcie_reset_flr(pdev, PCI_RESET_DO_RESET); pci_restore_state(pdev); diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c index 336d149ee..6e666be69 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c @@ -526,7 +526,7 @@ static void octeon_destroy_resources(struct octeon_device *oct) oct->irq_name_storage = NULL; } /* Soft reset the octeon device before exiting */ - if (!pcie_reset_flr(oct->pci_dev, 1)) + if (!pcie_reset_flr(oct->pci_dev, PCI_RESET_PROBE)) octeon_pci_flr(oct); else cn23xx_vf_ask_pf_to_do_flr(oct); diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index 4fd200d8b..87da03adc 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h @@ -181,7 +181,7 @@ void pciehp_release_ctrl(struct controller *ctrl); int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot); int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot); -int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe); +int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, pci_reset_mode_t mode); int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status); int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status); int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status); diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index fb3840e22..a99b828ae 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -834,14 +834,17 @@ void pcie_disable_interrupt(struct controller *ctrl) * momentarily, if we see that they could interfere. Also, clear any spurious * events after. */ -int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe) +int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, pci_reset_mode_t mode) { struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 stat_mask = 0, ctrl_mask = 0; int rc; - if (probe) + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + + if (mode == PCI_RESET_PROBE) return 0; down_write(&ctrl->reset_lock); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1d859b100..c6fef081c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4616,10 +4616,13 @@ EXPORT_SYMBOL_GPL(pcie_flr); * * Initiate a function level reset on @dev. */ -int pcie_reset_flr(struct pci_dev *dev, int probe) +int pcie_reset_flr(struct pci_dev *dev, pci_reset_mode_t mode) { u32 cap; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) return -ENOTTY; @@ -4627,18 +4630,21 @@ int pcie_reset_flr(struct pci_dev *dev, int probe) if (!(cap & PCI_EXP_DEVCAP_FLR)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; return pcie_flr(dev); } EXPORT_SYMBOL_GPL(pcie_reset_flr); -static int pci_af_flr(struct pci_dev *dev, int probe) +static int pci_af_flr(struct pci_dev *dev, pci_reset_mode_t mode) { int pos; u8 cap; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + pos = pci_find_capability(dev, PCI_CAP_ID_AF); if (!pos) return -ENOTTY; @@ -4650,7 +4656,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe) if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* @@ -4693,10 +4699,13 @@ static int pci_af_flr(struct pci_dev *dev, int probe) * by default (i.e. unless the @dev's d3hot_delay field has a different value). * Moreover, only devices in D0 can be reset by this function. */ -static int pci_pm_reset(struct pci_dev *dev, int probe) +static int pci_pm_reset(struct pci_dev *dev, pci_reset_mode_t mode) { u16 csr; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4704,7 +4713,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) if (csr & PCI_PM_CTRL_NO_SOFT_RESET) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; if (dev->current_state != PCI_D0) @@ -4953,10 +4962,13 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); -static int pci_parent_bus_reset(struct pci_dev *dev, int probe) +static int pci_parent_bus_reset(struct pci_dev *dev, pci_reset_mode_t mode) { struct pci_dev *pdev; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) return -ENOTTY; @@ -4965,43 +4977,53 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe) if (pdev != dev) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; return pci_bridge_secondary_bus_reset(dev->bus->self); } -static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) +static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, pci_reset_mode_t mode) { int rc = -ENOTTY; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!hotplug || !try_module_get(hotplug->owner)) return rc; if (hotplug->ops->reset_slot) - rc = hotplug->ops->reset_slot(hotplug, probe); + rc = hotplug->ops->reset_slot(hotplug, mode); module_put(hotplug->owner); return rc; } -static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) +static int pci_dev_reset_slot_function(struct pci_dev *dev, pci_reset_mode_t mode) { + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (dev->multifunction || dev->subordinate || !dev->slot || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) return -ENOTTY; - return pci_reset_hotplug_slot(dev->slot->hotplug, probe); + return pci_reset_hotplug_slot(dev->slot->hotplug, mode); } -static int pci_reset_bus_function(struct pci_dev *dev, int probe) +static int pci_reset_bus_function(struct pci_dev *dev, pci_reset_mode_t mode) { - int rc = pci_dev_reset_slot_function(dev, probe); + int rc = pci_dev_reset_slot_function(dev, mode); + + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; if (rc != -ENOTTY) return rc; - return pci_parent_bus_reset(dev, probe); + + return pci_parent_bus_reset(dev, mode); } static void pci_dev_lock(struct pci_dev *dev) @@ -5081,17 +5103,20 @@ static void pci_dev_restore(struct pci_dev *dev) * @dev: device to reset * @probe: check if _RST method is included in the acpi_device context. */ -static int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +static int pci_dev_acpi_reset(struct pci_dev *dev, pci_reset_mode_t mode) { #ifdef CONFIG_ACPI acpi_handle handle = ACPI_HANDLE(&dev->dev); + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + /* Return -ENOTTY if _RST method is not included in the dev context */ if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; /* Return 0 for probe phase indicating that we can reset this device */ - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* Invoke _RST() method to perform a function level reset */ @@ -5157,7 +5182,7 @@ int __pci_reset_function_locked(struct pci_dev *dev) * other error, we're also finished: this indicates that further * reset mechanisms might be broken on the device. */ - rc = pci_reset_fn_methods[i].reset_fn(dev, 0); + rc = pci_reset_fn_methods[i].reset_fn(dev, PCI_RESET_DO_RESET); if (rc != -ENOTTY) return rc; break; @@ -5193,7 +5218,7 @@ void pci_init_reset_methods(struct pci_dev *dev) might_sleep(); for (i = 0; i < PCI_RESET_METHODS_NUM; i++) { - rc = pci_reset_fn_methods[i].reset_fn(dev, 1); + rc = pci_reset_fn_methods[i].reset_fn(dev, PCI_RESET_PROBE); if (!rc) reset_methods[i] = prio--; else if (rc != -ENOTTY) @@ -5509,21 +5534,24 @@ static void pci_slot_restore_locked(struct pci_slot *slot) } } -static int pci_slot_reset(struct pci_slot *slot, int probe) +static int pci_slot_reset(struct pci_slot *slot, pci_reset_mode_t mode) { int rc; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!slot || !pci_slot_resetable(slot)) return -ENOTTY; - if (!probe) + if (mode == PCI_RESET_DO_RESET) pci_slot_lock(slot); might_sleep(); - rc = pci_reset_hotplug_slot(slot->hotplug, probe); + rc = pci_reset_hotplug_slot(slot->hotplug, mode); - if (!probe) + if (mode == PCI_RESET_DO_RESET) pci_slot_unlock(slot); return rc; @@ -5537,7 +5565,7 @@ static int pci_slot_reset(struct pci_slot *slot, int probe) */ int pci_probe_reset_slot(struct pci_slot *slot) { - return pci_slot_reset(slot, 1); + return pci_slot_reset(slot, PCI_RESET_PROBE); } EXPORT_SYMBOL_GPL(pci_probe_reset_slot); @@ -5560,14 +5588,14 @@ static int __pci_reset_slot(struct pci_slot *slot) { int rc; - rc = pci_slot_reset(slot, 1); + rc = pci_slot_reset(slot, PCI_RESET_PROBE); if (rc) return rc; if (pci_slot_trylock(slot)) { pci_slot_save_and_disable_locked(slot); might_sleep(); - rc = pci_reset_hotplug_slot(slot->hotplug, 0); + rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); pci_slot_restore_locked(slot); pci_slot_unlock(slot); } else @@ -5576,14 +5604,17 @@ static int __pci_reset_slot(struct pci_slot *slot) return rc; } -static int pci_bus_reset(struct pci_bus *bus, int probe) +static int pci_bus_reset(struct pci_bus *bus, pci_reset_mode_t mode) { int ret; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!bus->self || !pci_bus_resetable(bus)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; pci_bus_lock(bus); @@ -5622,14 +5653,14 @@ int pci_bus_error_reset(struct pci_dev *bridge) goto bus_reset; list_for_each_entry(slot, &bus->slots, list) - if (pci_slot_reset(slot, 0)) + if (pci_slot_reset(slot, PCI_RESET_DO_RESET)) goto bus_reset; mutex_unlock(&pci_slot_mutex); return 0; bus_reset: mutex_unlock(&pci_slot_mutex); - return pci_bus_reset(bridge->subordinate, 0); + return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); } /** @@ -5640,7 +5671,7 @@ int pci_bus_error_reset(struct pci_dev *bridge) */ int pci_probe_reset_bus(struct pci_bus *bus) { - return pci_bus_reset(bus, 1); + return pci_bus_reset(bus, PCI_RESET_PROBE); } EXPORT_SYMBOL_GPL(pci_probe_reset_bus); @@ -5654,7 +5685,7 @@ static int __pci_reset_bus(struct pci_bus *bus) { int rc; - rc = pci_bus_reset(bus, 1); + rc = pci_bus_reset(bus, PCI_RESET_PROBE); if (rc) return rc; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 1b3ba3116..4d482965d 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -609,19 +609,19 @@ static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) struct pci_dev_reset_methods { u16 vendor; u16 device; - int (*reset)(struct pci_dev *dev, int probe); + int (*reset)(struct pci_dev *dev, pci_reset_mode_t mode); }; struct pci_reset_fn_method { - int (*reset_fn)(struct pci_dev *, int probe); + int (*reset_fn)(struct pci_dev *, pci_reset_mode_t mode); char *name; }; extern const struct pci_reset_fn_method pci_reset_fn_methods[]; #ifdef CONFIG_PCI_QUIRKS -int pci_dev_specific_reset(struct pci_dev *dev, int probe); +int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode); #else -static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) +static inline int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode) { return -ENOTTY; } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index f4e891bd5..1259f1cdb 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1405,7 +1405,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) } if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { - rc = pcie_reset_flr(dev, 0); + rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET); if (!rc) pci_info(dev, "has been reset\n"); else diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index ceec67342..5dccf14c8 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3693,7 +3693,7 @@ DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, * reset a single function if other methods (e.g. FLR, PM D0->D3) are * not available. */ -static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) +static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, pci_reset_mode_t mode) { /* * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf @@ -3703,7 +3703,7 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) * Thus we must call pcie_flr() directly without first checking if it is * supported. */ - if (!probe) + if (mode == PCI_RESET_DO_RESET) pcie_flr(dev); return 0; } @@ -3715,13 +3715,13 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) #define NSDE_PWR_STATE 0xd0100 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ -static int reset_ivb_igd(struct pci_dev *dev, int probe) +static int reset_ivb_igd(struct pci_dev *dev, pci_reset_mode_t mode) { void __iomem *mmio_base; unsigned long timeout; u32 val; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; mmio_base = pci_iomap(dev, 0, 0); @@ -3758,7 +3758,7 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe) } /* Device-specific reset method for Chelsio T4-based adapters */ -static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) +static int reset_chelsio_generic_dev(struct pci_dev *dev, pci_reset_mode_t mode) { u16 old_command; u16 msix_flags; @@ -3774,7 +3774,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) * If this is the "probe" phase, return 0 indicating that we can * reset this device. */ - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* @@ -3836,17 +3836,17 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) * Chapter 3: NVMe control registers * Chapter 7.3: Reset behavior */ -static int nvme_disable_and_flr(struct pci_dev *dev, int probe) +static int nvme_disable_and_flr(struct pci_dev *dev, pci_reset_mode_t mode) { void __iomem *bar; u16 cmd; u32 cfg; if (dev->class != PCI_CLASS_STORAGE_EXPRESS || - pcie_reset_flr(dev, 1) || !pci_resource_start(dev, 0)) + pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); @@ -3910,11 +3910,13 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) * device too soon after FLR. A 250ms delay after FLR has heuristically * proven to produce reliably working results for device assignment cases. */ -static int delay_250ms_after_flr(struct pci_dev *dev, int probe) +static int delay_250ms_after_flr(struct pci_dev *dev, pci_reset_mode_t mode) { - int ret = pcie_reset_flr(dev, probe); + int ret; + + ret = pcie_reset_flr(dev, mode); - if (probe) + if (ret || mode == PCI_RESET_PROBE) return ret; msleep(250); @@ -3941,16 +3943,19 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { * because when a host assigns a device to a guest VM, the host may need * to reset the device but probably doesn't have a driver for it. */ -int pci_dev_specific_reset(struct pci_dev *dev, int probe) +int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode) { const struct pci_dev_reset_methods *i; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + for (i = pci_dev_reset_methods; i->reset; i++) { if ((i->vendor == dev->vendor || i->vendor == (u16)PCI_ANY_ID) && (i->device == dev->device || i->device == (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return i->reset(dev, mode); } return -ENOTTY; diff --git a/include/linux/pci.h b/include/linux/pci.h index 9bec3c616..2a35ec1f3 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -51,6 +51,12 @@ #define PCI_RESET_METHODS_NUM 6 +typedef enum pci_reset_mode { + PCI_RESET_DO_RESET, + PCI_RESET_PROBE, + PCI_RESET_MODE_MAX, +} pci_reset_mode_t; + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -1222,7 +1228,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); void pcie_print_link_status(struct pci_dev *dev); -int pcie_reset_flr(struct pci_dev *dev, int probe); +int pcie_reset_flr(struct pci_dev *dev, pci_reset_mode_t mode); int pcie_flr(struct pci_dev *dev); bool pci_reset_supported(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index b482e42d7..9e8da46e7 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -44,7 +44,7 @@ struct hotplug_slot_ops { int (*get_attention_status) (struct hotplug_slot *slot, u8 *value); int (*get_latch_status) (struct hotplug_slot *slot, u8 *value); int (*get_adapter_status) (struct hotplug_slot *slot, u8 *value); - int (*reset_slot) (struct hotplug_slot *slot, int probe); + int (*reset_slot) (struct hotplug_slot *slot, pci_reset_mode_t mode); }; /**