From patchwork Fri May 28 14:16:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 12287139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B3F8C4708C for ; Fri, 28 May 2021 14:17:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D5AC613B6 for ; Fri, 28 May 2021 14:17:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235854AbhE1OSi (ORCPT ); Fri, 28 May 2021 10:18:38 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:30828 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235690AbhE1OSh (ORCPT ); Fri, 28 May 2021 10:18:37 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14SE8SMl001078; Fri, 28 May 2021 16:16:53 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=Y7cT7lR60/u2v1bJVpqCfbs2Y7uM07+3yB1me2zWmVI=; b=fBYBqhUOgdLJ+K4TgFlh8h2q/aMiq8Wy0HBr+edSwp36H0jEZNjkUMFByjOw0DfTqwfZ jT1Ylz3GMgbb+GZ34ZJMcUHj6n8996s4tCy78IQnAXI9nZV1wS5ubOnI82LrKp5utvjH 65guM6ucEAxIpuTT974pCMSpwGFzBzwxirmTrn/Pjn1w8D9ttPrH2mIwrd2WdJIrNfca NsTAlc5Nk/xG4L0oXyRaLaFVvmcBJMYgX0lgApQFoInyTlufrvX+ags/AoKlIE6UgV1v oV9dYDBWyuJkTolsEn93PGYnTh+1FeJFaSWrBNS2ZWd8/D9Yft8BcWCcndbO4SaOX7n4 xQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 38u03c0mjm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 May 2021 16:16:53 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 70AE8100034; Fri, 28 May 2021 16:16:52 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 619A2231DC0; Fri, 28 May 2021 16:16:52 +0200 (CEST) Received: from localhost (10.75.127.47) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 28 May 2021 16:16:52 +0200 From: To: Mark Brown , Miquel Raynal , Vignesh Raghavendra , Boris Brezillon , , Alexandre Torgue , , , , , Pratyush Yadav CC: , Subject: [PATCH v4 1/3] mtd: spinand: Add spinand_init_flash() helper Date: Fri, 28 May 2021 16:16:37 +0200 Message-ID: <20210528141639.3194-2-patrice.chotard@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210528141639.3194-1-patrice.chotard@foss.st.com> References: <20210528141639.3194-1-patrice.chotard@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-05-28_05:2021-05-27,2021-05-28 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Patrice Chotard Add spinand_init_flash() helper which implements all needed init for future SPI-NAND resume ops. Signed-off-by: Patrice Chotard --- drivers/mtd/nand/spi/core.c | 66 +++++++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 25 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 17f63f95f4a2..1f39a38fbf69 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1074,12 +1074,51 @@ static int spinand_detect(struct spinand_device *spinand) return 0; } +static int spinand_init_flash(struct spinand_device *spinand) +{ + struct device *dev = &spinand->spimem->spi->dev; + struct nand_device *nand = spinand_to_nand(spinand); + int ret, i; + + ret = spinand_init_quad_enable(spinand); + if (ret) + return ret; + + ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); + if (ret) + return ret; + + ret = spinand_manufacturer_init(spinand); + if (ret) { + dev_err(dev, + "Failed to initialize the SPI NAND chip (err = %d)\n", + ret); + return ret; + } + + /* After power up, all blocks are locked, so unlock them here. */ + for (i = 0; i < nand->memorg.ntargets; i++) { + ret = spinand_select_target(spinand, i); + if (ret) + break; + + ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED); + if (ret) + break; + } + + if (ret) + spinand_manufacturer_cleanup(spinand); + + return ret; +} + static int spinand_init(struct spinand_device *spinand) { struct device *dev = &spinand->spimem->spi->dev; struct mtd_info *mtd = spinand_to_mtd(spinand); struct nand_device *nand = mtd_to_nanddev(mtd); - int ret, i; + int ret; /* * We need a scratch buffer because the spi_mem interface requires that @@ -1112,22 +1151,10 @@ static int spinand_init(struct spinand_device *spinand) if (ret) goto err_free_bufs; - ret = spinand_init_quad_enable(spinand); + ret = spinand_init_flash(spinand); if (ret) goto err_free_bufs; - ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); - if (ret) - goto err_free_bufs; - - ret = spinand_manufacturer_init(spinand); - if (ret) { - dev_err(dev, - "Failed to initialize the SPI NAND chip (err = %d)\n", - ret); - goto err_free_bufs; - } - ret = spinand_create_dirmaps(spinand); if (ret) { dev_err(dev, @@ -1136,17 +1163,6 @@ static int spinand_init(struct spinand_device *spinand) goto err_manuf_cleanup; } - /* After power up, all blocks are locked, so unlock them here. */ - for (i = 0; i < nand->memorg.ntargets; i++) { - ret = spinand_select_target(spinand, i); - if (ret) - goto err_manuf_cleanup; - - ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED); - if (ret) - goto err_manuf_cleanup; - } - ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); if (ret) goto err_manuf_cleanup; From patchwork Fri May 28 14:16:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 12287141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1DB6C2B9F7 for ; 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Fri, 28 May 2021 16:16:53 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 493A010002A; Fri, 28 May 2021 16:16:53 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 39FB8231DC0; Fri, 28 May 2021 16:16:53 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 28 May 2021 16:16:52 +0200 From: To: Mark Brown , Miquel Raynal , Vignesh Raghavendra , Boris Brezillon , , Alexandre Torgue , , , , , Pratyush Yadav CC: , Subject: [PATCH v4 2/3] mtd: spinand: add spinand_read_cfg() helper Date: Fri, 28 May 2021 16:16:38 +0200 Message-ID: <20210528141639.3194-3-patrice.chotard@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210528141639.3194-1-patrice.chotard@foss.st.com> References: <20210528141639.3194-1-patrice.chotard@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-05-28_05:2021-05-27,2021-05-28 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Patrice Chotard Put REG_CFG reading code in spinand_read_cfg(). This function will be needed by the future SPI-NAND resume ops. Signed-off-by: Patrice Chotard --- Changes in v4: - None drivers/mtd/nand/spi/core.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 1f39a38fbf69..58945f0ae839 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -138,20 +138,13 @@ int spinand_select_target(struct spinand_device *spinand, unsigned int target) return 0; } -static int spinand_init_cfg_cache(struct spinand_device *spinand) +static int spinand_read_cfg(struct spinand_device *spinand) { struct nand_device *nand = spinand_to_nand(spinand); - struct device *dev = &spinand->spimem->spi->dev; + unsigned int target; int ret; - spinand->cfg_cache = devm_kcalloc(dev, - nand->memorg.ntargets, - sizeof(*spinand->cfg_cache), - GFP_KERNEL); - if (!spinand->cfg_cache) - return -ENOMEM; - for (target = 0; target < nand->memorg.ntargets; target++) { ret = spinand_select_target(spinand, target); if (ret) @@ -170,6 +163,21 @@ static int spinand_init_cfg_cache(struct spinand_device *spinand) return 0; } +static int spinand_init_cfg_cache(struct spinand_device *spinand) +{ + struct nand_device *nand = spinand_to_nand(spinand); + struct device *dev = &spinand->spimem->spi->dev; + + spinand->cfg_cache = devm_kcalloc(dev, + nand->memorg.ntargets, + sizeof(*spinand->cfg_cache), + GFP_KERNEL); + if (!spinand->cfg_cache) + return -ENOMEM; + + return spinand_read_cfg(spinand); +} + static int spinand_init_quad_enable(struct spinand_device *spinand) { bool enable = false; From patchwork Fri May 28 14:16:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 12287143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0ABF9C47087 for ; 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Fri, 28 May 2021 16:16:54 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D15BC100034; Fri, 28 May 2021 16:16:53 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C0EE4231DC0; Fri, 28 May 2021 16:16:53 +0200 (CEST) Received: from localhost (10.75.127.46) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 28 May 2021 16:16:53 +0200 From: To: Mark Brown , Miquel Raynal , Vignesh Raghavendra , Boris Brezillon , , Alexandre Torgue , , , , , Pratyush Yadav CC: , Subject: [PATCH v4 3/3] mtd: spinand: add SPI-NAND MTD resume handler Date: Fri, 28 May 2021 16:16:39 +0200 Message-ID: <20210528141639.3194-4-patrice.chotard@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210528141639.3194-1-patrice.chotard@foss.st.com> References: <20210528141639.3194-1-patrice.chotard@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG3NODE1.st.com (10.75.127.7) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-05-28_05:2021-05-27,2021-05-28 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Patrice Chotard After power up, all SPI NAND's blocks are locked. Only read operations are allowed, write and erase operations are forbidden. The SPI NAND framework unlocks all the blocks during its initialization. During a standby low power, the memory is powered down, losing its configuration. During the resume, the QSPI driver state is restored but the SPI NAND framework does not reconfigured the memory. This patch adds SPI-NAND MTD PM handlers for resume ops. SPI NAND resume op re-initializes SPI NAND flash to its probed state. Signed-off-by: Christophe Kerello Signed-off-by: Patrice Chotard --- Changes in v4: - Call spinand_init_flash() helper in spinand_mtd_resume() Changes in v3: - Add spinand_read_cfg() call to repopulate cache Changes in v2: - Add helper spinand_block_unlock(). - Add spinand_ecc_enable() call. - Remove some dev_err(). - Fix commit's title and message. drivers/mtd/nand/spi/core.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 58945f0ae839..e108e6176f64 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1121,6 +1121,26 @@ static int spinand_init_flash(struct spinand_device *spinand) return ret; } +static void spinand_mtd_resume(struct mtd_info *mtd) +{ + struct spinand_device *spinand = mtd_to_spinand(mtd); + int ret; + + ret = spinand_reset_op(spinand); + if (ret) + return; + + ret = spinand_read_cfg(spinand); + if (ret) + return; + + ret = spinand_init_flash(spinand); + if (ret) + return; + + spinand_ecc_enable(spinand, false); +} + static int spinand_init(struct spinand_device *spinand) { struct device *dev = &spinand->spimem->spi->dev; @@ -1191,6 +1211,7 @@ static int spinand_init(struct spinand_device *spinand) mtd->_block_isreserved = spinand_mtd_block_isreserved; mtd->_erase = spinand_mtd_erase; mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; + mtd->_resume = spinand_mtd_resume; if (nand->ecc.engine) { ret = mtd_ooblayout_count_freebytes(mtd);