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mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.onmicrosoft.com; s=selector2-citrix-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GJvcxRwg22ywwmHcBxf934ac3uryD0pmSSRdtpvFX8U=; b=f5WRMDZSbDPh7hqA2tz1KmBVpBEO3Kf/o/d9srbj8eeX3loE7hg53UwXrkxGr0xAhu+4d8+kawQRrSXiNWFazcelrE5vcJ7tYEa2IYkf9XO9cIq6reQ97rCqFXT2cmH+ViGyoAanFDbjj+5swEmF23kedbRWZOP506L6jreizxk= From: Roger Pau Monne To: CC: Roger Pau Monne , Jan Beulich , Andrew Cooper , Wei Liu , Jun Nakajima , Kevin Tian , George Dunlap Subject: [PATCH 2/3] x86/mtrr: move epte_get_entry_emt to p2m-ept.c Date: Fri, 28 May 2021 19:39:34 +0200 Message-ID: <20210528173935.29919-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210528173935.29919-1-roger.pau@citrix.com> References: <20210528173935.29919-1-roger.pau@citrix.com> X-ClientProxiedBy: MR2P264CA0129.FRAP264.PROD.OUTLOOK.COM (2603:10a6:500:30::21) To DS7PR03MB5608.namprd03.prod.outlook.com (2603:10b6:5:2c9::18) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3c37482d-435b-4952-7e5d-08d921ff9acb X-MS-TrafficTypeDiagnostic: DM4PR03MB5966: X-LD-Processed: 335836de-42ef-43a2-b145-348c2ee9ca5b,ExtAddr X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?q?W+mbSgC0HgHXI6fVMAZ3IQDJ4atO9P?= =?utf-8?q?4lsCzQcemLnaMXG3Zddpdv85r7mFGUfbnhXUMyeiP0RGn1wh+eP/0U7M4ATD0OqAq?= =?utf-8?q?IzaeTGrR4+MBjksQY9iUMLQwl3YBzL1gA9kE4UPhl75iYzWHZ3A4BzsiCHMb0zhhN?= =?utf-8?q?yp9xvIqOgicQJdWe/OF80NCkf67qNBQHx2e1D7rDWONoZKIpJaQIwJ+pakna1fsd8?= =?utf-8?q?B8gSly5Rf90R27jTN69yus4k+uDyf5hFnL463JAGKdHRgOgID2jwFLP0tchGRq5Bn?= =?utf-8?q?9J4HNVM57iRxrazZRlMHKFjiQOV6JmLdLfX5mTgTapF3ygw0O531BIRSriV2q6IdA?= =?utf-8?q?OvX2GavmAENHIKinUcOZKjHBwMCqRxuKroEoha2qHEpMx1UOxcnYjGjMv4QzJYk0t?= =?utf-8?q?mOdanGpAYy2K8kxyza+zn7BdLTYgYxwe0JHA7QaHnY35F/GfOMMNqR7Dv1jXcPWnh?= =?utf-8?q?dROuckn3uVB/DnFPeo8ChRs5fKShbaB4l/AENoSH2hrq7WZTQ9sI4WqdU/PBCEgOw?= =?utf-8?q?Y8d7+0t+8nfp4v/PIprsIcv2uajI50/4J4GUhMS0GP93d0/5NRd6wcvgpkcJKg9Pv?= =?utf-8?q?CLfu7s/PK55HWKajVX9l7miGKC99E8CxRHyVrANrQlNwkaaEKP4hE74cyaFaVrGDb?= =?utf-8?q?dr2FWOV5EZvU29A8vKou4a179ebh3Wr3bG4bEZw0Bu018WAtdM6XRVBXhfgFE1Hk3?= =?utf-8?q?oS1Zx5ZVuD1H0d4zvWHyI35dSjI745rcS7BPmRvjzZ9XlFrtwR1cKIUtbMpfV8fcK?= =?utf-8?q?aZPYrf3lEj77e+e+SFhrHIrKfNjb4XmpAiPdBeqPFaWfu/VotjOyCiylEFlFld/4o?= =?utf-8?q?b7UTHAk/b57MUysFMoGlbQVjSMB1RqFd7LR/iYXVHEBg+5AoH/QeY14LI68i2LhQ2?= =?utf-8?q?CrZlAGtuBVP+yqARBpBdPnztCg/Rh/cZfxYjiPmQ/m8Nwpf9660jACH5gpSHslX2C?= =?utf-8?q?q63s/bueSyZZehO6zgv33hfbn6fFGVe6RzrSKotc4uo56b4nh9Nk03mWCN9gaPu7w?= =?utf-8?q?6Jm9Yc5qLsnR34pN3arAo13Bla69ek4tKyP2vQExzjmnTS0qdPoE596Qs/fj7RF5V?= =?utf-8?q?j6dmvRMmdjWksJAiU9T8v0bSHrMn/aLfbhvqgQY/z8M2kv7aq2zXW8iMEnnIV+nrv?= =?utf-8?q?0m2qTPBcYaszRE5PEvj0ZpCG4f5lmOwX6QkUxSLWbBlv9JoRIea6kl56JKKiSYmxz?= =?utf-8?q?kpt8sCsX7RFXRbiBdC5VU9nVkoYk8l7aUX2EGLJ1eFa9dZX5alb8nhd9tJPuUSoeW?= =?utf-8?q?WLWMOStaBk/ZQP?= X-MS-Exchange-CrossTenant-Network-Message-Id: 3c37482d-435b-4952-7e5d-08d921ff9acb X-MS-Exchange-CrossTenant-AuthSource: DS7PR03MB5608.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 17:39:54.8444 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iiGorM+JTj0lcezfzXSFfpp9FQvYBQOtEOMU32kLtWGxw0Z/FqNT1CP99ZxVDAWJN6Pcn/q5LqhdAnwEwc+IgQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR03MB5966 X-OriginatorOrg: citrix.com This is an EPT specific function, so it shouldn't live in the generic mtrr file. Such movement is also needed for future work that will require passing a p2m_type_t parameter to epte_get_entry_emt, and making that type visible to the mtrr users is cumbersome and unneeded. Moving epte_get_entry_emt out of mtrr.c requires making the helper to get the MTRR type of an address from the mtrr state public. While there rename the function to start with the mtrr prefix, like other mtrr related functions. While there fix some of the types of the function parameters. No functional change intended. Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich Reviewed-by: Kevin Tian --- xen/arch/x86/hvm/mtrr.c | 107 +--------------------------- xen/arch/x86/hvm/vmx/vmx.c | 4 +- xen/arch/x86/mm/p2m-ept.c | 114 ++++++++++++++++++++++++++++-- xen/include/asm-x86/hvm/vmx/vmx.h | 2 + xen/include/asm-x86/mtrr.h | 5 +- 5 files changed, 118 insertions(+), 114 deletions(-) diff --git a/xen/arch/x86/hvm/mtrr.c b/xen/arch/x86/hvm/mtrr.c index 82ded1635c..4a9f3177ed 100644 --- a/xen/arch/x86/hvm/mtrr.c +++ b/xen/arch/x86/hvm/mtrr.c @@ -194,8 +194,7 @@ void hvm_vcpu_cacheattr_destroy(struct vcpu *v) * May return a negative value when order > 0, indicating to the caller * that the respective mapping needs splitting. */ -static int get_mtrr_type(const struct mtrr_state *m, - paddr_t pa, unsigned int order) +int mtrr_get_type(const struct mtrr_state *m, paddr_t pa, unsigned int order) { uint8_t overlap_mtrr = 0; uint8_t overlap_mtrr_pos = 0; @@ -323,7 +322,7 @@ static uint8_t effective_mm_type(struct mtrr_state *m, * just use it */ if ( gmtrr_mtype == NO_HARDCODE_MEM_TYPE ) - mtrr_mtype = get_mtrr_type(m, gpa, 0); + mtrr_mtype = mtrr_get_type(m, gpa, 0); else mtrr_mtype = gmtrr_mtype; @@ -350,7 +349,7 @@ uint32_t get_pat_flags(struct vcpu *v, guest_eff_mm_type = effective_mm_type(g, pat, gpaddr, gl1e_flags, gmtrr_mtype); /* 2. Get the memory type of host physical address, with MTRR */ - shadow_mtrr_type = get_mtrr_type(&mtrr_state, spaddr, 0); + shadow_mtrr_type = mtrr_get_type(&mtrr_state, spaddr, 0); /* 3. Find the memory type in PAT, with host MTRR memory type * and guest effective memory type. @@ -789,106 +788,6 @@ void memory_type_changed(struct domain *d) } } -int epte_get_entry_emt(struct domain *d, unsigned long gfn, mfn_t mfn, - unsigned int order, uint8_t *ipat, bool_t direct_mmio) -{ - int gmtrr_mtype, hmtrr_mtype; - struct vcpu *v = current; - unsigned long i; - - *ipat = 0; - - if ( v->domain != d ) - v = d->vcpu ? d->vcpu[0] : NULL; - - /* Mask, not add, for order so it works with INVALID_MFN on unmapping */ - if ( rangeset_overlaps_range(mmio_ro_ranges, mfn_x(mfn), - mfn_x(mfn) | ((1UL << order) - 1)) ) - { - if ( !order || rangeset_contains_range(mmio_ro_ranges, mfn_x(mfn), - mfn_x(mfn) | ((1UL << order) - 1)) ) - { - *ipat = 1; - return MTRR_TYPE_UNCACHABLE; - } - /* Force invalid memory type so resolve_misconfig() will split it */ - return -1; - } - - if ( !mfn_valid(mfn) ) - { - *ipat = 1; - return MTRR_TYPE_UNCACHABLE; - } - - if ( !direct_mmio && !is_iommu_enabled(d) && !cache_flush_permitted(d) ) - { - *ipat = 1; - return MTRR_TYPE_WRBACK; - } - - for ( i = 0; i < (1ul << order); i++ ) - { - if ( is_special_page(mfn_to_page(mfn_add(mfn, i))) ) - { - if ( order ) - return -1; - *ipat = 1; - return MTRR_TYPE_WRBACK; - } - } - - if ( direct_mmio ) - return MTRR_TYPE_UNCACHABLE; - - gmtrr_mtype = hvm_get_mem_pinned_cacheattr(d, _gfn(gfn), order); - if ( gmtrr_mtype >= 0 ) - { - *ipat = 1; - return gmtrr_mtype != PAT_TYPE_UC_MINUS ? gmtrr_mtype - : MTRR_TYPE_UNCACHABLE; - } - if ( gmtrr_mtype == -EADDRNOTAVAIL ) - return -1; - - gmtrr_mtype = v ? get_mtrr_type(&v->arch.hvm.mtrr, gfn << PAGE_SHIFT, order) - : MTRR_TYPE_WRBACK; - hmtrr_mtype = get_mtrr_type(&mtrr_state, mfn_x(mfn) << PAGE_SHIFT, order); - if ( gmtrr_mtype < 0 || hmtrr_mtype < 0 ) - return -1; - - /* If both types match we're fine. */ - if ( likely(gmtrr_mtype == hmtrr_mtype) ) - return hmtrr_mtype; - - /* If either type is UC, we have to go with that one. */ - if ( gmtrr_mtype == MTRR_TYPE_UNCACHABLE || - hmtrr_mtype == MTRR_TYPE_UNCACHABLE ) - return MTRR_TYPE_UNCACHABLE; - - /* If either type is WB, we have to go with the other one. */ - if ( gmtrr_mtype == MTRR_TYPE_WRBACK ) - return hmtrr_mtype; - if ( hmtrr_mtype == MTRR_TYPE_WRBACK ) - return gmtrr_mtype; - - /* - * At this point we have disagreeing WC, WT, or WP types. The only - * combination that can be cleanly resolved is WT:WP. The ones involving - * WC need to be converted to UC, both due to the memory ordering - * differences and because WC disallows reads to be cached (WT and WP - * permit this), while WT and WP require writes to go straight to memory - * (WC can buffer them). - */ - if ( (gmtrr_mtype == MTRR_TYPE_WRTHROUGH && - hmtrr_mtype == MTRR_TYPE_WRPROT) || - (gmtrr_mtype == MTRR_TYPE_WRPROT && - hmtrr_mtype == MTRR_TYPE_WRTHROUGH) ) - return MTRR_TYPE_WRPROT; - - return MTRR_TYPE_UNCACHABLE; -} - /* * Local variables: * mode: C diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 7e3e67fdc3..0d4b47681b 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -417,12 +417,12 @@ static int vmx_domain_initialise(struct domain *d) static void domain_creation_finished(struct domain *d) { gfn_t gfn = gaddr_to_gfn(APIC_DEFAULT_PHYS_BASE); - uint8_t ipat; + bool ipat; if ( !has_vlapic(d) || mfn_eq(apic_access_mfn, INVALID_MFN) ) return; - ASSERT(epte_get_entry_emt(d, gfn_x(gfn), apic_access_mfn, 0, &ipat, + ASSERT(epte_get_entry_emt(d, gfn, apic_access_mfn, 0, &ipat, true) == MTRR_TYPE_WRBACK); ASSERT(ipat); diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index a3beaf91e2..f1d1d07e92 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -485,6 +486,108 @@ static int ept_invalidate_emt_range(struct p2m_domain *p2m, return rc; } +int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int order, bool *ipat, bool direct_mmio) +{ + int gmtrr_mtype, hmtrr_mtype; + struct vcpu *v = current; + unsigned long i; + + *ipat = false; + + if ( v->domain != d ) + v = d->vcpu ? d->vcpu[0] : NULL; + + /* Mask, not add, for order so it works with INVALID_MFN on unmapping */ + if ( rangeset_overlaps_range(mmio_ro_ranges, mfn_x(mfn), + mfn_x(mfn) | ((1UL << order) - 1)) ) + { + if ( !order || rangeset_contains_range(mmio_ro_ranges, mfn_x(mfn), + mfn_x(mfn) | ((1UL << order) - 1)) ) + { + *ipat = true; + return MTRR_TYPE_UNCACHABLE; + } + /* Force invalid memory type so resolve_misconfig() will split it */ + return -1; + } + + if ( !mfn_valid(mfn) ) + { + *ipat = true; + return MTRR_TYPE_UNCACHABLE; + } + + if ( !direct_mmio && !is_iommu_enabled(d) && !cache_flush_permitted(d) ) + { + *ipat = true; + return MTRR_TYPE_WRBACK; + } + + for ( i = 0; i < (1ul << order); i++ ) + { + if ( is_special_page(mfn_to_page(mfn_add(mfn, i))) ) + { + if ( order ) + return -1; + *ipat = true; + return MTRR_TYPE_WRBACK; + } + } + + if ( direct_mmio ) + return MTRR_TYPE_UNCACHABLE; + + gmtrr_mtype = hvm_get_mem_pinned_cacheattr(d, gfn, order); + if ( gmtrr_mtype >= 0 ) + { + *ipat = true; + return gmtrr_mtype != PAT_TYPE_UC_MINUS ? gmtrr_mtype + : MTRR_TYPE_UNCACHABLE; + } + if ( gmtrr_mtype == -EADDRNOTAVAIL ) + return -1; + + gmtrr_mtype = v ? mtrr_get_type(&v->arch.hvm.mtrr, + gfn_x(gfn) << PAGE_SHIFT, order) + : MTRR_TYPE_WRBACK; + hmtrr_mtype = mtrr_get_type(&mtrr_state, mfn_x(mfn) << PAGE_SHIFT, + order); + if ( gmtrr_mtype < 0 || hmtrr_mtype < 0 ) + return -1; + + /* If both types match we're fine. */ + if ( likely(gmtrr_mtype == hmtrr_mtype) ) + return hmtrr_mtype; + + /* If either type is UC, we have to go with that one. */ + if ( gmtrr_mtype == MTRR_TYPE_UNCACHABLE || + hmtrr_mtype == MTRR_TYPE_UNCACHABLE ) + return MTRR_TYPE_UNCACHABLE; + + /* If either type is WB, we have to go with the other one. */ + if ( gmtrr_mtype == MTRR_TYPE_WRBACK ) + return hmtrr_mtype; + if ( hmtrr_mtype == MTRR_TYPE_WRBACK ) + return gmtrr_mtype; + + /* + * At this point we have disagreeing WC, WT, or WP types. The only + * combination that can be cleanly resolved is WT:WP. The ones involving + * WC need to be converted to UC, both due to the memory ordering + * differences and because WC disallows reads to be cached (WT and WP + * permit this), while WT and WP require writes to go straight to memory + * (WC can buffer them). + */ + if ( (gmtrr_mtype == MTRR_TYPE_WRTHROUGH && + hmtrr_mtype == MTRR_TYPE_WRPROT) || + (gmtrr_mtype == MTRR_TYPE_WRPROT && + hmtrr_mtype == MTRR_TYPE_WRTHROUGH) ) + return MTRR_TYPE_WRPROT; + + return MTRR_TYPE_UNCACHABLE; +} + /* * Resolve deliberately mis-configured (EMT field set to an invalid value) * entries in the page table hierarchy for the given GFN: @@ -519,7 +622,7 @@ static int resolve_misconfig(struct p2m_domain *p2m, unsigned long gfn) if ( level == 0 || is_epte_superpage(&e) ) { - uint8_t ipat = 0; + bool ipat; if ( e.emt != MTRR_NUM_TYPES ) break; @@ -535,7 +638,7 @@ static int resolve_misconfig(struct p2m_domain *p2m, unsigned long gfn) e.emt = 0; if ( !is_epte_valid(&e) || !is_epte_present(&e) ) continue; - e.emt = epte_get_entry_emt(p2m->domain, gfn + i, + e.emt = epte_get_entry_emt(p2m->domain, _gfn(gfn + i), _mfn(e.mfn), 0, &ipat, e.sa_p2mt == p2m_mmio_direct); e.ipat = ipat; @@ -553,7 +656,8 @@ static int resolve_misconfig(struct p2m_domain *p2m, unsigned long gfn) } else { - int emt = epte_get_entry_emt(p2m->domain, gfn, _mfn(e.mfn), + int emt = epte_get_entry_emt(p2m->domain, _gfn(gfn), + _mfn(e.mfn), level * EPT_TABLE_ORDER, &ipat, e.sa_p2mt == p2m_mmio_direct); bool_t recalc = e.recalc; @@ -788,8 +892,8 @@ ept_set_entry(struct p2m_domain *p2m, gfn_t gfn_, mfn_t mfn, if ( mfn_valid(mfn) || p2m_allows_invalid_mfn(p2mt) ) { - uint8_t ipat = 0; - int emt = epte_get_entry_emt(p2m->domain, gfn, mfn, + bool ipat; + int emt = epte_get_entry_emt(p2m->domain, _gfn(gfn), mfn, i * EPT_TABLE_ORDER, &ipat, p2mt == p2m_mmio_direct); diff --git a/xen/include/asm-x86/hvm/vmx/vmx.h b/xen/include/asm-x86/hvm/vmx/vmx.h index 534e9fc221..f668ee1f09 100644 --- a/xen/include/asm-x86/hvm/vmx/vmx.h +++ b/xen/include/asm-x86/hvm/vmx/vmx.h @@ -599,6 +599,8 @@ void ept_p2m_uninit(struct p2m_domain *p2m); void ept_walk_table(struct domain *d, unsigned long gfn); bool_t ept_handle_misconfig(uint64_t gpa); +int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int order, bool *ipat, bool direct_mmio); void setup_ept_dump(void); void p2m_init_altp2m_ept(struct domain *d, unsigned int i); /* Locate an alternate p2m by its EPTP */ diff --git a/xen/include/asm-x86/mtrr.h b/xen/include/asm-x86/mtrr.h index 24e5de5c22..e0fd1005ce 100644 --- a/xen/include/asm-x86/mtrr.h +++ b/xen/include/asm-x86/mtrr.h @@ -72,12 +72,11 @@ extern int mtrr_add_page(unsigned long base, unsigned long size, unsigned int type, char increment); extern int mtrr_del(int reg, unsigned long base, unsigned long size); extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); +extern int mtrr_get_type(const struct mtrr_state *m, paddr_t pa, + unsigned int order); extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); extern u32 get_pat_flags(struct vcpu *v, u32 gl1e_flags, paddr_t gpaddr, paddr_t spaddr, uint8_t gmtrr_mtype); -extern int epte_get_entry_emt(struct domain *, unsigned long gfn, mfn_t mfn, - unsigned int order, uint8_t *ipat, - bool_t direct_mmio); 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mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.onmicrosoft.com; s=selector2-citrix-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AtL+Hp/29nuKWkROvVXgdUUpYBKLh+7LK1UvsLfBAnw=; b=UJFZGiApEH1vy8jgKaaJZ+4rdKdmjxOjojLnKlEZMMTN8In71yspd7/+zwVhtLdfcZ2azEu+czUq0guRWd/JGC8CdmzQhX6y0/3mzhpf0Ap2oCs/WbuxCTGt8OGTxxxZir6bPFORz5sA222biacpCqU0FzmcE38H+i0VMVn2Pas= From: Roger Pau Monne To: CC: Roger Pau Monne , Jun Nakajima , Kevin Tian , Jan Beulich , Andrew Cooper , Wei Liu , George Dunlap Subject: [PATCH 3/3] x86/ept: force WB cache attributes for grant and foreign maps Date: Fri, 28 May 2021 19:39:35 +0200 Message-ID: <20210528173935.29919-4-roger.pau@citrix.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210528173935.29919-1-roger.pau@citrix.com> References: <20210528173935.29919-1-roger.pau@citrix.com> X-ClientProxiedBy: MRXP264CA0003.FRAP264.PROD.OUTLOOK.COM (2603:10a6:500:15::15) To DS7PR03MB5608.namprd03.prod.outlook.com (2603:10b6:5:2c9::18) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a4af593d-a375-4a60-cea1-08d921ff9e03 X-MS-TrafficTypeDiagnostic: DM4PR03MB5966: X-LD-Processed: 335836de-42ef-43a2-b145-348c2ee9ca5b,ExtAddr X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?q?ES1BvX3yf++xRhU7LAJp6/1osyTRTH?= =?utf-8?q?vzAtNfppSneGlw0VXTZTcmI78GhXhFT4pMU9ifS8fRZf6MxC/SCTUQfChrjPBIwyI?= =?utf-8?q?rnmKkIPu0l9uMisgH0qzcQcncPxFU3nSBRcJnjZLpaI2d71w+OJdWVO+f/nKzTGx1?= =?utf-8?q?MzGfwLr1VYWupRWfdZUekOZCe+/zDxJZ5EYP6YhcqTxuSUuimlX/zFczjBPfka9j+?= =?utf-8?q?GNeMAsBtLRTJumrw1E9jjfr3762nxyDKvJKrnZIhVpBT50q94VL72SBmXU0xHrzc0?= =?utf-8?q?DCs8UsOn+QDjwNSg59SVwdC7dI58lxjBZBYjD4N/30myr4EAjSlnE3MuU7S4RJkLX?= =?utf-8?q?x5/sIREPN8yqP3d8/1N25u0pI8CPZPaBwehqecOHyDTADp2wUYDAosdt/ODFnn5Hx?= =?utf-8?q?GkP41PwtUkUR2e1NHaND/BnJbc++b/m9PCLQOrfCFAN3ELCVRlAH7B8djLHM5E+Bs?= =?utf-8?q?Cq76U2ZYzHGgtLq1/lwGHgmIJsL5znQxK9Trrf4WIHw/cXLNKYnSWUMmcTZB3PJuf?= =?utf-8?q?AqWasPQNA6cQfApxLB2zAedONBlsu75NNX9HJlyRihk/uyzw9LlaU9DPNt3MPFf/h?= =?utf-8?q?o0JZ5XSODlI6nAtV2BIxVVX16VMKC/slPrRcwf5EyOJvK0RMxT6SbilLswI3Lq1x4?= =?utf-8?q?GGLhO3+n3etVm3ia6tcIT4+Qpy85Lts1Xfax2jEkCFVMqHwBdi0QBSv3/zRVeVDm4?= =?utf-8?q?Yhn9bTcKiJ1yYA8JEuvxteLWUfrmem61j9RSGq3JXGkC2lb1yPj6fU4d139tN0+xM?= =?utf-8?q?9F1oLD+g43Nb8a/q52ayrj3ny9ypk6dEBAYRiQtwkxNIbru8MRP+/31HsHxBZeXa0?= =?utf-8?q?Y8HlSQZqrMH/5UEczXjfI03UTR9C5qGebLhFd5FjAd416m/LyhPEDXmyR8dptqR0x?= =?utf-8?q?G67sQWdac3JMzrIlfnJWZyHsTaFA9Zm8aipI9lhtAt/4d9XICm91/Flb1olgX5jnF?= =?utf-8?q?vGgol4Vp0I3TQBbRz7dWvw05Zlt6h8xbOx1CoMxGx24qoUfYjfat0SjZoKyQu8pG9?= =?utf-8?q?a5MwnSbKqTnOvaV01rz7+P+isJaQgjNemxie4aFB50XDtCFTtG0BN6UJsMsG/WstI?= =?utf-8?q?XUPHF0eBanFXjMN++lZcYf4E0qzzkxI3ogzJ3ZgFJYnJDiXBLYe5i1wRXyFDB495b?= =?utf-8?q?G8uY1nI3QV7UD5ydSL+jn90yzW7G3JIcuUAfRxGbT51qn9bZpmKCvXhQSdpCEJcdA?= =?utf-8?q?wpdq2jLxAWZyi0NmEnUSmT6Mrocjsr9WMiKjcSLPRf9k7Hxs1otxM2PBqjylduMC5?= =?utf-8?q?ldK23bpPoYvn4e?= X-MS-Exchange-CrossTenant-Network-Message-Id: a4af593d-a375-4a60-cea1-08d921ff9e03 X-MS-Exchange-CrossTenant-AuthSource: DS7PR03MB5608.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 17:40:00.3203 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TdcYqbP2mgA9Fh5hUhfZm4Tx+YmL8FNLGFav7GYHvq1HX0EN9wCvr99EbgxiEdgDEz3eAMm6Zh/ETzQEM0XNrA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR03MB5966 X-OriginatorOrg: citrix.com Force WB type for grants and foreign pages. Those are usually mapped over unpopulated physical ranges in the p2m, and those ranges would usually be UC in the MTRR state, which is unlikely to be the correct cache attribute. It's also cumbersome (or even impossible) for the guest to be setting the MTRR type for all those mappings as WB, as MTRR ranges are finite. Note that on AMD we cannot force a cache attribute because of the lack of ignore PAT equivalent, so the behavior here slightly diverges between AMD and Intel (or EPT vs NPT/shadow). Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich Reviewed-by: Kevin Tian --- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/mm/p2m-ept.c | 35 ++++++++++++++++++++++++++----- xen/include/asm-x86/hvm/vmx/vmx.h | 2 +- 3 files changed, 32 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 0d4b47681b..e09b7e3af9 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -423,7 +423,7 @@ static void domain_creation_finished(struct domain *d) return; ASSERT(epte_get_entry_emt(d, gfn, apic_access_mfn, 0, &ipat, - true) == MTRR_TYPE_WRBACK); + p2m_mmio_direct) == MTRR_TYPE_WRBACK); ASSERT(ipat); if ( set_mmio_p2m_entry(d, gfn, apic_access_mfn, PAGE_ORDER_4K) ) diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index f1d1d07e92..59c0325473 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -487,11 +487,12 @@ static int ept_invalidate_emt_range(struct p2m_domain *p2m, } int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn_t mfn, - unsigned int order, bool *ipat, bool direct_mmio) + unsigned int order, bool *ipat, p2m_type_t type) { int gmtrr_mtype, hmtrr_mtype; struct vcpu *v = current; unsigned long i; + bool direct_mmio = type == p2m_mmio_direct; *ipat = false; @@ -535,9 +536,33 @@ int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn_t mfn, } } - if ( direct_mmio ) + switch ( type ) + { + case p2m_mmio_direct: return MTRR_TYPE_UNCACHABLE; + case p2m_grant_map_ro: + case p2m_grant_map_rw: + case p2m_map_foreign: + /* + * Force WB type for grants and foreign pages. Those are usually mapped + * over unpopulated physical ranges in the p2m, and those would usually + * be UC in the MTRR state, which is unlikely to be the correct cache + * attribute. It's also cumbersome (or even impossible) for the guest + * to be setting the MTRR type for all those mappings as WB, as MTRR + * ranges are finite. + * + * Note that on AMD we cannot force a cache attribute because of the + * lack of ignore PAT equivalent, so the behavior here slightly + * diverges. See p2m_type_to_flags for the AMD attributes. + */ + *ipat = true; + return MTRR_TYPE_WRBACK; + + default: + break; + } + gmtrr_mtype = hvm_get_mem_pinned_cacheattr(d, gfn, order); if ( gmtrr_mtype >= 0 ) { @@ -640,7 +665,7 @@ static int resolve_misconfig(struct p2m_domain *p2m, unsigned long gfn) continue; e.emt = epte_get_entry_emt(p2m->domain, _gfn(gfn + i), _mfn(e.mfn), 0, &ipat, - e.sa_p2mt == p2m_mmio_direct); + e.sa_p2mt); e.ipat = ipat; nt = p2m_recalc_type(e.recalc, e.sa_p2mt, p2m, gfn + i); @@ -659,7 +684,7 @@ static int resolve_misconfig(struct p2m_domain *p2m, unsigned long gfn) int emt = epte_get_entry_emt(p2m->domain, _gfn(gfn), _mfn(e.mfn), level * EPT_TABLE_ORDER, &ipat, - e.sa_p2mt == p2m_mmio_direct); + e.sa_p2mt); bool_t recalc = e.recalc; if ( recalc && p2m_is_changeable(e.sa_p2mt) ) @@ -895,7 +920,7 @@ ept_set_entry(struct p2m_domain *p2m, gfn_t gfn_, mfn_t mfn, bool ipat; int emt = epte_get_entry_emt(p2m->domain, _gfn(gfn), mfn, i * EPT_TABLE_ORDER, &ipat, - p2mt == p2m_mmio_direct); + p2mt); if ( emt >= 0 ) new_entry.emt = emt; diff --git a/xen/include/asm-x86/hvm/vmx/vmx.h b/xen/include/asm-x86/hvm/vmx/vmx.h index f668ee1f09..0deb507490 100644 --- a/xen/include/asm-x86/hvm/vmx/vmx.h +++ b/xen/include/asm-x86/hvm/vmx/vmx.h @@ -600,7 +600,7 @@ void ept_p2m_uninit(struct p2m_domain *p2m); void ept_walk_table(struct domain *d, unsigned long gfn); bool_t ept_handle_misconfig(uint64_t gpa); int epte_get_entry_emt(struct domain *d, gfn_t gfn, mfn_t mfn, - unsigned int order, bool *ipat, bool direct_mmio); + unsigned int order, bool *ipat, p2m_type_t type); void setup_ept_dump(void); void p2m_init_altp2m_ept(struct domain *d, unsigned int i); /* Locate an alternate p2m by its EPTP */