From patchwork Sat May 29 05:02:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: William Tseng X-Patchwork-Id: 12287671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D724C47082 for ; Sat, 29 May 2021 05:03:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E0F9661248 for ; Sat, 29 May 2021 05:03:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E0F9661248 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2F1CC6E056; Sat, 29 May 2021 05:03:04 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F6356E056 for ; Sat, 29 May 2021 05:03:02 +0000 (UTC) IronPort-SDR: GypVXBNFeFW6aLXcCLwsY9ni495QO0eCaG30txNh5jYdXEjJ6ZZtcWHp+El5r5Z5AcAPpHAASd G6OkjerLM4nA== X-IronPort-AV: E=McAfee;i="6200,9189,9998"; a="201198658" X-IronPort-AV: E=Sophos;i="5.83,231,1616482800"; d="scan'208";a="201198658" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2021 22:03:01 -0700 IronPort-SDR: paB41NQYBl8Moayiw3hcVpV0pAgWRlP+GsYiwZtzsqppCxXrBcHFzEttsK5KikF1ipitxFurYx w3yMa5BVzWkg== X-IronPort-AV: E=Sophos;i="5.83,231,1616482800"; d="scan'208";a="444249350" Received: from tsengwil-desk1.itwn.intel.com (HELO gar) ([10.5.224.21]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2021 22:03:00 -0700 From: William Tseng To: intel-gfx@lists.freedesktop.org Date: Sat, 29 May 2021 13:02:55 +0800 Message-Id: <20210529050255.17405-1-william.tseng@intel.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: Reading DPRX caps in LTTPR transparent mode after LTTPR detection X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: William Tseng Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In some cases, the MAX_LANE_COUNT in the register at DCPD Address 0002h may be updated by LTTPR in non-transparent mode while reading DPRX Caps registers, e.g., the lane count is changed from 2 to 4. This may cause Link Training failure because of the updated lane count, which might not be supported by the DPRX. This change may work around the problem, which LTTPR updates the DCPD register not liseted in the table, i.e., Table 3-65, mentioned in the DP standard, Section 3.6.3, Version 2.0. "" Upon discovering its location between the DPTX and DPRX, the LTTPR replies to AUX request transactions to its DPCD address range within the LTTPR field. The LTTPR passes through all other AUX request transactions with one exception – an LTTPR shall snoop AUX request transactions to those DPCD Addresses listed in Table 3-65 and take necessary actions as specified in the table. (For complete register descriptions, see Table 2-184.) "" Cs : Khaled Almahallawy Cc : Imre Deak Cc : Tejas Upadhyay Cc : Ville Syrjälä Signed-off-by: William Tseng --- .../drm/i915/display/intel_dp_link_training.c | 44 +++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 50cae0198a3d..3658deb9da1c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -131,7 +131,6 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) static int intel_dp_init_lttpr(struct intel_dp *intel_dp) { int lttpr_count; - int i; if (!intel_dp_read_lttpr_common_caps(intel_dp)) return 0; @@ -152,27 +151,6 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp) */ intel_dp_set_lttpr_transparent_mode(intel_dp, true); - /* - * In case of unsupported number of LTTPRs or failing to switch to - * non-transparent mode fall-back to transparent link training mode, - * still taking into account any LTTPR common lane- rate/count limits. - */ - if (lttpr_count < 0) - return 0; - - if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { - drm_dbg_kms(&dp_to_i915(intel_dp)->drm, - "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); - - intel_dp_set_lttpr_transparent_mode(intel_dp, true); - intel_dp_reset_lttpr_count(intel_dp); - - return 0; - } - - for (i = 0; i < lttpr_count; i++) - intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i)); - return lttpr_count; } @@ -197,6 +175,7 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp) int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) { int lttpr_count = intel_dp_init_lttpr(intel_dp); + int i; /* The DPTX shall read the DPRX caps after LTTPR detection. */ if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { @@ -204,6 +183,27 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) return -EIO; } + /* + * In case of unsupported number of LTTPRs or failing to switch to + * non-transparent mode fall-back to transparent link training mode, + * still taking into account any LTTPR common lane- rate/count limits. + */ + if (lttpr_count <= 0) + return 0; + + if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); + + intel_dp_set_lttpr_transparent_mode(intel_dp, true); + intel_dp_reset_lttpr_count(intel_dp); + + return 0; + } + + for (i = 0; i < lttpr_count; i++) + intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i)); + return lttpr_count; } EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps);