From patchwork Sat May 29 17:09:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12287991 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CF0CC47091 for ; Sat, 29 May 2021 17:10:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB5356112F for ; Sat, 29 May 2021 17:10:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229789AbhE2RMS (ORCPT ); Sat, 29 May 2021 13:12:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229704AbhE2RMR (ORCPT ); Sat, 29 May 2021 13:12:17 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 215BDC06174A; Sat, 29 May 2021 10:10:41 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id a5so10145197lfm.0; Sat, 29 May 2021 10:10:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MpvhPzX1ymg5vSIOj/R3c0XtSN9hCFreWZQ1rMcnPsI=; b=cEF/edBeiZoX3EJ9sVxvgswrbajZc3tW0CiapswGcIFOKkVumpG8UnjFduDIad7/xi /qdTrL6u6fXfqDndW8DyNesMyQtJ0ZA7LERWemwR9W97ZJTX3Qj/k2UVRTHAzi58yihE 4ps2ulAHX/WU14f6kKnDvlFwsDiClfbTK3lw1ZDPtnIeWzaf7zRUbrUDSbnw0oWd3SLy /zpqbooQuWSMJ9zrLdJoItTHHGystEq50lgTCzZu+I4+1Gu7Mn14NOmdpKVAqSzX29iQ v1Evp4UMC1mSxqNvm6R6BqppnpS0sR3CfKV+OB6c/ghkI71ufurjoaMi/OfJDA48FK0b lloQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MpvhPzX1ymg5vSIOj/R3c0XtSN9hCFreWZQ1rMcnPsI=; b=DrDqtlixgvRoTzKs8zw2Dnulhx8HDPvd3+hVtRM003+Uo3atBGmppymDpcbTZNZWZj I5TtSI6y/BUjoqB8ECd84285YLWe7BEPN3KpBD1CWtUhciRGpAzx9OL3Olju/EEaVgzK U8XptXyKRgrnUT0ZnuwBDasUYUULD/82wLUCtK07f/M5+haUgupK0P5DtRbw3vZJlUes rWvlfZ/3JztpgSYS7ZI4IbdjO/t1A3OYzF+HHw1R5XJsUZwrHMagxS9csr70F0O11hp6 zZFKKCg53ukrB90qrIwTldzMZg+rX0gjyxJpScHjHMKliK8pN47FvtUZILVRCe6oDrxH J0Ig== X-Gm-Message-State: AOAM533W5xdmnov+8ZgC9K4l64c34lXMpfAHCnmdMfBDbJ7evvoUWYdl tjAIyPDh6n0GvgpfO0/M707BQGPK0L0= X-Google-Smtp-Source: ABdhPJy1AnCFjFJkmAbUJDv6G6Zo1zpo1Ym98T8f7DNpUaw/KUnkL21UOb5Zx81JRLHrVw+6MYAf/w== X-Received: by 2002:a19:ac45:: with SMTP id r5mr10163245lfc.449.1622308239519; Sat, 29 May 2021 10:10:39 -0700 (PDT) Received: from localhost.localdomain (46-138-84-89.dynamic.spd-mgts.ru. [46.138.84.89]) by smtp.gmail.com with ESMTPSA id h12sm901715ljh.130.2021.05.29.10.10.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 10:10:39 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 1/7] dt-bindings: thermal: Add binding for Tegra30 thermal sensor Date: Sat, 29 May 2021 20:09:49 +0300 Message-Id: <20210529170955.32574-2-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210529170955.32574-1-digetx@gmail.com> References: <20210529170955.32574-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org All NVIDIA Tegra30 SoCs have on-chip sensors which monitor temperature and voltage of the SoC. Sensors also controls CPU x2 freq throttle and emits emergency shutdown signal. TSENSOR has has two separate channels for each sensor placed in a different parts of the SoC. Add binding for the sensor hardware. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../thermal/nvidia,tegra30-tsensor.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml new file mode 100644 index 000000000000..6182090d313c --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra30-tsensor.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/nvidia,tegra30-tsensor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 Thermal Sensor + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +description: | + TSENSOR provides thermal and voltage sensors which monitor temperature + and voltage of the chip. Sensors are placed across the die to gauge the + temperature of the whole chip. The TSENSOR module: + + Generates an interrupt to SW to lower temperature via DVFS on reaching + a certain thermal/voltage threshold. + + Generates a signal to the CAR to reduce CPU frequency by half on reaching + a certain thermal/voltage threshold. + + Generates a signal to the PMC when the temperature reaches dangerously high + levels to reset the chip and sets a flag in the PMC. + + TSENSOR has two channels which monitor two different spots of the SoC. + +properties: + compatible: + const: nvidia,tegra30-tsensor + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + + "#cooling-cells": + const: 2 + + assigned-clock-parents: true + assigned-clock-rates: true + assigned-clocks: true + +required: + - compatible + - reg + - clocks + - resets + - interrupts + - "#thermal-sensor-cells" + - "#cooling-cells" + +additionalProperties: false + +examples: + - | + thermal-sensor@70014000 { + compatible = "nvidia,tegra30-tsensor"; + reg = <0x70014000 0x500>; + interrupts = <0 102 4>; + clocks = <&clk 100>; + resets = <&rst 100>; + + #thermal-sensor-cells = <1>; + #cooling-cells = <2>; + }; From patchwork Sat May 29 17:09:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12287997 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02122C4708F for ; Sat, 29 May 2021 17:10:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D37A06112F for ; Sat, 29 May 2021 17:10:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229841AbhE2RMW (ORCPT ); Sat, 29 May 2021 13:12:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229821AbhE2RMU (ORCPT ); Sat, 29 May 2021 13:12:20 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 034FFC061574; Sat, 29 May 2021 10:10:42 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id 131so9272642ljj.3; Sat, 29 May 2021 10:10:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XcXraiNoRPU0G8oGIVhPyNHE4YAr90zRs8GgZNjViE0=; b=YCaDe2bDmorvvCgvE1ShVN/7GR+xVx4dF6waLCCWikaW/lTY/xX0q8+9RzHGDih738 PrQrnKTGSlToJEDVifQew+0xNe4FcXqDSVj64BH35G8zmxtzoYyspZ1sCU6jd7XmhUIN Q3jmCcCKR/WHjMqgXdpFeGrMjDfa4TSptNAotxo4Ro1vJoYoCav+0bSPQV2Dc6fgwI82 f+ZRaoBvmb4VPdMz4SQcA+9nyGTRQYjrzPuCidyJrozEWGTnpMC1UAeWOECjVr357xlJ 3qcqEokOeJcSRLKeb3CR93wvR6yvBd7jdX6NF5zB53ch4C0F1ZXuV6rJDHIu46vg611X zlCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XcXraiNoRPU0G8oGIVhPyNHE4YAr90zRs8GgZNjViE0=; b=bveRvCQxTwOu5Z/HWu6PsUuPDqMDNW3c6kXlQrO1z+cdSUSmCdPm0SoVXDtDgkTtuI wZRrWydz3qxIo48n4W+skqzduslzlydabFe2mPWiygF6whLfsPXdpaLg5HeS+Y8kqE1c uhCFIb6KZPCoGYVjPpDyM9/9WP+usCJwa3HW8oNJKrwrhlmzhQqDHAvkTcEGxY+LqsPm KVSv+Hp50pTkHHTaE/XMUEzRbwIMzrcH9tcUKmBJxK+P9WKrsDht/3afeMx0ymynJFzf /66xhD9nZj7iEOLIirT8A0J2NkUQ6NziLAQ9xSjxpw4NGsGotRLW6o54x1vuIG0ad3O+ BGtA== X-Gm-Message-State: AOAM530PEqjIVQOPgQAdazPHDOhmXt4nfUK5fEx6ktxYB2sgtP1QVagd 8wA0j9KTiio2x6uAxHwn9eU= X-Google-Smtp-Source: ABdhPJzrlNuE74g1qMDB/HKjZQurMpmUHoKkU6SHJ/TfTL92dLi+ni/w2bYWkHpaV7Z7Rmf350AFqQ== X-Received: by 2002:a2e:9193:: with SMTP id f19mr10913555ljg.41.1622308240394; Sat, 29 May 2021 10:10:40 -0700 (PDT) Received: from localhost.localdomain (46-138-84-89.dynamic.spd-mgts.ru. [46.138.84.89]) by smtp.gmail.com with ESMTPSA id h12sm901715ljh.130.2021.05.29.10.10.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 10:10:40 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 2/7] thermal: thermal_of: Stop zone device before unregistering it Date: Sat, 29 May 2021 20:09:50 +0300 Message-Id: <20210529170955.32574-3-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210529170955.32574-1-digetx@gmail.com> References: <20210529170955.32574-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Zone device is enabled after thermal_zone_of_sensor_register() completion, but it's not disabled before senors if unregistered, leaving temperature polling active. This results in accessing a disabled zone device and produces a warning about this problem. Stop zone device before unregistering it in order to fix this "use-after-free" problem. Signed-off-by: Dmitry Osipenko --- drivers/thermal/thermal_of.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/thermal_of.c b/drivers/thermal/thermal_of.c index 5b76f9a1280d..6379f26a335f 100644 --- a/drivers/thermal/thermal_of.c +++ b/drivers/thermal/thermal_of.c @@ -559,6 +559,9 @@ void thermal_zone_of_sensor_unregister(struct device *dev, if (!tz) return; + /* stop temperature polling */ + thermal_zone_device_disable(tzd); + mutex_lock(&tzd->lock); tzd->ops->get_temp = NULL; tzd->ops->get_trend = NULL; From patchwork Sat May 29 17:09:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12287995 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46CF1C47082 for ; Sat, 29 May 2021 17:10:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2C2CA61104 for ; Sat, 29 May 2021 17:10:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229825AbhE2RMU (ORCPT ); Sat, 29 May 2021 13:12:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229704AbhE2RMT (ORCPT ); Sat, 29 May 2021 13:12:19 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5167C06174A; Sat, 29 May 2021 10:10:42 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id w33so10065352lfu.7; Sat, 29 May 2021 10:10:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AqIoL8w6UW8nZZQW4Ci4myc0ad3mcz0KynC5WY0Sz8A=; b=SC9HOFGn1FJK9Idj7J9epG+7uRSalCCjTpT+ovYZg5X/fmyIftzd/PYsWmCDMADsXO yPh5DjjR3mYVTy8UiEpfk3rxnftJAWcleoVd3zVqEK5gmP8l9vO8qADlmNjoUnQglvkL 8yMl1M+/hwY+5MAsOUcBxkbu5vrxpkxwe1djSjNMMOpYa8OuYe2OfK/F2E9k/FaUDps2 03XgPUlviicdiF7saiT4Mfke/9rxioHnuk3/v9LLVsKeb+ddABuom9ksPd7RT+BhzYTV EZytqkArLyeXYg8axBxn1O2N0f8ReY/ALjK/sQsTbttX/DS58W/u9M+IO8SWBTW1IqP/ 5OBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AqIoL8w6UW8nZZQW4Ci4myc0ad3mcz0KynC5WY0Sz8A=; b=p9IGAV8nggTA2koMLa8oLEeRu2Rl/SArsHkdFVrXxo//dHShXLm4aQWbZD71F5Azth ub6IiC2D0fkSLnveFnzwoOQZJ11E2WDsXnfBzhpoZFz/MzkBHOpHEzo8MBSTpyrkkkPy 5hWU8iUpbbu0+jq+B7mLMPaVlB7Vc7ZEjxzVxOmEaMFeX/sqpsQoBZhX/Y94xlAQpVvg NMOmA3BFUnMKto2hDduBgyWHMcqU4BhH1wWlf4n5WhoCfbRKcG72JKfB1KefNf1yrTB6 uoT8lu40QJLqV3uMJdhb5guIm8Z3yP57SsY2/eusjnOh2uOH6NFuQ/Zs7vQVj3C0Uewk n+5w== X-Gm-Message-State: AOAM5332Z9/WlY9aL1PybbCOYgwuK/ZEzQdNnrGQZayxKIAFZksFPs+t ZwUOkt6r2j7CrFqnvIAxX+U= X-Google-Smtp-Source: ABdhPJyEI8rYuXtAFA+S1t0ksIcqqd+dZ/oKKiQyHBdppzUjByxCYT0MZPoleGxlZpYZbbkdoS031w== X-Received: by 2002:a05:6512:374c:: with SMTP id a12mr9779590lfs.420.1622308241224; Sat, 29 May 2021 10:10:41 -0700 (PDT) Received: from localhost.localdomain (46-138-84-89.dynamic.spd-mgts.ru. [46.138.84.89]) by smtp.gmail.com with ESMTPSA id h12sm901715ljh.130.2021.05.29.10.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 10:10:40 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 3/7] thermal/core: Export thermal_cooling_device_stats_update() Date: Sat, 29 May 2021 20:09:51 +0300 Message-Id: <20210529170955.32574-4-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210529170955.32574-1-digetx@gmail.com> References: <20210529170955.32574-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org NVIDIA Tegra30 thermal sensor driver has a hardware-controlled CPU cooling feature that halves CPU frequency once a specified trip point is breached. In order to account the hardware state transitions, which are reported by interrupt, the sensor driver needs to report the cooling state transition and this is done by thermal_cooling_device_stats_update(). The sensor driver could be compiled as a loadable driver module, but this API function isn't exported, hence export it. Signed-off-by: Dmitry Osipenko --- drivers/thermal/thermal_sysfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/thermal/thermal_sysfs.c b/drivers/thermal/thermal_sysfs.c index 1c4aac8464a7..ab373280f853 100644 --- a/drivers/thermal/thermal_sysfs.c +++ b/drivers/thermal/thermal_sysfs.c @@ -690,6 +690,7 @@ void thermal_cooling_device_stats_update(struct thermal_cooling_device *cdev, unlock: spin_unlock(&stats->lock); } +EXPORT_SYMBOL_GPL(thermal_cooling_device_stats_update); static ssize_t total_trans_show(struct device *dev, struct device_attribute *attr, char *buf) From patchwork Sat May 29 17:09:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12288001 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 009B2C47082 for ; Sat, 29 May 2021 17:10:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D5E65610FC for ; Sat, 29 May 2021 17:10:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229845AbhE2RMX (ORCPT ); Sat, 29 May 2021 13:12:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229839AbhE2RMW (ORCPT ); Sat, 29 May 2021 13:12:22 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1E35C06174A; Sat, 29 May 2021 10:10:43 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id x38so10046048lfa.10; Sat, 29 May 2021 10:10:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IH8BMDskWfmbR7tPWOs8vAh4oaheRb/8a6mIZbgp2B4=; b=lE9bozMoidGzKaSqm18IjAmJZMZWSBY7AGXRrmldSMde6wL4fTqoJg5FLmWP+61v0Z rvQjBp6YFAfkmfeJE6ZA5k8F3+628DJF84gHl6xXdp7Dq7lBMRlefZnXkeyuE27OEpZ2 r4Yvx1IhrmOnABenWkBBBqmOWiNXyLuf93C1mMX0tuMMFZvYfT55OOCuFKrI6Uu9+BFo 5rNnYS5rpbsop2er7gOg5IcrTRx/SpyvHTPyFvW9K0LmmW+JKqKququaCo2pEUfVQrN4 CfpcxhuKiLfIoDd3cb8MtOS2+WgpyOMYZ6+wTP5JYAqArcBtrOawBhR0J/qeApqW7XBi yjHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IH8BMDskWfmbR7tPWOs8vAh4oaheRb/8a6mIZbgp2B4=; b=TegFGIHBbz0Hj4vDyQU+kEhSZoH+0iqZ+yWyztdAdx4Ks8R5LHfwMrwtTNktFfsuHR BS/0TZ1DYmFQ3PdEntoCWNkKHFJVaKGAkjGEd3qtJcYcbHwPe+BbzpqGNTWHZb3HaGva MaigQQ1Vk9S7DYOQ40LLi6PIV5HFxJmI9LNHBPhMbQBrowF7rU/qk8broBdPA23ToZ0+ JdEaLmwUyLh+sfywNcppxFa3TTOQzFe749SHTZ2v7pMvB5iewx84B6NwoQaVlJ/8T52J WetGAHEgd1DhWC/xlY+Qy7cvS0hR8zaNwQZeM5XvBkOzp6nluzaAVfc+/ArEzt4mUTkq pDAA== X-Gm-Message-State: AOAM5317uWG1FDcgOr+GepJD6RBeea78VDRWpiQw1xp/MrDKZb4byVsQ fUNDbpbpcZdf0hHH9+ko22c= X-Google-Smtp-Source: ABdhPJzE5Z4w++YYHjzMI7P/TIP4Uvuj68ZtOK1UI96EOldVjMQHnN2j2/J4JhX5K0G5/pKT5sYbLg== X-Received: by 2002:ac2:5990:: with SMTP id w16mr9623088lfn.270.1622308242170; Sat, 29 May 2021 10:10:42 -0700 (PDT) Received: from localhost.localdomain (46-138-84-89.dynamic.spd-mgts.ru. [46.138.84.89]) by smtp.gmail.com with ESMTPSA id h12sm901715ljh.130.2021.05.29.10.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 10:10:41 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 4/7] thermal/drivers/tegra: Add driver for Tegra30 thermal sensor Date: Sat, 29 May 2021 20:09:52 +0300 Message-Id: <20210529170955.32574-5-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210529170955.32574-1-digetx@gmail.com> References: <20210529170955.32574-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org All NVIDIA Tegra30 SoCs have a two-channel on-chip sensor unit which monitors temperature and voltage of the SoC. Sensors control CPU frequency throttling, which is activated by hardware once preprogrammed temperature level is breached, they also send signal to Power Management controller to perform emergency shutdown on a critical overheat of the SoC die. Add driver for the Tegra30 TSENSOR module, exposing it as a thermal sensor and a cooling device. Tested-by: Andreas Westman Dorcsak # Asus TF700T Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Svyatoslav Ryhel # Asus TF201T Tested-by: Ihor Didenko # Asus TF300T Tested-by: Ion Agorria # Asus TF201T Tested-by: Matt Merhar # Ouya Tested-by: Peter Geis # Ouya Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding --- drivers/thermal/tegra/Kconfig | 7 + drivers/thermal/tegra/Makefile | 1 + drivers/thermal/tegra/tegra30-tsensor.c | 736 ++++++++++++++++++++++++ 3 files changed, 744 insertions(+) create mode 100644 drivers/thermal/tegra/tegra30-tsensor.c diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig index 46c2215867cd..019e3a2eb69e 100644 --- a/drivers/thermal/tegra/Kconfig +++ b/drivers/thermal/tegra/Kconfig @@ -18,4 +18,11 @@ config TEGRA_BPMP_THERMAL Enable this option for support for sensing system temperature of NVIDIA Tegra systems-on-chip with the BPMP coprocessor (Tegra186). +config TEGRA30_TSENSOR + tristate "Tegra30 Thermal Sensor" + depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST + help + Enable this option to support thermal management of NVIDIA Tegra30 + system-on-chip. + endmenu diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile index 0f2b66edf0d2..eb27d194c583 100644 --- a/drivers/thermal/tegra/Makefile +++ b/drivers/thermal/tegra/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o obj-$(CONFIG_TEGRA_BPMP_THERMAL) += tegra-bpmp-thermal.o +obj-$(CONFIG_TEGRA30_TSENSOR) += tegra30-tsensor.o tegra-soctherm-y := soctherm.o soctherm-fuse.o tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o diff --git a/drivers/thermal/tegra/tegra30-tsensor.c b/drivers/thermal/tegra/tegra30-tsensor.c new file mode 100644 index 000000000000..f7562eac01d6 --- /dev/null +++ b/drivers/thermal/tegra/tegra30-tsensor.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tegra30 SoC Thermal Sensor driver + * + * Based on downstream HWMON driver from NVIDIA. + * Copyright (C) 2011 NVIDIA Corporation + * + * Author: Dmitry Osipenko + * Copyright (C) 2021 GRATE-DRIVER project + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "../thermal_core.h" +#include "../thermal_hwmon.h" + +#define TSENSOR_SENSOR0_CONFIG0 0x0 +#define TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP BIT(0) +#define TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN BIT(1) +#define TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN BIT(2) +#define TSENSOR_SENSOR0_CONFIG0_DVFS_EN BIT(3) +#define TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN BIT(4) +#define TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN BIT(5) +#define TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN BIT(6) +#define TSENSOR_SENSOR0_CONFIG0_M GENMASK(23, 8) +#define TSENSOR_SENSOR0_CONFIG0_N GENMASK(31, 24) + +#define TSENSOR_SENSOR0_CONFIG1 0x8 +#define TSENSOR_SENSOR0_CONFIG1_TH1 GENMASK(15, 0) +#define TSENSOR_SENSOR0_CONFIG1_TH2 GENMASK(31, 16) + +#define TSENSOR_SENSOR0_CONFIG2 0xc +#define TSENSOR_SENSOR0_CONFIG2_TH3 GENMASK(15, 0) + +#define TSENSOR_SENSOR0_STATUS0 0x18 +#define TSENSOR_SENSOR0_STATUS0_STATE GENMASK(2, 0) +#define TSENSOR_SENSOR0_STATUS0_INTR BIT(8) +#define TSENSOR_SENSOR0_STATUS0_CURRENT_VALID BIT(9) + +#define TSENSOR_SENSOR0_TS_STATUS1 0x1c +#define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT GENMASK(31, 16) + +#define TEGRA30_FUSE_TEST_PROG_VER 0x28 + +#define TEGRA30_FUSE_TSENSOR_CALIB 0x98 +#define TEGRA30_FUSE_TSENSOR_CALIB_LOW GENMASK(15, 0) +#define TEGRA30_FUSE_TSENSOR_CALIB_HIGH GENMASK(31, 16) + +#define TEGRA30_FUSE_SPARE_BIT 0x144 + +struct tegra_tsensor; + +struct tegra_tsensor_calibration_data { + int a, b, m, n, p, r; +}; + +struct tegra_tsensor_channel { + void __iomem *regs; + unsigned int id; + struct tegra_tsensor *ts; + struct thermal_zone_device *tzd; +}; + +struct tegra_tsensor { + void __iomem *regs; + bool swap_channels; + struct clk *clk; + struct device *dev; + struct reset_control *rst; + struct tegra_tsensor_channel ch[2]; + struct thermal_cooling_device *cdev; + struct tegra_tsensor_calibration_data calib; +}; + +static int tegra_tsensor_hw_enable(const struct tegra_tsensor *ts) +{ + u32 val; + int err; + + err = reset_control_assert(ts->rst); + if (err) { + dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); + return err; + } + + err = clk_prepare_enable(ts->clk); + if (err) { + dev_err(ts->dev, "failed to enable clock: %d\n", err); + return err; + } + + fsleep(1000); + + err = reset_control_deassert(ts->rst); + if (err) { + dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err); + goto disable_clk; + } + + /* + * Sensors are enabled after reset by default, but not gauging + * until clock counter is programmed. + * + * M: number of reference clock pulses after which every + * temperature / voltage measurement is made + * + * N: number of reference clock counts for which the counter runs + */ + val = FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_M, 12500); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_N, 255); + + /* apply the same configuration to both channels */ + writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0); + writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0); + + return 0; + +disable_clk: + clk_disable_unprepare(ts->clk); + + return err; +} + +static int tegra_tsensor_hw_disable(const struct tegra_tsensor *ts) +{ + int err; + + err = reset_control_assert(ts->rst); + if (err) { + dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); + return err; + } + + clk_disable_unprepare(ts->clk); + + return 0; +} + +static void devm_tegra_tsensor_hw_disable(void *data) +{ + const struct tegra_tsensor *ts = data; + + tegra_tsensor_hw_disable(ts); +} + +static int tegra_tsensor_get_temp(void *data, int *temp) +{ + const struct tegra_tsensor_channel *tsc = data; + const struct tegra_tsensor *ts = tsc->ts; + int err, c1, c2, c3, c4, counter; + u32 val; + + /* + * Counter will be invalid if hardware is misprogrammed or not enough + * time passed since the time when sensor was enabled. + */ + err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val, + val & TSENSOR_SENSOR0_STATUS0_CURRENT_VALID, + 21 * USEC_PER_MSEC, + 21 * USEC_PER_MSEC * 50); + if (err) { + dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id); + return err; + } + + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1); + counter = FIELD_GET(TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT, val); + + /* + * This shouldn't happen with a valid counter status, nevertheless + * lets verify the value since it's in a separate (from status) + * register. + */ + if (counter == 0xffff) { + dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id); + return -EINVAL; + } + + /* + * temperature = a * counter + b + * temperature = m * (temperature ^ 2) + n * temperature + p + */ + c1 = DIV_ROUND_CLOSEST(ts->calib.a * counter + ts->calib.b, 1000000); + c1 = c1 ?: 1; + c2 = DIV_ROUND_CLOSEST(ts->calib.p, c1); + c3 = c1 * ts->calib.m; + c4 = ts->calib.n; + + *temp = DIV_ROUND_CLOSEST(c1 * (c2 + c3 + c4), 1000); + + return 0; +} + +static int tegra_tsensor_temp_to_counter(const struct tegra_tsensor *ts, int temp) +{ + int c1, c2; + + c1 = DIV_ROUND_CLOSEST(ts->calib.p - temp * 1000, ts->calib.m); + c2 = -ts->calib.r - int_sqrt(ts->calib.r * ts->calib.r - c1); + + return DIV_ROUND_CLOSEST(c2 * 1000000 - ts->calib.b, ts->calib.a); +} + +static int tegra_tsensor_set_trips(void *data, int low, int high) +{ + const struct tegra_tsensor_channel *tsc = data; + const struct tegra_tsensor *ts = tsc->ts; + u32 val; + + /* + * TSENSOR doesn't trigger interrupt on the "low" temperature breach, + * hence bail out if high temperature is unspecified. + */ + if (high == INT_MAX) + return 0; + + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1); + val &= ~TSENSOR_SENSOR0_CONFIG1_TH1; + + high = tegra_tsensor_temp_to_counter(ts, high); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH1, high); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1); + + return 0; +} + +static const struct thermal_zone_of_device_ops ops = { + .get_temp = tegra_tsensor_get_temp, + .set_trips = tegra_tsensor_set_trips, +}; + +static int tegra_tsensor_get_max_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + *state = 1; + + return 0; +} + +static bool tegra_tsensor_channel_div2_active(const struct tegra_tsensor *ts, + unsigned int id) +{ + u32 val; + + val = readl_relaxed(ts->ch[id].regs + TSENSOR_SENSOR0_CONFIG0); + if (!FIELD_GET(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, val)) + return false; + + val = readl_relaxed(ts->ch[id].regs + TSENSOR_SENSOR0_STATUS0); + + /* CPU frequency is halved when LEVEL2 is breached */ + return FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) > 2; +} + +static int tegra_tsensor_get_cur_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + const struct tegra_tsensor *ts = cdev->devdata; + unsigned int i, div2_state = 0; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) + div2_state |= tegra_tsensor_channel_div2_active(ts, i); + + *state = div2_state; + + return 0; +} + +static int tegra_tsensor_set_cur_state(struct thermal_cooling_device *cdev, + unsigned long state) +{ + /* state is controlled by hardware and can't be changed by software */ + return -EOPNOTSUPP; +} + +static const struct thermal_cooling_device_ops tegra_tsensor_cpu_cooling_ops = { + .get_max_state = tegra_tsensor_get_max_state, + .get_cur_state = tegra_tsensor_get_cur_state, + .set_cur_state = tegra_tsensor_set_cur_state, +}; + +static bool +tegra_tsensor_handle_channel_interrupt(const struct tegra_tsensor *ts, + unsigned int id) +{ + const struct tegra_tsensor_channel *tsc = &ts->ch[id]; + u32 val; + + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_STATUS0); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0); + + if (FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) == 5) + dev_err_ratelimited(ts->dev, "ch%u: counter overflowed\n", id); + + if (!FIELD_GET(TSENSOR_SENSOR0_STATUS0_INTR, val)) + return false; + + thermal_zone_device_update(tsc->tzd, THERMAL_EVENT_UNSPECIFIED); + + return true; +} + +static irqreturn_t tegra_tsensor_isr(int irq, void *data) +{ + const struct tegra_tsensor *ts = data; + bool div2_state = false; + bool handled = false; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + div2_state |= tegra_tsensor_channel_div2_active(ts, i); + handled |= tegra_tsensor_handle_channel_interrupt(ts, i); + } + + thermal_cooling_device_stats_update(ts->cdev, div2_state); + + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +static int tegra_tsensor_disable_hw_channel(const struct tegra_tsensor *ts, + unsigned int id) +{ + const struct tegra_tsensor_channel *tsc = &ts->ch[id]; + struct thermal_zone_device *tzd = tsc->tzd; + u32 val; + int err; + + if (!tzd) + goto stop_channel; + + err = thermal_zone_device_disable(tzd); + if (err) { + dev_err(ts->dev, "ch%u: failed to disable zone: %d\n", id, err); + return err; + } + +stop_channel: + /* stop channel gracefully */ + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP, 1); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); + + return 0; +} + +static void tegra_tsensor_get_hw_channel_trips(struct thermal_zone_device *tzd, + int *hot_trip, int *crit_trip) +{ + unsigned int i; + + /* + * 90C is the maximal critical temperature of all Tegra30 SoC variants, + * use it for the default trip if unspecified in a device-tree. + */ + *hot_trip = 85000; + *crit_trip = 90000; + + for (i = 0; i < tzd->trips; i++) { + enum thermal_trip_type type; + int trip_temp; + + tzd->ops->get_trip_temp(tzd, i, &trip_temp); + tzd->ops->get_trip_type(tzd, i, &type); + + if (type == THERMAL_TRIP_HOT) + *hot_trip = trip_temp; + + if (type == THERMAL_TRIP_CRITICAL) + *crit_trip = trip_temp; + } + + /* clamp hardware trips to the calibration limits */ + *hot_trip = clamp(*hot_trip, 25000, 90000); + + /* + * Kernel will perform a normal system shut down if it will + * see that critical temperature is breached, hence set the + * hardware limit by 5C higher in order to allow system to + * shut down gracefully before sending signal to the Power + * Management controller. + */ + *crit_trip = clamp(*crit_trip + 5000, 25000, 90000); +} + +static int tegra_tsensor_enable_hw_channel(const struct tegra_tsensor *ts, + unsigned int id) +{ + const struct tegra_tsensor_channel *tsc = &ts->ch[id]; + struct thermal_zone_device *tzd = tsc->tzd; + int err, hot_trip = 0, crit_trip = 0; + u32 val; + + if (!tzd) { + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); + val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP; + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); + + return 0; + } + + tegra_tsensor_get_hw_channel_trips(tzd, &hot_trip, &crit_trip); + + /* prevent potential racing with tegra_tsensor_set_trips() */ + mutex_lock(&tzd->lock); + + dev_info_once(ts->dev, "ch%u: CPU freq div2 throttle trip set to %dC\n", + id, DIV_ROUND_CLOSEST(hot_trip, 1000)); + + dev_info_once(ts->dev, "ch%u: PMC emergency shutdown trip set to %dC\n", + id, DIV_ROUND_CLOSEST(crit_trip, 1000)); + + hot_trip = tegra_tsensor_temp_to_counter(ts, hot_trip); + crit_trip = tegra_tsensor_temp_to_counter(ts, crit_trip); + + /* program LEVEL2 counter threshold */ + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1); + val &= ~TSENSOR_SENSOR0_CONFIG1_TH2; + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH2, hot_trip); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1); + + /* program LEVEL3 counter threshold */ + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG2); + val &= ~TSENSOR_SENSOR0_CONFIG2_TH3; + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG2_TH3, crit_trip); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2); + + /* + * Enable sensor, DIV2 throttle, emergency shutdown, interrupts + * for level 1/2/3 breaches and counter overflow condition. + * + * Thermal levels supported by hardware: + * + * Level 0 = cold + * Level 1 = passive cooling (cpufreq DVFS) + * Level 2 = passive cooling assisted by hardware (DIV2) + * Level 3 = emergency shutdown assisted by hardware (PMC) + */ + val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); + val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP; + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_DVFS_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN, 1); + val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN, 1); + writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); + + mutex_unlock(&tzd->lock); + + err = thermal_zone_device_enable(tzd); + if (err) { + dev_err(ts->dev, "ch%u: failed to enable zone: %d\n", id, err); + return err; + } + + return 0; +} + +static bool tegra_tsensor_fuse_read_spare(unsigned int spare) +{ + u32 val = 0; + + tegra_fuse_readl(TEGRA30_FUSE_SPARE_BIT + spare * 4, &val); + + return !!val; +} + +static int tegra_tsensor_nvmem_setup(struct tegra_tsensor *ts) +{ + u32 i, ate_ver = 0, cal = 0, t1_25C = 0, t2_90C = 0; + int err, c1_25C, c2_90C; + + err = tegra_fuse_readl(TEGRA30_FUSE_TEST_PROG_VER, &ate_ver); + if (err) { + dev_err_probe(ts->dev, err, "failed to get ATE version\n"); + return err; + } + + if (ate_ver < 8) { + dev_info(ts->dev, "unsupported ATE version: %u\n", ate_ver); + return -ENODEV; + } + + /* + * We have two TSENSOR channels in a two different spots on SoC. + * Second channel provides more accurate data on older SoC versions, + * use it as a primary channel. + */ + if (ate_ver <= 21) { + dev_info_once(ts->dev, + "older ATE version detected, channels remapped\n"); + ts->swap_channels = true; + } + + err = tegra_fuse_readl(TEGRA30_FUSE_TSENSOR_CALIB, &cal); + if (err) { + dev_err(ts->dev, "failed to get calibration data: %d\n", err); + return err; + } + + /* get calibrated counter values for 25C/90C thresholds */ + c1_25C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_LOW, cal); + c2_90C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_HIGH, cal); + + /* and calibrated temperatures corresponding to the counter values */ + for (i = 0; i < 7; i++) { + t1_25C |= tegra_tsensor_fuse_read_spare(14 + i) << i; + t1_25C |= tegra_tsensor_fuse_read_spare(21 + i) << i; + + t2_90C |= tegra_tsensor_fuse_read_spare(0 + i) << i; + t2_90C |= tegra_tsensor_fuse_read_spare(7 + i) << i; + } + + if (c2_90C - c1_25C <= t2_90C - t1_25C) { + dev_err(ts->dev, "invalid calibration data: %d %d %u %u\n", + c2_90C, c1_25C, t2_90C, t1_25C); + return -EINVAL; + } + + /* all calibration coefficients are premultiplied by 1000000 */ + + ts->calib.a = DIV_ROUND_CLOSEST((t2_90C - t1_25C) * 1000000, + (c2_90C - c1_25C)); + + ts->calib.b = t1_25C * 1000000 - ts->calib.a * c1_25C; + + if (tegra_sku_info.revision == TEGRA_REVISION_A01) { + ts->calib.m = -2775; + ts->calib.n = 1338811; + ts->calib.p = -7300000; + } else { + ts->calib.m = -3512; + ts->calib.n = 1528943; + ts->calib.p = -11100000; + } + + /* except the coefficient of a reduced quadratic equation */ + ts->calib.r = DIV_ROUND_CLOSEST(ts->calib.n, ts->calib.m * 2); + + dev_info_once(ts->dev, + "calibration: %d %d %u %u ATE ver: %u SoC rev: %u\n", + c2_90C, c1_25C, t2_90C, t1_25C, ate_ver, + tegra_sku_info.revision); + + return 0; +} + +static int tegra_tsensor_register_channel(struct tegra_tsensor *ts, + unsigned int id) +{ + struct tegra_tsensor_channel *tsc = &ts->ch[id]; + unsigned int hw_id = ts->swap_channels ? !id : id; + + tsc->ts = ts; + tsc->id = id; + tsc->regs = ts->regs + 0x40 * (hw_id + 1); + + tsc->tzd = devm_thermal_zone_of_sensor_register(ts->dev, id, tsc, &ops); + if (IS_ERR(tsc->tzd)) { + if (PTR_ERR(tsc->tzd) != -ENODEV) + return dev_err_probe(ts->dev, PTR_ERR(tsc->tzd), + "failed to register thermal zone\n"); + + /* + * It's okay if sensor isn't assigned to any thermal zone + * in a device-tree. + */ + tsc->tzd = NULL; + return 0; + } + + if (devm_thermal_add_hwmon_sysfs(tsc->tzd)) + dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n"); + + return 0; +} + +static int tegra_tsensor_probe(struct platform_device *pdev) +{ + struct tegra_tsensor *ts; + unsigned int i; + int err, irq; + + ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL); + if (!ts) + return -ENOMEM; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ts->dev = &pdev->dev; + platform_set_drvdata(pdev, ts); + + ts->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ts->regs)) + return PTR_ERR(ts->regs); + + ts->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(ts->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(ts->clk), + "failed to get clock\n"); + + ts->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(ts->rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(ts->rst), + "failed to get reset control\n"); + + err = tegra_tsensor_nvmem_setup(ts); + if (err) + return err; + + err = tegra_tsensor_hw_enable(ts); + if (err) + return err; + + err = devm_add_action_or_reset(&pdev->dev, + devm_tegra_tsensor_hw_disable, + ts); + if (err) + return err; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + err = tegra_tsensor_register_channel(ts, i); + if (err) + return err; + } + + ts->cdev = devm_thermal_of_cooling_device_register(&pdev->dev, + pdev->dev.of_node, "tegra-cpu-div2-throttle", + ts, &tegra_tsensor_cpu_cooling_ops); + if (IS_ERR(ts->cdev)) + return dev_err_probe(&pdev->dev, PTR_ERR(ts->cdev), + "failed to register cooling device\n"); + + err = devm_request_threaded_irq(&pdev->dev, irq, NULL, + tegra_tsensor_isr, IRQF_ONESHOT, + "tegra_tsensor", ts); + if (err) + return dev_err_probe(&pdev->dev, err, + "failed to request interrupt\n"); + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + err = tegra_tsensor_enable_hw_channel(ts, i); + if (err) + return err; + } + + return 0; +} + +static int __maybe_unused tegra_tsensor_suspend(struct device *dev) +{ + struct tegra_tsensor *ts = dev_get_drvdata(dev); + unsigned int i; + int err; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + err = tegra_tsensor_disable_hw_channel(ts, i); + if (err) + goto enable_channel; + } + + err = tegra_tsensor_hw_disable(ts); + if (err) + goto enable_channel; + + return 0; + +enable_channel: + while (i--) + tegra_tsensor_enable_hw_channel(ts, i); + + return err; +} + +static int __maybe_unused tegra_tsensor_resume(struct device *dev) +{ + struct tegra_tsensor *ts = dev_get_drvdata(dev); + unsigned int i; + int err; + + err = tegra_tsensor_hw_enable(ts); + if (err) + return err; + + for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { + err = tegra_tsensor_enable_hw_channel(ts, i); + if (err) + return err; + } + + return 0; +} + +static const struct dev_pm_ops tegra_tsensor_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_tsensor_suspend, + tegra_tsensor_resume) +}; + +static const struct of_device_id tegra_tsensor_of_match[] = { + { .compatible = "nvidia,tegra30-tsensor", }, + {}, +}; +MODULE_DEVICE_TABLE(of, tegra_tsensor_of_match); + +static struct platform_driver tegra_tsensor_driver = { + .probe = tegra_tsensor_probe, + .driver = { + .name = "tegra30-tsensor", + .of_match_table = tegra_tsensor_of_match, + .pm = &tegra_tsensor_pm_ops, + }, +}; +module_platform_driver(tegra_tsensor_driver); + +MODULE_DESCRIPTION("NVIDIA Tegra30 Thermal Sensor driver"); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_LICENSE("GPL"); From patchwork Sat May 29 17:09:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12287999 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6779AC47093 for ; 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[46.138.84.89]) by smtp.gmail.com with ESMTPSA id h12sm901715ljh.130.2021.05.29.10.10.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 10:10:42 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 5/7] ARM: tegra_defconfig: Enable CONFIG_TEGRA30_TSENSOR Date: Sat, 29 May 2021 20:09:53 +0300 Message-Id: <20210529170955.32574-6-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210529170955.32574-1-digetx@gmail.com> References: <20210529170955.32574-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable NVIDIA Tegra30 SoC thermal sensor driver in tegra_defconfig. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/tegra_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 3d8d8af9524d..63e7f3261e6d 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -169,6 +169,7 @@ CONFIG_THERMAL_STATISTICS=y CONFIG_CPU_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_TEGRA_SOCTHERM=m +CONFIG_TEGRA30_TSENSOR=m CONFIG_WATCHDOG=y CONFIG_MAX77620_WATCHDOG=y CONFIG_TEGRA_WATCHDOG=y From patchwork Sat May 29 17:09:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12288003 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11F72C4709E for ; Sat, 29 May 2021 17:10:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E473161104 for ; Sat, 29 May 2021 17:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229881AbhE2RM0 (ORCPT ); Sat, 29 May 2021 13:12:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229851AbhE2RMX (ORCPT ); Sat, 29 May 2021 13:12:23 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C33FC061574; Sat, 29 May 2021 10:10:45 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id f30so10130287lfj.1; Sat, 29 May 2021 10:10:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uG0wF9x5J31B5QovgpxzHE3VxGkFw0gZRlBKzlTkO48=; b=YNpD36hsPQ45qUtw8B28Q9nG9ZzBBjoeBj5/0zS6S9J+LiA4+6Qdh4dYVss7GfIGkt 74iJBtqxqzgCIGq1/7riA7MkLShiUGI8hBsQLGeQp6L3uauf8TtdGgLGsP1twXQf2sac TMu9OW4wm7onG4Zfo0HJmXRZl+cFRX0dIYxxmcIVk9M/N+lQDVuASZ+Wn61G81McwJGc LnjilsCskV4NofFzaKPblkcdNDuIfAjesRYaeaN/Lb4SUm9ZAU7+feUK19WDBA6ix0Vi MIotrfcDPW3GiF3oIkPLn7pnxt78mG7ZEnDicDFlKjvklpZsNRVdL8k8YH8tSsTfk90F Fz/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uG0wF9x5J31B5QovgpxzHE3VxGkFw0gZRlBKzlTkO48=; b=Xqmv/o9ovlPgLwD0KEImh+D0ZST+0AE2+vghc/v97xE2WdB/ydM6Otmqz6qJ12eU1N hWlTRHkGL3JZDKmsZhplva9PmoT/AxHiH2kF3JGrD4IEcT0G3MG3VE2tHlSWaCSuP9Vz l7PLUDm6FPU+7j0UeNbc0z42fFNEOfAhtgqIEh11rL98EHuVk+Z64cUnh4hEktx21Em+ Cnlbb44UqLXgIH/guPP+Ks30VFQSP9ueUPUJGB0MsYaT1Zaz/lOm+c0kJ7GNwpttxcXO UzG1i4VHZ61GZSliT+ZbROGc8kAVjojK6ciSRYTMqAdzvdlv5Y3nw40pulT1nv91gqrr dNAQ== X-Gm-Message-State: AOAM532CwEsPVuoXOHNxeiAjt30dOJqctj8LHOSNSIejCRUUW0R5/SiX V/9ZnSdq+T4jeQEsP6BkYRDyvMpn5yc= X-Google-Smtp-Source: ABdhPJy6gHfOnZuQmJd7NMeqZJaT8AyHCBdb2KRGRIy4gpCNNP1NevOiAgYPasZ3Bf7LwFV8OmgJ+Q== X-Received: by 2002:a05:6512:308a:: with SMTP id z10mr9363913lfd.601.1622308244024; Sat, 29 May 2021 10:10:44 -0700 (PDT) Received: from localhost.localdomain (46-138-84-89.dynamic.spd-mgts.ru. [46.138.84.89]) by smtp.gmail.com with ESMTPSA id h12sm901715ljh.130.2021.05.29.10.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 10:10:43 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 6/7] ARM: multi_v7_defconfig: Enable CONFIG_TEGRA30_TSENSOR Date: Sat, 29 May 2021 20:09:54 +0300 Message-Id: <20210529170955.32574-7-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210529170955.32574-1-digetx@gmail.com> References: <20210529170955.32574-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable NVIDIA Tegra30 SoC thermal sensor driver in multi_v7_defconfig. Signed-off-by: Dmitry Osipenko --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 52a0400fdd92..fc346f87d7f9 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -523,6 +523,7 @@ CONFIG_BRCMSTB_THERMAL=m CONFIG_GENERIC_ADC_THERMAL=m CONFIG_ST_THERMAL_MEMMAP=y CONFIG_TEGRA_SOCTHERM=m +CONFIG_TEGRA30_TSENSOR=m CONFIG_UNIPHIER_THERMAL=y CONFIG_DA9063_WATCHDOG=m CONFIG_XILINX_WATCHDOG=y From patchwork Sat May 29 17:09:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12288005 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DFA8C4709B for ; Sat, 29 May 2021 17:10:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 911B66112F for ; Sat, 29 May 2021 17:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229873AbhE2RMZ (ORCPT ); Sat, 29 May 2021 13:12:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229716AbhE2RMX (ORCPT ); Sat, 29 May 2021 13:12:23 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6987EC0613ED; Sat, 29 May 2021 10:10:46 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id e2so9257120ljk.4; Sat, 29 May 2021 10:10:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SZjslNJj0RrvMEBltMfpTerrLG/TtMo8+YaLhqfm6kQ=; b=TDW8ZzXYDp2oc6DphvUGC+WHNYNIMexOtligeBq3SVRlKqHVDXAU08brKpUsnjayP1 WZ2iW0bZqX567d6cDo96Sx/yAEe6kTsvl2AIWbyo8uUHUegAk9pJbYvFrBjYrUxgLCoo /2NTQtZu4gU9kQJPMtBqmsIcDCki0lQSor+a9BqDxLB1ftMp4x/Q2t/Th2BTIIOzsZ72 wpu6VdfwiuJjrldsWyXTnvXHVk4pvgURytckbegPRkzME/FCSHXP+SeFj1JpQFPWP8r7 RdVwdAFA01GYoRA/CluHzJSS1FQRDmlopxQgz37IsI/BEb8eQ6xolHmmesiUYHp1mUxh rYJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SZjslNJj0RrvMEBltMfpTerrLG/TtMo8+YaLhqfm6kQ=; b=QfbUDqPmB3eywMQ8YxiHmfDeceug3vn6vjGm9OOUGYwDrVNfDAEDLooKSCg8IH05b5 YGCn5k8atR5WOIwOdK3zQANB+mrLGBdutklJx0jrSYbCEtUPj34aH7WGTSLqUT65mFTK IuwuQAT1Mr9tyUO4D9MqctEgIK8u/iHhmbqdeAJKvtbJKqroWERlunKLGagHAEh2/OiD GM405k44Db4ln1B1s36EYfuLFxwBhU9s9GBvqN9jfHQ2q9utmvzUotlNpnKk32ROlCji vCPVTWH0IOUyTEEJGj+SFDtfDwOsT9kBfrvDwu1jZHBGlNCRKt+pmCSnvazxKjqcT5MO XWyA== X-Gm-Message-State: AOAM530sahC7aL8kWvSaQAOeyfLjOl/4aW7oGjsZcGGw/6B+J5YYn/cl l0/pHIHwP3h/Jjwqs7xNt8I= X-Google-Smtp-Source: ABdhPJxfszUulR2F0ddmj6BL948l0w7cS2dxVOk69YLRIId7Ube1bp7zOyHXXYO8qkXKORXezYDvGg== X-Received: by 2002:a2e:8717:: with SMTP id m23mr11079864lji.161.1622308244846; Sat, 29 May 2021 10:10:44 -0700 (PDT) Received: from localhost.localdomain (46-138-84-89.dynamic.spd-mgts.ru. [46.138.84.89]) by smtp.gmail.com with ESMTPSA id h12sm901715ljh.130.2021.05.29.10.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 May 2021 10:10:44 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Zhang Rui , Daniel Lezcano , Amit Kucheria , Andreas Westman Dorcsak , Maxim Schwalm , Svyatoslav Ryhel , Ihor Didenko , Ion Agorria , Matt Merhar , Peter Geis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 7/7] ARM: tegra: Add SoC thermal sensor to Tegra30 device-trees Date: Sat, 29 May 2021 20:09:55 +0300 Message-Id: <20210529170955.32574-8-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210529170955.32574-1-digetx@gmail.com> References: <20210529170955.32574-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add the on-chip SoC thermal sensor to Tegra30 device-trees. Now CPU temperature reporting and thermal throttling is available on all Tegra30 devices universally. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-ouya.dts | 16 +++++ arch/arm/boot/dts/tegra30.dtsi | 93 ++++++++++++++++++++++++++++-- 2 files changed, 105 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index e767ac227a81..d792ce5c64c0 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -468,6 +468,22 @@ map1 { }; }; }; + + tsensor-channel0 { + trips { + dvfs-alert { + temperature = <70000>; + }; + + cpu-div2-throttle { + temperature = <75000>; + }; + + soc-critical { + temperature = <90000>; + }; + }; + }; }; vdd_12v_in: vdd_12v_in { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index c577c191be4b..6becbadef210 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include "tegra30-peripherals-opp.dtsi" @@ -800,6 +801,21 @@ fuse@7000f800 { reset-names = "fuse"; }; + tsensor: tsensor@70014000 { + compatible = "nvidia,tegra30-tsensor"; + reg = <0x70014000 0x500>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; + resets = <&tegra_car TEGRA30_CLK_TSENSOR>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>; + assigned-clock-rates = <500000>; + + #thermal-sensor-cells = <1>; + #cooling-cells = <2>; + }; + hda@70030000 { compatible = "nvidia,tegra30-hda"; reg = <0x70030000 0x10000>; @@ -1062,32 +1078,36 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; + #cooling-cells = <2>; }; }; @@ -1102,4 +1122,69 @@ pmu { <&{/cpus/cpu@2}>, <&{/cpus/cpu@3}>; }; + + thermal-zones { + tsensor-channel0 { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsensor 0>; + + trips { + level1_trip: dvfs-alert { + /* throttle at 67C until temperature drops to 66.8C */ + temperature = <67000>; + hysteresis = <200>; + type = "passive"; + }; + + level2_trip: cpu-div2-throttle { + /* hardware CPU x2 freq throttle at 70C */ + temperature = <70000>; + hysteresis = <200>; + type = "hot"; + }; + + soc-critical { + /* hardware shut down at 80C */ + temperature = <80000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&level1_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&level2_trip>; + cooling-device = <&tsensor THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + tsensor-channel1 { + status = "disabled"; + + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <0>; /* milliseconds */ + + thermal-sensors = <&tsensor 1>; + + trips { + dvfs-alert { + temperature = <80000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + }; };