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[24.5.140.25]) by smtp.googlemail.com with ESMTPSA id d68sm703139pfa.64.2018.11.28.20.19.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Nov 2018 20:19:36 -0800 (PST) From: Nick Desaulniers To: will.deacon@arm.com Subject: [PATCH] arm64: io: specify asm operand width for __iormb() Date: Wed, 28 Nov 2018 20:19:10 -0800 Message-Id: <20181129041912.5918-1-nick.desaulniers@gmail.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181128_201948_544719_B63A499B X-CRM114-Status: GOOD ( 13.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jens Axboe , Catalin Marinas , Nick Desaulniers , linux-kernel@vger.kernel.org, natechancellor@gmail.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes the warning produced from Clang: ./include/asm-generic/io.h:711:9: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths] return readl(addr); ^ ./arch/arm64/include/asm/io.h:149:58: note: expanded from macro 'readl' ^ ./include/asm-generic/io.h:711:9: note: use constraint modifier "w" ./arch/arm64/include/asm/io.h:149:50: note: expanded from macro 'readl' ^ ./arch/arm64/include/asm/io.h:118:25: note: expanded from macro '__iormb' asm volatile("eor %w0, %1, %1\n" \ ^ Though we disable Clang's integrated assembler with -no-integrated-as, it still tries to do some validation of assembler constraints. While __iormb() is type agnostic to operand widths for argument v, its lone use is to zero'd out via eor (exclusive or). Fixes commit 6460d3201471 ("arm64: io: Ensure calls to delay routines are ordered against prior readX()") Link: https://github.com/ClangBuiltLinux/continuous-integration/issues/78 Suggested-by: Nathan Chancellor Reviewed-by: Nathan Chancellor Signed-off-by: Nick Desaulniers --- Side note: is it not correct to cite SHAs from linux-next in "Fixes commit ..." lines? I guess we can drop it. Link to regression build: https://travis-ci.com/ClangBuiltLinux/continuous-integration/builds/92799938 Link to build w/ this patch: https://travis-ci.com/ClangBuiltLinux/continuous-integration/builds/92935901 arch/arm64/include/asm/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index d42d00d8d5b6..dbdebf81162b 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -115,7 +115,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * later instructions. This ensures that a subsequent call to \ * udelay() will be ordered due to the ISB in get_cycles(). \ */ \ - asm volatile("eor %0, %1, %1\n" \ + asm volatile("eor %0, %x1, %x1\n" \ "cbnz %0, ." \ : "=r" (tmp) : "r" (v) : "memory"); \ })