From patchwork Thu Nov 29 06:38:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kevin Strasser X-Patchwork-Id: 10704071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8097414E2 for ; Thu, 29 Nov 2018 06:38:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74C2A2E57D for ; Thu, 29 Nov 2018 06:38:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 691B62EA51; Thu, 29 Nov 2018 06:38:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 108692E57D for ; Thu, 29 Nov 2018 06:38:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA80F6E471; Thu, 29 Nov 2018 06:38:21 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id BEF586E46A; Thu, 29 Nov 2018 06:38:14 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Nov 2018 22:38:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,293,1539673200"; d="scan'208";a="96604227" Received: from z170x-ud5.jf.intel.com ([10.54.75.40]) by orsmga008.jf.intel.com with ESMTP; 28 Nov 2018 22:38:14 -0800 From: Kevin Strasser To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 1/3] drm/fourcc: Add 64 bpp half float formats Date: Wed, 28 Nov 2018 22:38:11 -0800 Message-Id: <1543473493-30973-2-git-send-email-kevin.strasser@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543473493-30973-1-git-send-email-kevin.strasser@intel.com> References: <1543473493-30973-1-git-send-email-kevin.strasser@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Daniel Vetter , Tina Zhang , Uma Shankar Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add 64 bpp 16:16:16:16 half float pixel formats. Each 16 bit component is formatted in IEEE-754 half-precision float (binary16) 1:5:10 MSb-sign:exponent:fraction form. An 'is_fp' attribute is added to drm_format_info so that drivers can easily distinguish these formats from those that might contain uint pixel data. This patch attempts to address the feedback provided when 2 of these formats were previosly proposed: https://patchwork.kernel.org/patch/10072545/ Signed-off-by: Kevin Strasser Cc: Tina Zhang Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-devel@lists.freedesktop.org --- drivers/gpu/drm/drm_fourcc.c | 4 ++++ include/drm/drm_fourcc.h | 3 +++ include/uapi/drm/drm_fourcc.h | 6 ++++++ 3 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index f523948..a7b969a 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -198,6 +198,10 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, { .format = DRM_FORMAT_RGBA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, + { .format = DRM_FORMAT_XRGB16161616H, .depth = 48, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_fp = true }, + { .format = DRM_FORMAT_XBGR16161616H, .depth = 48, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_fp = true }, + { .format = DRM_FORMAT_ARGB16161616H, .depth = 64, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_fp = true }, + { .format = DRM_FORMAT_ABGR16161616H, .depth = 64, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_fp = true }, { .format = DRM_FORMAT_RGB888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, { .format = DRM_FORMAT_BGR888_A8, .depth = 32, .num_planes = 2, .cpp = { 3, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, { .format = DRM_FORMAT_XRGB8888_A8, .depth = 32, .num_planes = 2, .cpp = { 4, 1, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true }, diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index bcb389f..2c5aa19 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -133,6 +133,9 @@ struct drm_format_info { /** @is_yuv: Is it a YUV format? */ bool is_yuv; + + /** @is_fp: Is it a floating point format? */ + bool is_fp; }; /** diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index e7e48f1f..530bce4 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -144,6 +144,12 @@ extern "C" { #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ +/* 64 bpp RGB IEEE-754 half-precision float (binary16) */ +#define DRM_FORMAT_XBGR16161616H fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616H fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#define DRM_FORMAT_XRGB16161616H fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ARGB16161616H fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ + /* packed YCbCr */ #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ From patchwork Thu Nov 29 06:38:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kevin Strasser X-Patchwork-Id: 10704073 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC30B13BF for ; Thu, 29 Nov 2018 06:38:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF9BC2EA51 for ; Thu, 29 Nov 2018 06:38:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D39FA2EA5A; Thu, 29 Nov 2018 06:38:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5A4C22EA51 for ; Thu, 29 Nov 2018 06:38:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A482D6E472; Thu, 29 Nov 2018 06:38:22 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C1D76E46A; Thu, 29 Nov 2018 06:38:15 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Nov 2018 22:38:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,293,1539673200"; d="scan'208";a="96604228" Received: from z170x-ud5.jf.intel.com ([10.54.75.40]) by orsmga008.jf.intel.com with ESMTP; 28 Nov 2018 22:38:14 -0800 From: Kevin Strasser To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 2/3] drm: Add optional PIXEL_NORMALIZE_RANGE property to drm_plane Date: Wed, 28 Nov 2018 22:38:12 -0800 Message-Id: <1543473493-30973-3-git-send-email-kevin.strasser@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543473493-30973-1-git-send-email-kevin.strasser@intel.com> References: <1543473493-30973-1-git-send-email-kevin.strasser@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Daniel Vetter , Uma Shankar Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add an optional property to allow applications to indicate what range their floating point pixel data is normalized to. Drivers are free to choose what ranges they want to support and can attach this property to each plane that actually supports floating point formats Signed-off-by: Kevin Strasser Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-devel@lists.freedesktop.org --- drivers/gpu/drm/drm_atomic.c | 2 ++ drivers/gpu/drm/drm_atomic_uapi.c | 4 +++ drivers/gpu/drm/drm_color_mgmt.c | 68 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/drm_crtc_internal.h | 1 + include/drm/drm_color_mgmt.h | 9 +++++ include/drm/drm_plane.h | 14 ++++++++ 6 files changed, 98 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 1706ed1..1f520ef 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -624,6 +624,8 @@ static void drm_atomic_plane_print_state(struct drm_printer *p, drm_get_color_encoding_name(state->color_encoding)); drm_printf(p, "\tcolor-range=%s\n", drm_get_color_range_name(state->color_range)); + drm_printf(p, "\tpixel-normalize-range=%s\n", + drm_get_pixel_normalize_range_name(state->pixel_normalize_range)); if (plane->funcs->atomic_print_state) plane->funcs->atomic_print_state(p, state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 86ac339..e79a23cd 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -566,6 +566,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, state->color_encoding = val; } else if (property == plane->color_range_property) { state->color_range = val; + } else if (property == plane->pixel_normalize_range_property) { + state->pixel_normalize_range = val; } else if (plane->funcs->atomic_set_property) { return plane->funcs->atomic_set_property(plane, state, property, val); @@ -621,6 +623,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane, *val = state->color_encoding; } else if (property == plane->color_range_property) { *val = state->color_range; + } else if (property == plane->pixel_normalize_range_property) { + *val = state->pixel_normalize_range; } else if (plane->funcs->atomic_get_property) { return plane->funcs->atomic_get_property(plane, state, property, val); } else { diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 581cc37..b1e2a0a 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -472,3 +472,71 @@ int drm_plane_create_color_properties(struct drm_plane *plane, return 0; } EXPORT_SYMBOL(drm_plane_create_color_properties); + +static const char * const pixel_normalize_range_name[] = { + [DRM_PIXEL_NORMALIZE_RANGE_0_1] = "0.0 - 1.0", + [DRM_PIXEL_NORMALIZE_RANGE_0_255] = "0.0 - 255.0", +}; + +/** + * drm_get_pixel_normalize_range_name - return a string for pixel normalize + * range + * @range: pixel normalize range to compute name of + * + * In contrast to the other drm_get_*_name functions this one here returns a + * const pointer and hence is threadsafe. + */ +const char *drm_get_pixel_normalize_range_name(enum drm_pixel_normalize_range range) +{ + if (WARN_ON(range >= ARRAY_SIZE(pixel_normalize_range_name))) + return "unknown"; + + return pixel_normalize_range_name[range]; +} + +/** + * drm_plane_create_pixel_normalize_range_property - pixel normalize range + * property + * @plane: plane object + * @supported_ranges: bitfield indicating supported normalize ranges + * @default_range: default normalize range + * + * Create and attach plane specific PIXEL_NORMALIZE_RANGE property to @plane. + * The supported ranges should be provided in supported_ranges bitmask. Eeach + * bit set in the bitmask indicates that its number as enum value is supported. + */ +int drm_plane_create_pixel_normalize_range_property(struct drm_plane *plane, + u32 supported_ranges, enum drm_pixel_normalize_range default_range) +{ + struct drm_property *prop; + struct drm_prop_enum_list enum_list[DRM_PIXEL_NORMALIZE_RANGE_MAX]; + int i, len = 0; + + if (WARN_ON(supported_ranges == 0 || + (supported_ranges & -BIT(DRM_PIXEL_NORMALIZE_RANGE_MAX)) != 0 || + (supported_ranges & BIT(default_range)) == 0)) + return -EINVAL; + + for (i = 0; i < DRM_PIXEL_NORMALIZE_RANGE_MAX; i++) { + if ((supported_ranges & BIT(i)) == 0) + continue; + + enum_list[len].type = i; + enum_list[len].name = pixel_normalize_range_name[i]; + len++; + } + + prop = drm_property_create_enum(plane->dev, 0, "PIXEL_NORMALIZE_RANGE", + enum_list, len); + if (!prop) + return -ENOMEM; + + plane->pixel_normalize_range_property = prop; + drm_object_attach_property(&plane->base, prop, default_range); + + if (plane->state) + plane->state->pixel_normalize_range = default_range; + + return 0; +} +EXPORT_SYMBOL(drm_plane_create_pixel_normalize_range_property); diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index 8689344..82ddc50 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -90,6 +90,7 @@ int drm_mode_destroy_dumb_ioctl(struct drm_device *dev, /* drm_color_mgmt.c */ const char *drm_get_color_encoding_name(enum drm_color_encoding encoding); const char *drm_get_color_range_name(enum drm_color_range range); +const char *drm_get_pixel_normalize_range_name(enum drm_pixel_normalize_range range); /* IOCTLs */ int drm_mode_gamma_get_ioctl(struct drm_device *dev, diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 90ef999..460e31c 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -64,9 +64,18 @@ enum drm_color_range { DRM_COLOR_RANGE_MAX, }; +enum drm_pixel_normalize_range { + DRM_PIXEL_NORMALIZE_RANGE_0_1, + DRM_PIXEL_NORMALIZE_RANGE_0_255, + DRM_PIXEL_NORMALIZE_RANGE_MAX +}; + int drm_plane_create_color_properties(struct drm_plane *plane, u32 supported_encodings, u32 supported_ranges, enum drm_color_encoding default_encoding, enum drm_color_range default_range); +int drm_plane_create_pixel_normalize_range_property(struct drm_plane *plane, + u32 supported_ranges, + enum drm_pixel_normalize_range default_range); #endif diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 3701f56..11f5be4 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -130,6 +130,13 @@ struct drm_plane_state { uint16_t pixel_blend_mode; /** + * @pixel_normalize_range: + * The range to use for floating point pixel data normalization. See + * drm_plane_create_pixel_normalize_range_property() for more details. + */ + enum drm_pixel_normalize_range pixel_normalize_range; + + /** * @rotation: * Rotation of the plane. See drm_plane_create_rotation_property() for * more details. @@ -680,6 +687,13 @@ struct drm_plane { struct drm_property *blend_mode_property; /** + * @pixel_normalize_range_property: + * Optional "PIXEL_NORMALIZE_RANGE" property for this plane. See + * drm_plane_create_pixel_normalize_range_property(). + */ + struct drm_property *pixel_normalize_range_property; + + /** * @color_encoding_property: * * Optional "COLOR_ENCODING" enum property for specifying From patchwork Thu Nov 29 06:38:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kevin Strasser X-Patchwork-Id: 10704061 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7743813BF for ; Thu, 29 Nov 2018 06:38:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6940A2E57D for ; Thu, 29 Nov 2018 06:38:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5D5952EA51; Thu, 29 Nov 2018 06:38:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C25572E57D for ; Thu, 29 Nov 2018 06:38:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 92DA76E46C; Thu, 29 Nov 2018 06:38:16 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9814F6E468; Thu, 29 Nov 2018 06:38:14 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Nov 2018 22:38:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,293,1539673200"; d="scan'208";a="96604230" Received: from z170x-ud5.jf.intel.com ([10.54.75.40]) by orsmga008.jf.intel.com with ESMTP; 28 Nov 2018 22:38:14 -0800 From: Kevin Strasser To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property Date: Wed, 28 Nov 2018 22:38:13 -0800 Message-Id: <1543473493-30973-4-git-send-email-kevin.strasser@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543473493-30973-1-git-send-email-kevin.strasser@intel.com> References: <1543473493-30973-1-git-send-email-kevin.strasser@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Daniel Vetter , Uma Shankar Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP 64 bpp half float formats are supported on hdr planes only and are subject to the following restrictions: * 90/270 rotation not supported * Yf Tiling not supported * Frame Buffer Compression not supported * Color Keying not supported The behavior of pixel normalize with non-float formats is currently undefined. As such, the pixel normalize register is enabled iff the framebuffer contains floating point pixel data. Signed-off-by: Kevin Strasser Cc: Uma Shankar Cc: Shashank Sharma Cc: Ville Syrjälä Cc: David Airlie Cc: Daniel Vetter Cc: dri-devel@lists.freedesktop.org --- drivers/gpu/drm/i915/i915_reg.h | 15 ++++++- drivers/gpu/drm/i915/intel_display.c | 48 +++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 5 +++ drivers/gpu/drm/i915/intel_sprite.c | 82 +++++++++++++++++++++++++++++++++--- 4 files changed, 143 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 47baf2fe..871d293 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6563,6 +6563,10 @@ enum { #define _PLANE_KEYMAX_1_A 0x701a0 #define _PLANE_KEYMAX_2_A 0x702a0 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) +#define _PLANE_PIXEL_NORMALIZE_1_A 0x701a8 +#define _PLANE_PIXEL_NORMALIZE_2_A 0x702a8 +#define PLANE_PIXEL_NORMALIZE_ENABLE (1 << 31) +#define PLANE_PIXEL_NORMALIZE_FACTOR_MASK 0xffff #define _PLANE_AUX_DIST_1_A 0x701c0 #define _PLANE_AUX_DIST_2_A 0x702c0 #define _PLANE_AUX_OFFSET_1_A 0x701c4 @@ -6786,7 +6790,16 @@ enum { #define PLANE_COLOR_CTL(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) -#/* SKL new cursor registers */ +#define _PLANE_PIXEL_NORMALIZE_1_B 0x711a8 +#define _PLANE_PIXEL_NORMALIZE_2_B 0x712a8 +#define _PLANE_PIXEL_NORMALIZE_1(pipe) \ + _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B) +#define _PLANE_PIXEL_NORMALIZE_2(pipe) \ + _PIPE(pipe, _PLANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B) +#define PLANE_PIXEL_NORMALIZE(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_PIXEL_NORMALIZE_1(pipe), _PLANE_PIXEL_NORMALIZE_2(pipe)) + +/* SKL new cursor registers */ #define _CUR_BUF_CFG_A 0x7017c #define _CUR_BUF_CFG_B 0x7117c #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e9f4e22..cbacb4b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2618,6 +2618,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12; + case PLANE_CTL_FORMAT_XRGB_16161616F: + if (rgb_order) { + if (alpha) + return DRM_FORMAT_ABGR16161616H; + else + return DRM_FORMAT_XBGR16161616H; + } else { + if (alpha) + return DRM_FORMAT_ARGB16161616H; + else + return DRM_FORMAT_XRGB16161616H; + } default: case PLANE_CTL_FORMAT_XRGB_8888: if (rgb_order) { @@ -3505,6 +3517,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12; + case DRM_FORMAT_XBGR16161616H: + case DRM_FORMAT_ABGR16161616H: + return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX; + case DRM_FORMAT_XRGB16161616H: + case DRM_FORMAT_ARGB16161616H: + return PLANE_CTL_FORMAT_XRGB_16161616F; default: MISSING_CASE(pixel_format); } @@ -3680,6 +3698,32 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, return plane_color_ctl; } +u32 icl_plane_pixel_normalize(uint32_t pixel_format, + enum drm_pixel_normalize_range range) +{ + /* 1.0 in half float */ + u16 half_float_1 = 0x3c00; + /* 3.92E-3 in half float */ + u16 half_float_255 = 0x1c04; + + switch (pixel_format) { + case DRM_FORMAT_XRGB16161616H: + case DRM_FORMAT_XBGR16161616H: + case DRM_FORMAT_ARGB16161616H: + case DRM_FORMAT_ABGR16161616H: + switch (range) { + case DRM_PIXEL_NORMALIZE_RANGE_0_1: + return PLANE_PIXEL_NORMALIZE_ENABLE | half_float_1; + case DRM_PIXEL_NORMALIZE_RANGE_0_255: + return PLANE_PIXEL_NORMALIZE_ENABLE | half_float_255; + default: + return 0; + } + default: + return 0; + } +} + static int __intel_display_resume(struct drm_device *dev, struct drm_atomic_state *state, @@ -4998,6 +5042,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_XBGR16161616H: + case DRM_FORMAT_ABGR16161616H: + case DRM_FORMAT_XRGB16161616H: + case DRM_FORMAT_ARGB16161616H: break; default: DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a62d77b..a56b131 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -565,6 +565,9 @@ struct intel_plane_state { u32 slave; struct drm_intel_sprite_colorkey ckey; + + /* plane pixel normalize register */ + u32 pixel_normalize; }; struct intel_initial_plane_config { @@ -1738,6 +1741,8 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, u32 glk_color_ctl(const struct intel_plane_state *plane_state); u32 skl_plane_stride(const struct intel_plane_state *plane_state, int plane); +u32 icl_plane_pixel_normalize(uint32_t pixel_format, + enum drm_pixel_normalize_range range); int skl_check_plane_surface(struct intel_plane_state *plane_state); int i9xx_check_plane_surface(struct intel_plane_state *plane_state); int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index abe1938..9dea0b8 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -515,6 +515,10 @@ skl_program_plane(struct intel_plane *plane, if (fb->format->is_yuv && icl_is_hdr_plane(plane)) icl_program_input_csc_coeff(crtc_state, plane_state); + if (fb->format->is_fp && icl_is_hdr_plane(plane)) + I915_WRITE_FW(PLANE_PIXEL_NORMALIZE(pipe, plane_id), + plane_state->pixel_normalize); + I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax); I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk); @@ -1417,8 +1421,6 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, /* * 90/270 is not allowed with RGB64 16:16:16:16 and * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. - * TBD: Add RGB64 case once its added in supported format - * list. */ switch (fb->format->format) { case DRM_FORMAT_RGB565: @@ -1426,6 +1428,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, break; /* fall through */ case DRM_FORMAT_C8: + case DRM_FORMAT_XRGB16161616H: + case DRM_FORMAT_XBGR16161616H: + case DRM_FORMAT_ARGB16161616H: + case DRM_FORMAT_ABGR16161616H: DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n", drm_get_format_name(fb->format->format, &format_name)); @@ -1552,6 +1558,11 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, plane_state->color_ctl = glk_plane_color_ctl(crtc_state, plane_state); + if (icl_is_hdr_plane(plane)) + plane_state->pixel_normalize = + icl_plane_pixel_normalize(plane_state->base.fb->format->format, + plane_state->base.pixel_normalize_range); + return 0; } @@ -1741,6 +1752,45 @@ static const uint32_t skl_planar_formats[] = { DRM_FORMAT_NV12, }; +static const uint32_t icl_hdr_plane_formats[] = { + DRM_FORMAT_C8, + DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XRGB2101010, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_XRGB16161616H, + DRM_FORMAT_XBGR16161616H, + DRM_FORMAT_ARGB16161616H, + DRM_FORMAT_ABGR16161616H, + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, +}; + +static const uint32_t icl_hdr_planar_formats[] = { + DRM_FORMAT_C8, + DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XRGB2101010, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_XRGB16161616H, + DRM_FORMAT_XBGR16161616H, + DRM_FORMAT_ARGB16161616H, + DRM_FORMAT_ABGR16161616H, + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, + DRM_FORMAT_NV12, +}; + static const uint64_t skl_plane_format_modifiers_noccs[] = { I915_FORMAT_MOD_Yf_TILED, I915_FORMAT_MOD_Y_TILED, @@ -1884,6 +1934,10 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, return true; /* fall through */ case DRM_FORMAT_C8: + case DRM_FORMAT_XBGR16161616H: + case DRM_FORMAT_ABGR16161616H: + case DRM_FORMAT_XRGB16161616H: + case DRM_FORMAT_ARGB16161616H: if (modifier == DRM_FORMAT_MOD_LINEAR || modifier == I915_FORMAT_MOD_X_TILED || modifier == I915_FORMAT_MOD_Y_TILED) @@ -2020,11 +2074,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->update_slave = icl_update_slave; if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { - formats = skl_planar_formats; - num_formats = ARRAY_SIZE(skl_planar_formats); + if (icl_is_hdr_plane(plane)) { + formats = icl_hdr_planar_formats; + num_formats = ARRAY_SIZE(icl_hdr_planar_formats); + } else { + formats = skl_planar_formats; + num_formats = ARRAY_SIZE(skl_planar_formats); + } } else { - formats = skl_plane_formats; - num_formats = ARRAY_SIZE(skl_plane_formats); + if (icl_is_hdr_plane(plane)) { + formats = icl_hdr_plane_formats; + num_formats = ARRAY_SIZE(icl_hdr_plane_formats); + } else { + formats = skl_plane_formats; + num_formats = ARRAY_SIZE(skl_plane_formats); + } } plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); @@ -2074,6 +2138,12 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE)); + if (icl_is_hdr_plane(plane)) + drm_plane_create_pixel_normalize_range_property(&plane->base, + BIT(DRM_PIXEL_NORMALIZE_RANGE_0_1) | + BIT(DRM_PIXEL_NORMALIZE_RANGE_0_255), + DRM_PIXEL_NORMALIZE_RANGE_0_1); + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); return plane;