From patchwork Tue Jun 1 10:41:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF022C47093 for ; Tue, 1 Jun 2021 10:06:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 77B7F61370 for ; Tue, 1 Jun 2021 10:06:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 77B7F61370 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94CFE6E9D1; Tue, 1 Jun 2021 10:06:01 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8699C6E10C; Tue, 1 Jun 2021 10:05:57 +0000 (UTC) IronPort-SDR: 489OmspNXUE3zW91DZO/M7pD+jgdyzpL9IBlWTSlRqUnpPQBnvTQhTf9gfo2ff4LQpUUXJrI2Z KqgaHX8kZgxw== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197717" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197717" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:45 -0700 IronPort-SDR: PtDIQbeqtu0bSVmnBKiKN0F+wDHhYIv/eBAn7D7IHjwgaG/OfBI426FaE5K9vL055kuTiRpAvz HpmIheEvGYTw== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245154" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:41 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 1 Jun 2021 16:11:27 +0530 Message-Id: <20210601104135.29020-2-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/9] drm: Add gamma mode property X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a gamma mode property to enable various kind of gamma modes supported by platforms like: Interpolated, Split, Multi Segmented, Logarithmic etc. Userspace can get this property and should be able to get the platform capabilities wrt various gamma modes possible and the possible ranges. It can select one of the modes exposed as blob_id as an enum and set the respective mode. It can then create the LUT and send it to driver using already available GAMMA_LUT property as blob. Note: This is based on design by Ville and is being carried forward based on his original idea. Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_atomic_uapi.c | 5 +++ drivers/gpu/drm/drm_color_mgmt.c | 75 +++++++++++++++++++++++++++++++ include/drm/drm_color_mgmt.h | 8 ++++ include/drm/drm_crtc.h | 14 ++++++ include/uapi/drm/drm_mode.h | 43 ++++++++++++++++++ 5 files changed, 145 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 438e9585b225..a5470a0ebbe6 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -471,6 +471,9 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == crtc->gamma_mode_property) { + state->gamma_mode = val; + state->color_mgmt_changed |= true; } else if (property == config->prop_out_fence_ptr) { s32 __user *fence_ptr = u64_to_user_ptr(val); @@ -510,6 +513,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = (state->mode_blob) ? state->mode_blob->base.id : 0; else if (property == config->prop_vrr_enabled) *val = state->vrr_enabled; + else if (property == crtc->gamma_mode_property) + *val = state->gamma_mode; else if (property == config->degamma_lut_property) *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0; else if (property == config->ctm_property) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index bb14f488c8f6..766d0fd14daa 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -187,6 +187,81 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, } EXPORT_SYMBOL(drm_crtc_enable_color_mgmt); +void drm_crtc_attach_gamma_mode_property(struct drm_crtc *crtc) +{ + if (!crtc->gamma_mode_property) + return; + + drm_object_attach_property(&crtc->base, + crtc->gamma_mode_property, 0); +} +EXPORT_SYMBOL(drm_crtc_attach_gamma_mode_property); + +int drm_color_create_gamma_mode_property(struct drm_crtc *crtc, + int num_values) +{ + struct drm_property *prop; + + prop = drm_property_create(crtc->dev, + DRM_MODE_PROP_ENUM, + "GAMMA_MODE", num_values); + if (!prop) + return -ENOMEM; + + crtc->gamma_mode_property = prop; + + return 0; +} +EXPORT_SYMBOL(drm_color_create_gamma_mode_property); + +int drm_color_add_gamma_mode_range(struct drm_crtc *crtc, + const char *name, + const struct drm_color_lut_range *ranges, + size_t length) +{ + struct drm_property_blob *blob; + struct drm_property *prop; + int num_ranges = length / sizeof(ranges[0]); + int i, ret, num_types_0; + + prop = crtc->gamma_mode_property; + if (!prop) + return -EINVAL; + + if (length == 0 && name) + return drm_property_add_enum(prop, 0, name); + + if (WARN_ON(length == 0 || length % sizeof(ranges[0]) != 0)) + return -EINVAL; + + num_types_0 = hweight8(ranges[0].flags & (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA)); + if (num_types_0 == 0) + return -EINVAL; + + for (i = 1; i < num_ranges; i++) { + int num_types = hweight8(ranges[i].flags & (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA)); + + /* either all ranges have DEGAMMA|GAMMA or none have it */ + if (num_types_0 != num_types) + return -EINVAL; + } + + blob = drm_property_create_blob(crtc->dev, length, ranges); + if (IS_ERR(blob)) + return PTR_ERR(blob); + + ret = drm_property_add_enum(prop, blob->base.id, name); + if (ret) { + drm_property_blob_put(blob); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_color_add_gamma_mode_range); + /** * drm_mode_crtc_set_gamma_size - set the gamma table size * @crtc: CRTC to set the gamma table size for diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 81c298488b0c..db68f42f6d12 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -74,6 +74,14 @@ static inline int drm_color_lut_size(const struct drm_property_blob *blob) return blob->length / sizeof(struct drm_color_lut); } +int drm_color_create_gamma_mode_property(struct drm_crtc *crtc, + int num_values); +void drm_crtc_attach_gamma_mode_property(struct drm_crtc *crtc); +int drm_color_add_gamma_mode_range(struct drm_crtc *crtc, + const char *name, + const struct drm_color_lut_range *ranges, + size_t length); + enum drm_color_encoding { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_BT709, diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 13eeba2a750a..b1eead03ebe8 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -262,6 +262,13 @@ struct drm_crtc_state { */ struct drm_property_blob *mode_blob; + /** + * @gamma_mode: This is a blob_id and exposes the platform capabilities + * wrt to various gamma modes and the respective lut ranges. This also + * helps user select a gamma mode amongst the supported ones. + */ + u32 gamma_mode; + /** * @degamma_lut: * @@ -1096,6 +1103,13 @@ struct drm_crtc { */ struct drm_property *scaling_filter_property; + /** + * @gamma_mode_property: Optional CRTC property to enumerate and + * select the mode of the crtc gamma/degmama LUTs. This also exposes + * the lut ranges of the various supported gamma modes to userspace. + */ + struct drm_property *gamma_mode_property; + /** * @state: * diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 9b6722d45f36..d7758d351936 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -819,6 +819,49 @@ struct hdr_output_metadata { }; }; +/* + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT + * can be used for either purpose, but not simultaneously. To expose + * modes that support gamma and degamma simultaneously the gamma mode + * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA + * ranges. + */ +/* LUT is for gamma (after CTM) */ +#define DRM_MODE_LUT_GAMMA BIT(0) +/* LUT is for degamma (before CTM) */ +#define DRM_MODE_LUT_DEGAMMA BIT(1) +/* linearly interpolate between the points */ +#define DRM_MODE_LUT_INTERPOLATE BIT(2) +/* + * the last value of the previous range is the + * first value of the current range. + */ +#define DRM_MODE_LUT_REUSE_LAST BIT(3) +/* the curve must be non-decreasing */ +#define DRM_MODE_LUT_NON_DECREASING BIT(4) +/* the curve is reflected across origin for negative inputs */ +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5) +/* the same curve (red) is used for blue and green channels as well */ +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6) + +struct drm_color_lut_range { + /* DRM_MODE_LUT_* */ + __u32 flags; + /* number of points on the curve */ + __u16 count; + /* input/output bits per component */ + __u8 input_bpc, output_bpc; + /* input start/end values */ + __s32 start, end; + /* output min/max values */ + __s32 min, max; +}; + +enum lut_type { + LUT_TYPE_DEGAMMA = 0, + LUT_TYPE_GAMMA = 1, +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 From patchwork Tue Jun 1 10:41:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 597A0C4708F for ; Tue, 1 Jun 2021 10:06:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1FAB861396 for ; Tue, 1 Jun 2021 10:06:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1FAB861396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 799946E9C5; Tue, 1 Jun 2021 10:06:00 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 704646E145; Tue, 1 Jun 2021 10:05:58 +0000 (UTC) IronPort-SDR: HP/T8Ud1N9XA9cmXUcbOBVPe96i7ASXQ1SJIvGDhsMBygsMuzGkgmODatonyQytLqhZU1yA8Ot VSbxvXebllKg== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197723" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197723" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:46 -0700 IronPort-SDR: UJ+hSyXM65DdjpL+RKk5vdJ9eVPZ2rAfQMAcNuAMMYlzT4ti+QzrcA0qhYmJfF59gCP++TZ21x oJ8PPsZgNIqg== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245195" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:44 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 1 Jun 2021 16:11:28 +0530 Message-Id: <20210601104135.29020-3-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/9] drm/i915/xelpd: Define color lut range structure X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This defines the color lut ranges for logarithmic gamma which is being introduced from XE_LPD onwards. Signed-off-by: Uma Shankar Signed-off-by: Bhanuprakash Modem --- drivers/gpu/drm/i915/display/intel_color.c | 250 ++++++++++++++++++++- 1 file changed, 246 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index dab892d2251b..0b59d8a89761 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -2093,6 +2093,238 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state) } } +#define D13_GAMMA_CAPABILITY_FLAG (DRM_MODE_LUT_GAMMA | \ + DRM_MODE_LUT_REFLECT_NEGATIVE | \ + DRM_MODE_LUT_INTERPOLATE | \ + DRM_MODE_LUT_NON_DECREASING) + /* FIXME input bpc? */ +static const struct drm_color_lut_range d13_logarithmic_gamma[] = { + /* segment 0 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = 0, + .min = 0, .max = 0, + }, + /* segment 1 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = (1 << 0), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 2 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 2, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 0), .end = (1 << 1), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 3 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 2, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 1), .end = (1 << 2), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 4 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 2, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 2), .end = (1 << 3), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 5 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 2, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 3), .end = (1 << 4), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 6 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 4, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 4), .end = (1 << 5), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 7 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 4, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 5), .end = (1 << 6), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 8 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 4, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 6), .end = (1 << 7), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 9 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 8, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 7), .end = (1 << 8), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 10 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 8, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 8), .end = (1 << 9), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 11 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 8, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 9), .end = (1 << 10), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 12 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 16, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 10), .end = (1 << 11), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 13 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 16, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 11), .end = (1 << 12), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 14 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 16, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 12), .end = (1 << 13), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 15 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 13), .end = (1 << 14), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 16 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 14), .end = (1 << 15), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 17 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 64, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 15), .end = (1 << 16), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 18 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 64, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 16), .end = (1 << 17), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 19 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 64, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 17), .end = (1 << 18), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 20 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 18), .end = (1 << 19), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 21 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 19), .end = (1 << 20), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 22 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 20), .end = (1 << 21), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 23 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 21), .end = (1 << 22), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 24 */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG, + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 22), .end = (1 << 23), + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 3 aka. coarse segment / PAL_GC_MAX */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG | DRM_MODE_LUT_REUSE_LAST, + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 24), .end = (3 << 24), + .min = 0, .max = 1 << 16, + }, + /* PAL_EXT_GC_MAX */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG | DRM_MODE_LUT_REUSE_LAST, + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = (3 << 24), .end = (7 << 24), + .min = 0, .max = (8 << 16) - 1, + }, + /* PAL_EXT2_GC_MAX */ + { + .flags = D13_GAMMA_CAPABILITY_FLAG | DRM_MODE_LUT_REUSE_LAST, + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = (7 << 24), .end = (7 << 24), + .min = 0, .max = (8 << 16) - 1, + }, +}; + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -2118,14 +2350,24 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.read_luts = i9xx_read_luts; } } else { - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(dev_priv) >= 13) { + dev_priv->display.color_check = icl_color_check; + drm_color_create_gamma_mode_property(&crtc->base, 2); + drm_color_add_gamma_mode_range(&crtc->base, + "no gamma", NULL, 0); + drm_color_add_gamma_mode_range(&crtc->base, + "logarithmic gamma", + d13_logarithmic_gamma, + sizeof(d13_logarithmic_gamma)); + } else if (DISPLAY_VER(dev_priv) >= 11) { dev_priv->display.color_check = icl_color_check; - else if (DISPLAY_VER(dev_priv) >= 10) + } else if (DISPLAY_VER(dev_priv) >= 10) { dev_priv->display.color_check = glk_color_check; - else if (DISPLAY_VER(dev_priv) >= 7) + } else if (DISPLAY_VER(dev_priv) >= 7) { dev_priv->display.color_check = ivb_color_check; - else + } else { dev_priv->display.color_check = ilk_color_check; + } if (DISPLAY_VER(dev_priv) >= 9) dev_priv->display.color_commit = skl_color_commit; From patchwork Tue Jun 1 10:41:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 018BBC47080 for ; Tue, 1 Jun 2021 10:06:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6F706136E for ; Tue, 1 Jun 2021 10:05:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A6F706136E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D83F6E9C2; Tue, 1 Jun 2021 10:05:59 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id D43E06E145; Tue, 1 Jun 2021 10:05:58 +0000 (UTC) IronPort-SDR: 9kBQMoGWMvy9ggOCZtgGvcPYZ3IM0obFd6D+5VbfKXNipwemN1YSkCMEGPDYRT5vFz8lTiSrkh vrU01RSeME2w== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197732" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197732" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:48 -0700 IronPort-SDR: 6PQU+PwHFltX5JTeJFj8EnZ+RfdOQfL4+MC7GRVEfYcp7WdHzGPjI9bGc9/ORtzCRy0NqBbcsk BE3t59QdLVcQ== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245213" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:46 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 1 Jun 2021 16:11:29 +0530 Message-Id: <20210601104135.29020-4-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/9] drm/i915/xelpd: Add support for Logarithmic gamma mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" XE_LPD hardware introduced a new gamma mode i.e, Logarithmic gamma mode. Added support for the same. Signed-off-by: Uma Shankar Signed-off-by: Bhanuprakash Modem --- drivers/gpu/drm/i915/display/intel_color.c | 111 ++++++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 1 + include/drm/drm_crtc.h | 3 + 3 files changed, 110 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 0b59d8a89761..12cacd3aeead 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -75,6 +75,21 @@ #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255) +#define GAMMA_MODE_LEGACY_PALETTE_8BIT BIT(0) +#define GAMMA_MODE_PRECISION_PALETTE_10BIT BIT(1) +#define GAMMA_MODE_INTERPOLATED_12BIT BIT(2) +#define GAMMA_MODE_MULTI_SEGMENTED_12BIT BIT(3) +#define GAMMA_MODE_SPLIT_12BIT BIT(4) +#define GAMMA_MODE_LOGARITHMIC_12BIT BIT(5) /* D13+ */ + +#define INTEL_GAMMA_MODE_MASK (\ + GAMMA_MODE_LEGACY_PALETTE_8BIT | \ + GAMMA_MODE_PRECISION_PALETTE_10BIT | \ + GAMMA_MODE_INTERPOLATED_12BIT | \ + GAMMA_MODE_MULTI_SEGMENTED_12BIT | \ + GAMMA_MODE_SPLIT_12BIT \ + GAMMA_MODE_LOGARITHMIC_12BIT) + /* Nop pre/post offsets */ static const u16 ilk_csc_off_zero[3] = {}; @@ -929,12 +944,20 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state, const struct drm_color_lut *color) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); enum pipe pipe = crtc->pipe; - /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ - intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); - intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); - intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); + if (DISPLAY_VER(i915) >= 13) { + /* MAx val from UAPI is 16bit only, so setting fixed for GC max */ + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), 1 << 16); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), 1 << 16); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), 1 << 16); + } else { + /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); + } } static void @@ -1585,6 +1608,9 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) if (!crtc_state->hw.gamma_lut || crtc_state_is_legacy_gamma(crtc_state)) gamma_mode |= GAMMA_MODE_MODE_8BIT; + else if (crtc_state->uapi.gamma_mode_type == + GAMMA_MODE_LOGARITHMIC_12BIT) + gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC; else gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; @@ -1607,12 +1633,33 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) static int icl_color_check(struct intel_crtc_state *crtc_state) { + struct drm_device *dev = crtc_state->uapi.crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_property *property = crtc_state->uapi.crtc->gamma_mode_property; + struct drm_property_enum *prop_enum; + u32 index = 0; int ret; ret = check_luts(crtc_state); if (ret) return ret; + if (DISPLAY_VER(dev_priv) >= 13) { + list_for_each_entry(prop_enum, &property->enum_list, head) { + if (prop_enum->value == crtc_state->uapi.gamma_mode) { + if (!strcmp(prop_enum->name, + "logarithmic gamma")) { + crtc_state->uapi.gamma_mode_type = + GAMMA_MODE_LOGARITHMIC_12BIT; + drm_dbg_kms(dev, + "logarithmic gamma enabled\n"); + } + break; + } + index++; + } + } + crtc_state->gamma_mode = icl_gamma_mode(crtc_state); crtc_state->csc_mode = icl_csc_mode(crtc_state); @@ -2325,6 +2372,58 @@ static const struct drm_color_lut_range d13_logarithmic_gamma[] = { }, }; +static void +d13_program_logarithmic_gamma_lut(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_property_blob *blob = crtc_state->hw.gamma_lut; + const u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + const struct drm_color_lut *lut; + enum pipe pipe = crtc->pipe; + u32 i; + + if (!blob || !blob->data) + return; + + lut = blob->data; + intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT); + + for (i = 0; i < lut_size - 3; i++) { + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), + ilk_lut_12p4_ldw(&lut[i])); + intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), + ilk_lut_12p4_udw(&lut[i])); + } + + icl_load_gcmax(crtc_state, &lut[i]); + ivb_load_lut_ext_max(crtc_state); +} + +static void d13_load_luts(const struct intel_crtc_state *crtc_state) +{ + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if (crtc_state->hw.degamma_lut) + glk_load_degamma_lut(crtc_state); + + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { + case GAMMA_MODE_MODE_8BIT: + ilk_load_lut_8(crtc, gamma_lut); + break; + case GAMMA_MODE_MODE_12BIT_LOGARITHMIC: + d13_program_logarithmic_gamma_lut(crtc_state); + break; + default: + bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); + ivb_load_lut_ext_max(crtc_state); + } + + intel_dsb_commit(crtc_state); +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -2376,7 +2475,9 @@ void intel_color_init(struct intel_crtc *crtc) else dev_priv->display.color_commit = ilk_color_commit; - if (DISPLAY_VER(dev_priv) >= 11) { + if (DISPLAY_VER(dev_priv) >= 13) { + dev_priv->display.load_luts = d13_load_luts; + } else if (DISPLAY_VER(dev_priv) >= 11) { dev_priv->display.load_luts = icl_load_luts; dev_priv->display.read_luts = icl_read_luts; } else if (DISPLAY_VER(dev_priv) == 10) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 24307c49085f..957f97edf035 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7749,6 +7749,7 @@ enum { #define GAMMA_MODE_MODE_12BIT (2 << 0) #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ +#define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */ /* DMC */ #define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4) diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index b1eead03ebe8..5a594f134a81 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -269,6 +269,9 @@ struct drm_crtc_state { */ u32 gamma_mode; + /** Gamma mode type programmed on the pipe */ + u32 gamma_mode_type; + /** * @degamma_lut: * From patchwork Tue Jun 1 10:41:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE648C47080 for ; Tue, 1 Jun 2021 10:06:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC2D36136E for ; Tue, 1 Jun 2021 10:06:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BC2D36136E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 263C26E9CC; Tue, 1 Jun 2021 10:06:01 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F0F86E10C; Tue, 1 Jun 2021 10:05:59 +0000 (UTC) IronPort-SDR: ZThiIH8k2pzsQtz9n2tFX2W9HahqhA6uhuxmUjYv4lNqYmrR70vU5f8LEp0iHapI8RFCgwbdf9 B8JcYwGTmY7w== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197737" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197737" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:50 -0700 IronPort-SDR: Yy3cKuJhJeoRwpn+rPKX20DUCPJgiHsKDtSxlPY7v9JQttzU1wxeF7rkhHkxP1JDPdsDGmPiJN SMmxcFoqZksQ== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245225" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:48 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 1 Jun 2021 16:11:30 +0530 Message-Id: <20210601104135.29020-5-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/9] drm/i915/xelpd: Attach gamma mode property X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Attach the gamma mode property to allow userspace set the gamma mode and provide the luts for the same. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 12cacd3aeead..cae96fbec1a7 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -2458,6 +2458,7 @@ void intel_color_init(struct intel_crtc *crtc) "logarithmic gamma", d13_logarithmic_gamma, sizeof(d13_logarithmic_gamma)); + drm_crtc_attach_gamma_mode_property(&crtc->base); } else if (DISPLAY_VER(dev_priv) >= 11) { dev_priv->display.color_check = icl_color_check; } else if (DISPLAY_VER(dev_priv) >= 10) { From patchwork Tue Jun 1 10:41:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA49DC47080 for ; Tue, 1 Jun 2021 10:06:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7717B6136E for ; Tue, 1 Jun 2021 10:06:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7717B6136E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B6A46E9DC; Tue, 1 Jun 2021 10:06:03 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2FC116E145; Tue, 1 Jun 2021 10:05:59 +0000 (UTC) IronPort-SDR: 5V1DZD4/79WrE0U+qZPU/pD2aQPuMXjB6986f4fnUr9vfehJ/iB2y54o3v6B/8E+yM7Gh2w84g HfjTxtlq2IPg== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197744" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197744" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:52 -0700 IronPort-SDR: wbEzqGlcbpVKa76dE9z4+w5pw/SjahScsbqaoAnNSI0sRFMXPF9d7jiRom/J2TNrXLMHwll+3d EgZf+HZHdFMA== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245238" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:50 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 1 Jun 2021 16:11:31 +0530 Message-Id: <20210601104135.29020-6-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/9] drm: Add Client Cap for advance gamma mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Introduced a client cap for advance cap mode capability. Userspace should set this to get to be able to use the new gamma_mode property. If this is not set, driver will work in legacy mode. Note: This is suggested by Ville and based on his idea, the new gamma mode handling is designed. Signed-off-by: Uma Shankar Reported-by: kernel test robot --- drivers/gpu/drm/drm_atomic_uapi.c | 3 +++ drivers/gpu/drm/drm_ioctl.c | 5 +++++ include/drm/drm_atomic.h | 1 + include/drm/drm_crtc.h | 8 ++++++++ include/drm/drm_file.h | 8 ++++++++ include/uapi/drm/drm.h | 8 ++++++++ 6 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index a5470a0ebbe6..7ee35bc14455 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -1036,6 +1036,8 @@ int drm_atomic_set_property(struct drm_atomic_state *state, break; } + crtc_state->advance_gamma_mode_active = + state->advance_gamma_mode_active; ret = drm_atomic_crtc_set_property(crtc, crtc_state, prop, prop_value); break; @@ -1372,6 +1374,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); state->acquire_ctx = &ctx; state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET); + state->advance_gamma_mode_active = file_priv->advance_gamma_mode_active; retry: copied_objs = 0; diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 53d314103a37..d51f72213882 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -361,6 +361,11 @@ drm_setclientcap(struct drm_device *dev, void *data, struct drm_file *file_priv) return -EINVAL; file_priv->writeback_connectors = req->value; break; + case DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES: + if (req->value > 1) + return -EINVAL; + file_priv->advance_gamma_mode_active = req->value; + break; default: return -EINVAL; } diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index ac5a28eff2c8..5a398a249c80 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -379,6 +379,7 @@ struct drm_atomic_state { * states. */ bool duplicated : 1; + bool advance_gamma_mode_active : 1; struct __drm_planes_state *planes; struct __drm_crtcs_state *crtcs; int num_connector; diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 5a594f134a81..f4339fbad086 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -170,6 +170,11 @@ struct drm_crtc_state { */ bool color_mgmt_changed : 1; + /** + * This is to indicate advance gamma mode support + */ + bool advance_gamma_mode_active : 1; + /** * @no_vblank: * @@ -1036,6 +1041,9 @@ struct drm_crtc { */ bool enabled; + /** To handle advance gamma mode support */ + bool advance_gamma_mode_active : 1; + /** * @mode: * diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h index b81b3bfb08c8..4af3e1a2a158 100644 --- a/include/drm/drm_file.h +++ b/include/drm/drm_file.h @@ -201,6 +201,14 @@ struct drm_file { */ bool writeback_connectors; + /** + * This is to enable advance gamma modes using + * gamma_mode property + * + * True if client understands advance gamma + */ + bool advance_gamma_mode_active : 1; + /** * @was_master: * diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 67b94bc3c885..661efdf0c969 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -816,6 +816,14 @@ struct drm_get_cap { */ #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 +/** + * Add support for advance gamma mode UAPI + * If set to 1, DRM will enable advance gamma mode + * UAPI to process the gamma mode based on extended + * range and segments. + */ +#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6 + /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct drm_set_client_cap { __u64 capability; From patchwork Tue Jun 1 10:41:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36C9FC47092 for ; Tue, 1 Jun 2021 10:06:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F315A61370 for ; Tue, 1 Jun 2021 10:06:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F315A61370 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D956F6E9C4; Tue, 1 Jun 2021 10:06:00 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C4166E9C3; Tue, 1 Jun 2021 10:05:59 +0000 (UTC) IronPort-SDR: cgztEJslFxBBWpUDUkA+PSxQDynY9ofskMBfvxPtTATzLzRp7KiK0Mg5eDen/fyxc63pibDBs1 OgLzZI0e2Bhg== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197753" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197753" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:54 -0700 IronPort-SDR: o76rtFl+KRO2SrF+2YJbZSX0yvpPsFylG52BqFIM1OwS9+TTVkb5i8hp/fMqNIJoBP1RfTiQrd wM/+e7dDuMDQ== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245243" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:53 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 1 Jun 2021 16:11:32 +0530 Message-Id: <20210601104135.29020-7-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/9] drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Only Enable Logarithmic Gamma if client caps for advance gamma mode is enabled. Fallback to 10bit gamma in case its not supported. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index cae96fbec1a7..18b51b9cc2aa 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1606,13 +1606,17 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) gamma_mode |= POST_CSC_GAMMA_ENABLE; if (!crtc_state->hw.gamma_lut || - crtc_state_is_legacy_gamma(crtc_state)) + crtc_state_is_legacy_gamma(crtc_state)) { gamma_mode |= GAMMA_MODE_MODE_8BIT; - else if (crtc_state->uapi.gamma_mode_type == - GAMMA_MODE_LOGARITHMIC_12BIT) - gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC; - else + } else if (crtc_state->uapi.gamma_mode_type == + GAMMA_MODE_LOGARITHMIC_12BIT) { + if (crtc_state->uapi.advance_gamma_mode_active) + gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC; + else + gamma_mode |= GAMMA_MODE_MODE_10BIT; + } else { gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED; + } return gamma_mode; } From patchwork Tue Jun 1 10:41:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C348C47093 for ; Tue, 1 Jun 2021 10:06:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 019D16136E for ; Tue, 1 Jun 2021 10:06:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 019D16136E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 391036E9CB; Tue, 1 Jun 2021 10:06:04 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id A83206E9D7; Tue, 1 Jun 2021 10:06:02 +0000 (UTC) IronPort-SDR: Ghd2cIc984dFDds5nR22f4FMTmBnJCca4/G3XLFKqr+jgErXyG0TABeS3su+gF3p0BbslNj2Gd E3jkYdUbD+kw== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197763" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197763" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:56 -0700 IronPort-SDR: NlQfD4GCOmcyzwP63hqSXSlCFoAlcIY87pm5X07CUKynuXkx9mQ3PxRAI2MUUur7gb2SvYjclh t1+Ddb2KMmEg== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245248" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:55 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 1 Jun 2021 16:11:33 +0530 Message-Id: <20210601104135.29020-8-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 7/9] drm/i915/xelpd: Enable Pipe Degamma X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable Pipe Degamma for XE_LPD. Extend the legacy implementation to incorparate the extended lut size for XE_LPD. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 18b51b9cc2aa..a8b771f22880 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -829,6 +829,12 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data; + u32 extended_lut_size = 0; + + if (DISPLAY_VER(dev_priv) >= 13) + extended_lut_size = 131; + else + extended_lut_size = 35; /* * When setting the auto-increment bit, the hardware seems to @@ -841,8 +847,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) for (i = 0; i < lut_size; i++) { /* - * First 33 entries represent range from 0 to 1.0 - * 34th and 35th entry will represent extended range + * First lut_size entries represent range from 0 to 1.0 + * 3 additional lut entries will represent extended range * inputs 3.0 and 7.0 respectively, currently clamped * at 1.0. Since the precision is 16bit, the user * value can be directly filled to register. @@ -858,7 +864,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) } /* Clamp values > 1.0. */ - while (i++ < 35) + while (i++ < extended_lut_size) intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); From patchwork Tue Jun 1 10:41:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D02C6C4708F for ; Tue, 1 Jun 2021 10:06:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9974C61370 for ; Tue, 1 Jun 2021 10:06:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9974C61370 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1070C6E9D5; Tue, 1 Jun 2021 10:06:05 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id E31BE6E9DA; Tue, 1 Jun 2021 10:06:02 +0000 (UTC) IronPort-SDR: LFg9r9PuQwLOda7IX8iCrNt5biS2BqYO1w2ApEx/sMz7MkKdADiFSu9ckkTS+C61ZUnvjb7nIO SI6Lsi7aUFcQ== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197772" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197772" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:59 -0700 IronPort-SDR: QJ1haKtiQalouPhG+W+lP8CtlmCWrlJg90tGqRukGqQfRDxGqS37CWtgxyDENCBe8U0Ab55dIN zQr/PLuVAcVw== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245266" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:57 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 1 Jun 2021 16:11:34 +0530 Message-Id: <20210601104135.29020-9-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 8/9] drm/i915/xelpd: Add Pipe Color Lut caps to platform config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for extended range. It has 511 entries for gamma with additional 2 entries for extended range. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_pci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 97c98f4fb265..844d08e37ec5 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -947,7 +947,8 @@ static const struct intel_device_info adl_s_info = { .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \ .dbuf.size = 4096, \ - .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4) + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), \ + .color = { .degamma_lut_size = 128, .gamma_lut_size = 513 } static const struct intel_device_info adl_p_info = { GEN12_FEATURES, From patchwork Tue Jun 1 10:41:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38373C47093 for ; Tue, 1 Jun 2021 10:06:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 04B9661370 for ; Tue, 1 Jun 2021 10:06:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 04B9661370 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE7AD6E9DA; Tue, 1 Jun 2021 10:06:05 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1638C6E9DE; Tue, 1 Jun 2021 10:06:03 +0000 (UTC) IronPort-SDR: 3bGnSxKDRG8wRYpbL8Gr57YHiDcLRpB6BscGK4tPCsx64GSAOt6P0m4r2PobgWixVr1vSAcBJD pE69eoZjK3zA== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197776" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197776" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:06:01 -0700 IronPort-SDR: nAMCoBFdy5aRuUvxZGNXIUYlF7/TEDzuXVuVdXHIkhqzlAbPQPRmcwM2u0+Ej9pCok3rF6az2v GHHo6Gw2vBVA== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245279" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:59 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 1 Jun 2021 16:11:35 +0530 Message-Id: <20210601104135.29020-10-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 9/9] drm/i915/xelpd: Enable XE_LPD Gamma Lut readout X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable support for Logarithmic gamma readout for XE_LPD. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 72 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++ 2 files changed, 78 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index a8b771f22880..1238fe05b358 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -486,6 +486,17 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw); } +static void d13_lut_logarithmic_pack(struct drm_color_lut *entry, + u32 ldw, u32 udw) +{ + entry->red = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_LDW_MASK, ldw); + entry->green = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK, ldw); + entry->blue = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK, ldw); +} + static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -2434,6 +2445,66 @@ static void d13_load_luts(const struct intel_crtc_state *crtc_state) intel_dsb_commit(crtc_state); } +static struct drm_property_blob * +d13_read_lut_logarithmic(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *lut; + u32 gamma_max_val = 0xFFFF; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(struct drm_color_lut) * lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + lut = blob->data; + + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT); + + for (i = 0; i < lut_size - 3; i++) { + u32 ldw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); + u32 udw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); + + d13_lut_logarithmic_pack(&lut[i], ldw, udw); + } + + /* All the extended ranges are now limited to last value of 1.0 */ + while (i < lut_size) { + lut[i].red = gamma_max_val; + lut[i].green = gamma_max_val; + lut[i].blue = gamma_max_val; + i++; + }; + + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); + + return blob; +} + +static void d13_read_luts(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) + return; + + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { + case GAMMA_MODE_MODE_8BIT: + crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); + break; + case GAMMA_MODE_MODE_12BIT_LOGARITHMIC: + crtc_state->hw.gamma_lut = d13_read_lut_logarithmic(crtc); + break; + default: + crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); + } +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -2488,6 +2559,7 @@ void intel_color_init(struct intel_crtc *crtc) if (DISPLAY_VER(dev_priv) >= 13) { dev_priv->display.load_luts = d13_load_luts; + dev_priv->display.read_luts = d13_read_luts; } else if (DISPLAY_VER(dev_priv) >= 11) { dev_priv->display.load_luts = icl_load_luts; dev_priv->display.read_luts = icl_read_luts; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 957f97edf035..dc10b5e2ff3c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7750,6 +7750,12 @@ enum { #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ #define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */ +#define PAL_PREC_LOGARITHMIC_RED_LDW_MASK REG_GENMASK(29, 24) +#define PAL_PREC_LOGARITHMIC_RED_UDW_MASK REG_GENMASK(29, 20) +#define PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK REG_GENMASK(19, 14) +#define PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK REG_GENMASK(19, 10) +#define PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK REG_GENMASK(9, 4) +#define PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK REG_GENMASK(9, 0) /* DMC */ #define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)