From patchwork Tue Jun 1 10:51:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C2D3C47092 for ; Tue, 1 Jun 2021 10:16:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E6C486139A for ; Tue, 1 Jun 2021 10:16:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E6C486139A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C47CF6E9E5; Tue, 1 Jun 2021 10:16:04 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7ED826E9D9; Tue, 1 Jun 2021 10:16:02 +0000 (UTC) IronPort-SDR: fo1EUJ8tZEv8pPlkLRuhR6Kvrzwbf+nit2c1FA5fVpWietKMatp671JFWAgBdrEroXrRLCz/fI qS5n35FE4Ubw== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203549926" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203549926" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:02 -0700 IronPort-SDR: 0Rf5dWhPW+IB4k537YuHI9O2DtFjlIGtNGgXCe2JkuSLDSAF+Ma3V56nF40US7+rl5lMffK3yJ 8t556lwV2Utw== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431153" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:00 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 01/21] drm: Add Enhanced Gamma and color lut range attributes Date: Tue, 1 Jun 2021 16:21:58 +0530 Message-Id: <20210601105218.29185-2-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Existing LUT precision structure is having only 16 bit precision. This is not enough for upcoming enhanced hardwares and advance usecases like HDR processing. Hence added a new structure with 32 bit precision values. This also defines a new structure to define color lut ranges, along with related macro definitions and enums. This will help describe multi segmented lut ranges in the hardware. Signed-off-by: Uma Shankar --- include/uapi/drm/drm_mode.h | 58 +++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 9b6722d45f36..d0ce48d2e732 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -819,6 +819,64 @@ struct hdr_output_metadata { }; }; +/* + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT + * can be used for either purpose, but not simultaneously. To expose + * modes that support gamma and degamma simultaneously the gamma mode + * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA + * ranges. + */ +/* LUT is for gamma (after CTM) */ +#define DRM_MODE_LUT_GAMMA BIT(0) +/* LUT is for degamma (before CTM) */ +#define DRM_MODE_LUT_DEGAMMA BIT(1) +/* linearly interpolate between the points */ +#define DRM_MODE_LUT_INTERPOLATE BIT(2) +/* + * the last value of the previous range is the + * first value of the current range. + */ +#define DRM_MODE_LUT_REUSE_LAST BIT(3) +/* the curve must be non-decreasing */ +#define DRM_MODE_LUT_NON_DECREASING BIT(4) +/* the curve is reflected across origin for negative inputs */ +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5) +/* the same curve (red) is used for blue and green channels as well */ +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6) + +struct drm_color_lut_range { + /* DRM_MODE_LUT_* */ + __u32 flags; + /* number of points on the curve */ + __u16 count; + /* input/output bits per component */ + __u8 input_bpc, output_bpc; + /* input start/end values */ + __s32 start, end; + /* output min/max values */ + __s32 min, max; +}; + +enum lut_type { + LUT_TYPE_DEGAMMA = 0, + LUT_TYPE_GAMMA = 1, +}; + +/* + * Creating 64 bit palette entries for better data + * precision. This will be required for HDR and + * similar color processing usecases. + */ +struct drm_color_lut_ext { + /* + * Data is U32.32 fixed point format. + */ + __u64 red; + __u64 green; + __u64 blue; + __u64 reserved; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 From patchwork Tue Jun 1 10:51:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 737D0C47092 for ; Tue, 1 Jun 2021 10:16:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3CC2461396 for ; Tue, 1 Jun 2021 10:16:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3CC2461396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA4396E9E2; Tue, 1 Jun 2021 10:16:08 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 45B7B6E9E2; Tue, 1 Jun 2021 10:16:07 +0000 (UTC) IronPort-SDR: KaKWTNai1EsW4f2MZcjRu8NF0kUEsj4xyyHyB6uYpGRRUua4vEJzGa8PQEEz3TcyodOYxmJGhQ FnRXkKolxLBA== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203549941" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203549941" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:05 -0700 IronPort-SDR: SPuHKXFALvjt1qi9Xsm04w4swSPXTFfDLCQ+36Oh/xSVFW1cLl9Cg9GYNUXM59ZY/hSOs6J1my 9tYfluHGhF4A== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431171" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:02 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 02/21] drm: Add Plane Degamma Mode property Date: Tue, 1 Jun 2021 16:21:59 +0530 Message-Id: <20210601105218.29185-3-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add Plane Degamma Mode as an enum property. Create a helper function for all plane color management features. This is an enum property with values as blob_id's and exposes the various gamma modes supported and the lut ranges. Getting the blob id in userspace, user can get the mode supported and also the range of gamma mode supported with number of lut coefficients. It can then set one of the modes using this enum property. Lut values will be sent through separate GAMMA_LUT blob property. Signed-off-by: Uma Shankar --- Documentation/gpu/drm-kms.rst | 90 ++++++++++++++++++++++ drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_atomic_state_helper.c | 2 + drivers/gpu/drm/drm_atomic_uapi.c | 4 + drivers/gpu/drm/drm_color_mgmt.c | 93 ++++++++++++++++++++++- include/drm/drm_mode_object.h | 2 +- include/drm/drm_plane.h | 23 ++++++ 7 files changed, 212 insertions(+), 3 deletions(-) diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 87e5023e3f55..752be545e7d7 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -514,9 +514,99 @@ Damage Tracking Properties Color Management Properties --------------------------- +Below is how a typical hardware pipeline for color +will look like: + +.. kernel-render:: DOT + :alt: Display Color Pipeline + :caption: Display Color Pipeline Overview + + digraph "KMS" { + node [shape=box] + + subgraph cluster_static { + style=dashed + label="Display Color Hardware Blocks" + + node [bgcolor=grey style=filled] + "Plane Degamma A" -> "Plane CSC/CTM A" + "Plane CSC/CTM A" -> "Plane Gamma A" + "Pipe Blender" [color=lightblue,style=filled, width=5.25, height=0.75]; + "Plane Gamma A" -> "Pipe Blender" + "Pipe Blender" -> "Pipe DeGamma" + "Pipe DeGamma" -> "Pipe CSC/CTM" + "Pipe CSC/CTM" -> "Pipe Gamma" + "Pipe Gamma" -> "Pipe Output" + } + + subgraph cluster_static { + style=dashed + + node [shape=box] + "Plane Degamma B" -> "Plane CSC/CTM B" + "Plane CSC/CTM B" -> "Plane Gamma B" + "Plane Gamma B" -> "Pipe Blender" + } + + subgraph cluster_static { + style=dashed + + node [shape=box] + "Plane Degamma C" -> "Plane CSC/CTM C" + "Plane CSC/CTM C" -> "Plane Gamma C" + "Plane Gamma C" -> "Pipe Blender" + } + + subgraph cluster_fb { + style=dashed + label="RAM" + + node [shape=box width=1.7 height=0.2] + + "FB 1" -> "Plane Degamma A" + "FB 2" -> "Plane Degamma B" + "FB 3" -> "Plane Degamma C" + } + } + +In real world usecases, + +1. Plane Degamma can be used to linearize a non linear gamma +encoded framebuffer. This is needed to do any linear math like +color space conversion. For ex, linearize frames encoded in SRGB +or by HDR curve. + +2. Later Plane CTM block can convert the content to some different +colorspace. For ex, SRGB to BT2020 etc. + +3. Plane Gamma block can be used later to re-apply the non-linear +curve. This can also be used to apply Tone Mapping for HDR usecases. + +All the layers or framebuffers need to be converted to same color +space and format before blending. The plane color hardware blocks +can help with this. Once the Data is blended, similar color processing +can be done on blended output using pipe color hardware blocks. + +DRM Properties have been created to define and expose all these +hardware blocks to userspace. A userspace application (compositor +or any color app) can use these interfaces and define policies to +efficiently use the display hardware for such color operations. + +Pipe Color Management Properties +--------------------------------- + .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c :doc: overview +Plane Color Management Properties +--------------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c + :doc: Plane Color Properties + +.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c + :doc: export + Tile Group Property ------------------- diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index a8bbb021684b..8892d03602f7 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -708,6 +708,7 @@ static void drm_atomic_plane_print_state(struct drm_printer *p, drm_get_color_encoding_name(state->color_encoding)); drm_printf(p, "\tcolor-range=%s\n", drm_get_color_range_name(state->color_range)); + drm_printf(p, "\tcolor_mgmt_changed=%d\n", state->color_mgmt_changed); if (plane->funcs->atomic_print_state) plane->funcs->atomic_print_state(p, state); diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index ddcf5c2c8e6a..f26b03853711 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -311,6 +311,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, state->fence = NULL; state->commit = NULL; state->fb_damage_clips = NULL; + + state->color_mgmt_changed = false; } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 438e9585b225..40fa05fa33dc 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -595,6 +595,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, state->color_encoding = val; } else if (property == plane->color_range_property) { state->color_range = val; + } else if (property == plane->degamma_mode_property) { + state->degamma_mode = val; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -661,6 +663,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane, *val = state->color_encoding; } else if (property == plane->color_range_property) { *val = state->color_range; + } else if (property == plane->degamma_mode_property) { + *val = state->degamma_mode; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index bb14f488c8f6..085ed0d0db00 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -34,8 +34,8 @@ /** * DOC: overview * - * Color management or color space adjustments is supported through a set of 5 - * properties on the &drm_crtc object. They are set up by calling + * Pipe Color management or color space adjustments is supported through a + * set of 5 properties on the &drm_crtc object. They are set up by calling * drm_crtc_enable_color_mgmt(). * * "DEGAMMA_LUT”: @@ -584,6 +584,95 @@ int drm_plane_create_color_properties(struct drm_plane *plane, } EXPORT_SYMBOL(drm_plane_create_color_properties); +/** + * DOC: Plane Color Properties + * + * Plane Color management or color space adjustments is supported + * through a set of 5 properties on the &drm_plane object. + * + * degamma_mode_property: + * Blob property which advertizes the possible degamma modes and + * lut ranges supported by the platform. This allows userspace + * to query and get the plane degamma color caps and choose the + * appropriate degamma mode and create lut values accordingly + * + */ +int drm_plane_create_color_mgmt_properties(struct drm_device *dev, + struct drm_plane *plane, + int num_values) +{ + struct drm_property *prop; + + prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, + "PLANE_DEGAMMA_MODE", num_values); + if (!prop) + return -ENOMEM; + + plane->degamma_mode_property = prop; + + return 0; +} +EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties); + +void drm_plane_attach_degamma_properties(struct drm_plane *plane) +{ + if (!plane->degamma_mode_property) + return; + + drm_object_attach_property(&plane->base, + plane->degamma_mode_property, 0); +} +EXPORT_SYMBOL(drm_plane_attach_degamma_properties); + +int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, + const char *name, + const struct drm_color_lut_range *ranges, + size_t length, enum lut_type type) +{ + struct drm_property_blob *blob; + struct drm_property *prop = NULL; + int num_ranges = length / sizeof(ranges[0]); + int i, ret, num_types_0; + + if (type == LUT_TYPE_DEGAMMA) + prop = plane->degamma_mode_property; + + if (!prop) + return -EINVAL; + + if (length == 0 && name) + return drm_property_add_enum(prop, 0, name); + + if (WARN_ON(length == 0 || length % sizeof(ranges[0]) != 0)) + return -EINVAL; + num_types_0 = hweight8(ranges[0].flags & (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA)); + if (num_types_0 == 0) + return -EINVAL; + + for (i = 1; i < num_ranges; i++) { + int num_types = hweight8(ranges[i].flags & (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_DEGAMMA)); + + /* either all ranges have DEGAMMA|GAMMA or none have it */ + if (num_types_0 != num_types) + return -EINVAL; + } + + blob = drm_property_create_blob(plane->dev, length, ranges); + if (IS_ERR(blob)) + return PTR_ERR(blob); + + ret = drm_property_add_enum(prop, blob->base.id, name); + if (ret) { + drm_property_blob_put(blob); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_plane_color_add_gamma_degamma_mode_range); + /** * drm_color_lut_check - check validity of lookup table * @lut: property blob containing LUT to check diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h index c34a3e8030e1..d4128c7daa08 100644 --- a/include/drm/drm_mode_object.h +++ b/include/drm/drm_mode_object.h @@ -60,7 +60,7 @@ struct drm_mode_object { void (*free_cb)(struct kref *kref); }; -#define DRM_OBJECT_MAX_PROPERTY 24 +#define DRM_OBJECT_MAX_PROPERTY 26 /** * struct drm_object_properties - property tracking for &drm_mode_object */ diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 1294610e84f4..e476a5939f8e 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -236,6 +236,15 @@ struct drm_plane_state { /** @state: backpointer to global drm_atomic_state */ struct drm_atomic_state *state; + + /** + * @degamma_mode: This is a blob_id and exposes the platform capabilities + * wrt to various gamma modes and the respective lut ranges. This also + * helps user select a degamma mode amongst the supported ones. + */ + u32 degamma_mode; + + u8 color_mgmt_changed : 1; }; static inline struct drm_rect @@ -747,6 +756,12 @@ struct drm_plane { * scaling. */ struct drm_property *scaling_filter_property; + + /** + * @degamma_mode_property: Optional Plane property to set the LUT + * used to convert the framebuffer's colors to linear gamma. + */ + struct drm_property *degamma_mode_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) @@ -838,6 +853,14 @@ void drm_plane_force_disable(struct drm_plane *plane); int drm_mode_plane_set_obj_prop(struct drm_plane *plane, struct drm_property *property, uint64_t value); +int drm_plane_create_color_mgmt_properties(struct drm_device *dev, + struct drm_plane *plane, + int num_values); +void drm_plane_attach_degamma_properties(struct drm_plane *plane); +int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, + const char *name, + const struct drm_color_lut_range *ranges, + size_t length, enum lut_type type); /** * drm_plane_find - find a &drm_plane From patchwork Tue Jun 1 10:52:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95CD3C47080 for ; Tue, 1 Jun 2021 10:16:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6052D613AB for ; Tue, 1 Jun 2021 10:16:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6052D613AB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 080336E9E4; Tue, 1 Jun 2021 10:16:09 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id A09846E9E3; Tue, 1 Jun 2021 10:16:07 +0000 (UTC) IronPort-SDR: GGM64ew4BmETC1ybfKOIa2tQWAYFZ7vhkr8ANSLvgMSqL7HtRust74IoOXhazRZPNDnGqfoSee VpKVasPNXUeA== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203549946" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203549946" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:07 -0700 IronPort-SDR: gx5phQ/jIwI05I5ogUbSWKGCNCAVD5mMT+2QO75IWa2jon50pHhZuoc/wJxADDXGcmYebm/5+7 Ayv7O3499vwQ== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431189" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:05 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 03/21] drm: Add Plane Degamma Lut property Date: Tue, 1 Jun 2021 16:22:00 +0530 Message-Id: <20210601105218.29185-4-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add Plane Degamma Lut as a blob property. User will calculate the lut values, create the blob and send it to driver using this property. Lut calculation will be based on the gamma mode chosen out of the gamma mode exposed. Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_atomic_state_helper.c | 4 ++++ drivers/gpu/drm/drm_atomic_uapi.c | 10 ++++++++++ drivers/gpu/drm/drm_color_mgmt.c | 19 +++++++++++++++++++ include/drm/drm_plane.h | 14 ++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index f26b03853711..6e358067cb7a 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -312,6 +312,9 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, state->commit = NULL; state->fb_damage_clips = NULL; + if (state->degamma_lut) + drm_property_blob_get(state->degamma_lut); + state->color_mgmt_changed = false; } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); @@ -359,6 +362,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_crtc_commit_put(state->commit); drm_property_blob_put(state->fb_damage_clips); + drm_property_blob_put(state->degamma_lut); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 40fa05fa33dc..ce3cb65d415e 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -597,6 +597,13 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, state->color_range = val; } else if (property == plane->degamma_mode_property) { state->degamma_mode = val; + } else if (property == plane->degamma_lut_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->degamma_lut, + val, -1, sizeof(struct drm_color_lut_ext), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -665,6 +672,9 @@ drm_atomic_plane_get_property(struct drm_plane *plane, *val = state->color_range; } else if (property == plane->degamma_mode_property) { *val = state->degamma_mode; + } else if (property == plane->degamma_lut_property) { + *val = (state->degamma_lut) ? + state->degamma_lut->base.id : 0; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 085ed0d0db00..29d0fc1e52b5 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -596,6 +596,12 @@ EXPORT_SYMBOL(drm_plane_create_color_properties); * to query and get the plane degamma color caps and choose the * appropriate degamma mode and create lut values accordingly * + * degamma_lut_property: + * Blob property which allows a userspace to provide LUT values + * to apply degamma curve using the h/w plane degamma processing + * engine, thereby making the content as linear for further color + * processing. + * */ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, struct drm_plane *plane, @@ -610,6 +616,13 @@ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, plane->degamma_mode_property = prop; + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "PLANE_DEGAMMA_LUT", 0); + if (!prop) + return -ENOMEM; + + plane->degamma_lut_property = prop; + return 0; } EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties); @@ -621,6 +634,12 @@ void drm_plane_attach_degamma_properties(struct drm_plane *plane) drm_object_attach_property(&plane->base, plane->degamma_mode_property, 0); + + if (!plane->degamma_lut_property) + return; + + drm_object_attach_property(&plane->base, + plane->degamma_lut_property, 0); } EXPORT_SYMBOL(drm_plane_attach_degamma_properties); diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index e476a5939f8e..bbd0033ed1d2 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -244,6 +244,14 @@ struct drm_plane_state { */ u32 degamma_mode; + /* @degamma_lut: + * + * Lookup table for converting framebuffer pixel data before apply the + * color conversion matrix @ctm. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is an array of &struct drm_color_lut_ext. + */ + struct drm_property_blob *degamma_lut; + u8 color_mgmt_changed : 1; }; @@ -762,6 +770,12 @@ struct drm_plane { * used to convert the framebuffer's colors to linear gamma. */ struct drm_property *degamma_mode_property; + + /** + * @degamma_lut_property: Optional Plane property to set the LUT + * used to convert the framebuffer's colors to linear gamma. + */ + struct drm_property *degamma_lut_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) From patchwork Tue Jun 1 10:52:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C484DC47093 for ; Tue, 1 Jun 2021 10:16:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 917EB61396 for ; Tue, 1 Jun 2021 10:16:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 917EB61396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD6CA6E9EA; Tue, 1 Jun 2021 10:16:11 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6C7346E9EC; Tue, 1 Jun 2021 10:16:10 +0000 (UTC) IronPort-SDR: r1siSZytJ8NYIQzeX8JORiS+crGQ66kXqu6TpewkfpbMytfYBu5LWI7a/AqO/zce7OhoRRi0P7 vaTEDUHVihKA== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203549960" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203549960" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:09 -0700 IronPort-SDR: iK9fpCnn2lHnL3CJo0LtfAd0VS9c7sh9jcyZgmUoSYa1+IeI9f0cyYzoCPHTpdC4D+bqqHo0ka adSk10KjeFhw== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431217" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:07 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 04/21] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes Date: Tue, 1 Jun 2021 16:22:01 +0530 Message-Id: <20210601105218.29185-5-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Define the structure with XE_LPD degamma lut ranges. HDR and SDR planes have different capabilities, implemented respective structure for the HDR planes. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index dab892d2251b..c735d06a6b54 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -2093,6 +2093,58 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state) } } + /* FIXME input bpc? */ +__maybe_unused +static const struct drm_color_lut_range d13_degamma_hdr[] = { + /* segment 1 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 128, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = (1 << 24) - 1, + .min = 0, .max = (1 << 24) - 1, + }, + /* segment 2 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 24) - 1, .end = 1 << 24, + .min = 0, .max = (1 << 27) - 1, + }, + /* Segment 3 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 1 << 24, .end = 3 << 24, + .min = 0, .max = (1 << 27) - 1, + }, + /* Segment 4 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 3 << 24, .end = 7 << 24, + .min = 0, .max = (1 << 27) - 1, + }, +}; + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); From patchwork Tue Jun 1 10:52:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE33DC47092 for ; Tue, 1 Jun 2021 10:16:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B09A161396 for ; Tue, 1 Jun 2021 10:16:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B09A161396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ACAAB6E9EC; Tue, 1 Jun 2021 10:16:12 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F45C6E9E9; Tue, 1 Jun 2021 10:16:11 +0000 (UTC) IronPort-SDR: 1PEwMgu4HxP0nMDabVzMAkATuxRHmdmLw7GcM5e/xaXRzZo/wW/HWzlutOP1RY3oJXKrJlGLtg l9COHvwKpVWA== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203549968" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203549968" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:11 -0700 IronPort-SDR: g3+sokxoDgDukmNO4AZqHn6+3TzgbI5+ZdPq4uGGMNVIvm0L3oCsI8z0CAbRBfdyDOusFibMuj f2XgV2i0n2/Q== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431247" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:09 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 05/21] drm/i915/xelpd: Add register definitions for Plane Degamma Date: Tue, 1 Jun 2021 16:22:02 +0530 Message-Id: <20210601105218.29185-6-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add macros to define Plane Degamma registers Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 24307c49085f..9431913969f3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -262,6 +262,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ DISPLAY_MMIO_BASE(dev_priv)) +/* Plane Gamma Registers */ +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) + #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) #define _MASKED_FIELD(mask, value) ({ \ if (__builtin_constant_p(mask)) \ @@ -11300,6 +11303,55 @@ enum skl_power_gate { _PAL_PREC_MULTI_SEG_DATA_A, \ _PAL_PREC_MULTI_SEG_DATA_B) +/* Display13 Plane Degmma Reg */ +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x712d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B) +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B) +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701d4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711d4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702d4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712d4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \ + _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B) +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \ + _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B) +#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \ + _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_INDEX_1_A 0x704d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_1_B 0x714d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_2_A 0x705d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_2_B 0x715d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_1_A, \ + _PLANE_PRE_CSC_GAMC_INDEX_1_B) +#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_2_A, \ + _PLANE_PRE_CSC_GAMC_INDEX_2_B) +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \ + _PLANE_PRE_CSC_GAMC_INDEX_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_DATA_1_A 0x704d4 +#define _PLANE_PRE_CSC_GAMC_DATA_1_B 0x714d4 +#define _PLANE_PRE_CSC_GAMC_DATA_2_A 0x705d4 +#define _PLANE_PRE_CSC_GAMC_DATA_2_B 0x715d4 +#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_1_A, \ + _PLANE_PRE_CSC_GAMC_DATA_1_B) +#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_2_A, \ + _PLANE_PRE_CSC_GAMC_DATA_2_B) +#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \ + _PLANE_PRE_CSC_GAMC_DATA_2(pipe)) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) From patchwork Tue Jun 1 10:52:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E666EC47080 for ; Tue, 1 Jun 2021 10:16:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AED056139A for ; Tue, 1 Jun 2021 10:16:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AED056139A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 76BEF6E9EF; Tue, 1 Jun 2021 10:16:14 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E1706E9EB; Tue, 1 Jun 2021 10:16:13 +0000 (UTC) IronPort-SDR: AB2zTaonUm8FmnKnkAogvvFKazQk2tl02rK/RePIZ7eWfT6w8Vn2UXCcLjYF+cs+BsXy8W6FLj c4uH2k6SDZsQ== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203549975" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203549975" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:13 -0700 IronPort-SDR: +zk230PKXcaNpFvD2gefNEQjAfMgmvqfdB4DpcJzsI93cQfopjrSPwn40cnxOEqVmz4Bbbc7t2 xbA3jmgbZu/w== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431258" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:11 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 06/21] drm/i915/xelpd: Enable plane color features Date: Tue, 1 Jun 2021 16:22:03 +0530 Message-Id: <20210601105218.29185-7-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable and initialize plane color features. Also initialize the color features of HDR planes. Signed-off-by: Uma Shankar Signed-off-by: Bhanuprakash Modem --- drivers/gpu/drm/i915/display/intel_color.c | 22 +++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_color.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 3 +++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index c735d06a6b54..00a0d45632fe 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -25,6 +25,7 @@ #include "intel_color.h" #include "intel_de.h" #include "intel_display_types.h" +#include #define CTM_COEFF_SIGN (1ULL << 63) @@ -2094,7 +2095,6 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state) } /* FIXME input bpc? */ -__maybe_unused static const struct drm_color_lut_range d13_degamma_hdr[] = { /* segment 1 */ { @@ -2145,6 +2145,26 @@ static const struct drm_color_lut_range d13_degamma_hdr[] = { }, }; +int intel_plane_color_init(struct drm_plane *plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->dev); + int ret = 0; + + if (DISPLAY_VER(dev_priv) >= 13) { + drm_plane_create_color_mgmt_properties(plane->dev, plane, 2); + ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no degamma", + NULL, 0, + LUT_TYPE_DEGAMMA); + ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "plane degamma", + d13_degamma_hdr, + sizeof(d13_degamma_hdr), + LUT_TYPE_DEGAMMA); + drm_plane_attach_degamma_properties(plane); + } + + return ret; +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index 173727aaa24d..b8850bb1b0c9 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -10,6 +10,7 @@ struct intel_crtc_state; struct intel_crtc; +struct drm_plane; struct drm_property_blob; void intel_color_init(struct intel_crtc *crtc); @@ -21,5 +22,6 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat bool intel_color_lut_equal(struct drm_property_blob *blob1, struct drm_property_blob *blob2, u32 gamma_mode, u32 bit_precision); +int intel_plane_color_init(struct drm_plane *plane); #endif /* __INTEL_COLOR_H__ */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0f6d27da69ac..f955f039edba 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -326,6 +326,9 @@ struct drm_i915_display_funcs { */ void (*load_luts)(const struct intel_crtc_state *crtc_state); void (*read_luts)(struct intel_crtc_state *crtc_state); + /* Add Plane Color callbacks */ + void (*load_plane_csc_matrix)(const struct drm_plane_state *plane_state); + void (*load_plane_luts)(const struct drm_plane_state *plane_state); }; struct intel_dmc { From patchwork Tue Jun 1 10:52:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64CE3C4708F for ; Tue, 1 Jun 2021 10:16:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 34B0D6139A for ; Tue, 1 Jun 2021 10:16:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 34B0D6139A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56AE16E9EB; Tue, 1 Jun 2021 10:16:16 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 37CE56E9F2; Tue, 1 Jun 2021 10:16:15 +0000 (UTC) IronPort-SDR: IdkQ3Wj1bd6NSv+Wdixh9QiVISgtd5t20Cq3qyp7fZZKvpcVs9VaBJO16s9siiZYrtqTIToDBf ayBqnsc4WIXg== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203549979" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203549979" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:14 -0700 IronPort-SDR: PSjq4OUyoxc4sin4JJBlh2pYpR1ogOtc83851nYi1ple6BaZz7kP3eHGGbL1YHd/7be/ZwQEat pYsl0Dzxcoig== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431271" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:13 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 07/21] drm/i915/xelpd: Add color capabilities of SDR planes Date: Tue, 1 Jun 2021 16:22:04 +0530 Message-Id: <20210601105218.29185-8-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the Color capabilities of SDR planes. Signed-off-by: Uma Shankar Signed-off-by: Bhanuprakash Modem --- drivers/gpu/drm/i915/display/intel_color.c | 67 ++++++++++++++++++++-- 1 file changed, 63 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 00a0d45632fe..4908e825f3cc 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -25,6 +25,7 @@ #include "intel_color.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_sprite.h" #include #define CTM_COEFF_SIGN (1ULL << 63) @@ -2145,6 +2146,57 @@ static const struct drm_color_lut_range d13_degamma_hdr[] = { }, }; + /* FIXME input bpc? */ +static const struct drm_color_lut_range d13_degamma_sdr[] = { + /* segment 1 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 32, + .input_bpc = 16, .output_bpc = 16, + .start = 0, .end = (1 << 16) - (1 << 16) / 33, + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 2 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 16, .output_bpc = 16, + .start = (1 << 16) - (1 << 16) / 33, .end = 1 << 16, + .min = 0, .max = 1 << 16, + }, + /* Segment 3 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 16, .output_bpc = 16, + .start = 1 << 16, .end = 3 << 16, + .min = 0, .max = (8 << 16) - 1, + }, + /* Segment 4 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 16, .output_bpc = 16, + .start = 3 << 16, .end = 7 << 16, + .min = 0, .max = (8 << 16) - 1, + }, +}; + int intel_plane_color_init(struct drm_plane *plane) { struct drm_i915_private *dev_priv = to_i915(plane->dev); @@ -2155,10 +2207,17 @@ int intel_plane_color_init(struct drm_plane *plane) ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no degamma", NULL, 0, LUT_TYPE_DEGAMMA); - ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "plane degamma", - d13_degamma_hdr, - sizeof(d13_degamma_hdr), - LUT_TYPE_DEGAMMA); + if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id)) + ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "plane degamma", + d13_degamma_hdr, + sizeof(d13_degamma_hdr), + LUT_TYPE_DEGAMMA); + else + ret = drm_plane_color_add_gamma_degamma_mode_range(plane, + "plane degamma", + d13_degamma_sdr, + sizeof(d13_degamma_sdr), + LUT_TYPE_DEGAMMA); drm_plane_attach_degamma_properties(plane); } From patchwork Tue Jun 1 10:52:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0089AC47092 for ; Tue, 1 Jun 2021 10:16:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC7326139A for ; Tue, 1 Jun 2021 10:16:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BC7326139A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 275416E9F4; Tue, 1 Jun 2021 10:16:19 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E2446E9F0; Tue, 1 Jun 2021 10:16:17 +0000 (UTC) IronPort-SDR: CI7/BLBn5Aav8uqtwj2PGEpqOWqUYMxI01rJ881Mrj6W+FuFQDzV3iixbIbT+BMN/qjPgYPbDo 9Kk8cDvDa/fA== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203549989" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203549989" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:16 -0700 IronPort-SDR: 8aYIfoeQXwoCOH7hxnz2jUtIl2vUvEgmgvbPnmMd0T2+FPPqWoIRnUXyjdqgzauhQSK/w2T8B2 kVMwwBmDV23A== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431289" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:15 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 08/21] drm/i915/xelpd: Program Plane Degamma Registers Date: Tue, 1 Jun 2021 16:22:05 +0530 Message-Id: <20210601105218.29185-9-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Extract the LUT and program plane degamma registers. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 116 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 + 2 files changed, 118 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 4908e825f3cc..4e5733573fd8 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -126,6 +126,29 @@ static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state lut_is_legacy(crtc_state->hw.gamma_lut); } +/* + * Added to accommodate enhanced LUT precision. + * Max LUT precision is 32 bits. + */ +static u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision) +{ + u64 val = user_input & 0xffffffff; + u32 max; + + if (bit_precision > 32) + return 0; + + max = 0xffffffff >> (32 - bit_precision); + /* Round only if we're not using full precision. */ + if (bit_precision < 32) { + val += 1UL << (32 - bit_precision - 1); + val >>= 32 - bit_precision; + } + + return ((user_input & 0xffffffff00000000) | + clamp_val(val, 0, max)); +} + /* * When using limited range, multiply the matrix given by userspace by * the matrix that we would use for the limited range. @@ -2197,6 +2220,97 @@ static const struct drm_color_lut_range d13_degamma_sdr[] = { }, }; +static void d13_program_plane_degamma_lut(const struct drm_plane_state *state, + struct drm_color_lut_ext *degamma_lut, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u32 i, lut_size; + + if (icl_is_hdr_plane(dev_priv, plane)) { + lut_size = 128; + + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), + PLANE_PAL_PREC_AUTO_INCREMENT); + + if (degamma_lut) { + for (i = 0; i < lut_size; i++) { + u64 word = drm_color_lut_extract_ext(degamma_lut[i].green, 24); + u32 lut_val = (word & 0xffffff); + + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + lut_val); + } + + /* Program the max register to clamp values > 1.0. */ + while (i < 131) + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + degamma_lut[i++].green); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); + } + + do { + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + 1 << 24); + } while (i++ < 130); + } + + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); + } else { + lut_size = 32; + + /* + * First 3 planes are HDR, so reduce by 3 to get to the right + * SDR plane offset + */ + plane = plane - 3; + + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, 0), + PLANE_PAL_PREC_AUTO_INCREMENT); + + if (degamma_lut) { + for (i = 0; i < lut_size; i++) + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + degamma_lut[i].green); + /* Program the max register to clamp values > 1.0. */ + while (i < 35) + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + degamma_lut[i++].green); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1); + + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), v); + } + + do { + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + 1 << 16); + } while (i++ < 34); + } + + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, 0), 0); + } +} + +static void d13_plane_load_luts(const struct drm_plane_state *plane_state) +{ + const struct drm_property_blob *degamma_lut_blob = + plane_state->degamma_lut; + struct drm_color_lut_ext *degamma_lut = NULL; + + if (degamma_lut_blob) { + degamma_lut = degamma_lut_blob->data; + d13_program_plane_degamma_lut(plane_state, degamma_lut, 0); + } +} + int intel_plane_color_init(struct drm_plane *plane) { struct drm_i915_private *dev_priv = to_i915(plane->dev); @@ -2218,6 +2332,8 @@ int intel_plane_color_init(struct drm_plane *plane) d13_degamma_sdr, sizeof(d13_degamma_sdr), LUT_TYPE_DEGAMMA); + + dev_priv->display.load_plane_luts = d13_plane_load_luts; drm_plane_attach_degamma_properties(plane); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9431913969f3..ede7dca440e2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7189,6 +7189,7 @@ enum { #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ +#define PLANE_PRE_CSC_GAMMA_ENABLE (1 << 14) #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17) #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) @@ -11315,6 +11316,7 @@ enum skl_power_gate { #define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) \ _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) +#define PLANE_PAL_PREC_AUTO_INCREMENT (1 << 10) #define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701d4 #define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711d4 From patchwork Tue Jun 1 10:52:06 2021 Content-Type: text/plain; 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dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 071AA6E9F3; Tue, 1 Jun 2021 10:16:22 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A2C46E9F2; Tue, 1 Jun 2021 10:16:20 +0000 (UTC) IronPort-SDR: QOT4bEa4gKYSZqS4Gr4GVX8nttD8ABg09YUZj1405Myctpl6cOmXIEOrb1K/trSaR2AwmsAAuh iw9wVnoL3eVw== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203549998" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203549998" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:19 -0700 IronPort-SDR: XxeAUV91/h8IRdY+eCl4DPdkqzcOg2hhDAYuO+ksV2fkrZ/4qulyCYhkksBUQ2Fy8kXkMuMFfM Fh9hZdgO+i/A== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431299" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:17 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 09/21] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Date: Tue, 1 Jun 2021 16:22:06 +0530 Message-Id: <20210601105218.29185-10-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Extended glk_plane_color_ctl to have plane color checks. This helps enabling the degamma or gamma block based on user inputs. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 92a4fd508e92..ae439dca4b3c 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -960,6 +960,11 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, u32 plane_color_ctl = 0; plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; + + /* FIXME needs hw.degamma_lut */ + if (plane_state->uapi.degamma_lut) + plane_color_ctl |= PLANE_PRE_CSC_GAMMA_ENABLE; + plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { From patchwork Tue Jun 1 10:52:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AEC5C47092 for ; Tue, 1 Jun 2021 10:16:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E1E0D61396 for ; Tue, 1 Jun 2021 10:16:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E1E0D61396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E198E6E9F7; Tue, 1 Jun 2021 10:16:23 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id D52E06E9F2; Tue, 1 Jun 2021 10:16:21 +0000 (UTC) IronPort-SDR: iNedb+nvi+t92kVx0zqoaUXmmyCxwrwggh1CKM1unI+AyBXTARxQdK+92YLCPMfn6ApsWG+kks asZrw6zbq6Mw== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550002" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550002" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:21 -0700 IronPort-SDR: Uei5AL0gV3yyJkEqNDQwz7gbuyL3x+yD2RXXYCmGjL9aBcJ7JApZ2xJVQxr7Fvzv0aEyya4mZm 3mNXluH519hw== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431311" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:19 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 10/21] drm/i915/xelpd: Initialize plane color features Date: Tue, 1 Jun 2021 16:22:07 +0530 Message-Id: <20210601105218.29185-11-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Initialize plane color features for XE_LPD. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 + drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index dc4d05e75e1c..c809f522a710 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -65,5 +65,6 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, bool can_position); void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state); +int intel_plane_color_init(struct drm_plane *plane); #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index ae439dca4b3c..aadb984fdf77 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2184,6 +2184,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, BIT(DRM_SCALING_FILTER_DEFAULT) | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); + intel_plane_color_init(&plane->base); + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); return plane; From patchwork Tue Jun 1 10:52:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FC2BC47092 for ; Tue, 1 Jun 2021 10:16:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 287C561396 for ; Tue, 1 Jun 2021 10:16:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 287C561396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A9896E9F9; Tue, 1 Jun 2021 10:16:26 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id BF5176E9F2; Tue, 1 Jun 2021 10:16:23 +0000 (UTC) IronPort-SDR: /WKxFs42QKPNS1+K0Ty091SBl9S9EMaPLlY8aNuRn0VMSU1bhLZaj8l9XRWgp5grpLpBfLHuuw Se5smXMsgOEg== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550007" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550007" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:23 -0700 IronPort-SDR: qEv8SNUSBr55OUVOi6SR3/u3fOzK0AqpIU9X1IdDwSu3YbP5iITnEoOfqDwnrSbgzj+ndIG+6g CAqwUQC3uc0g== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431328" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:21 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 11/21] drm/i915/xelpd: Load plane color luts from atomic flip Date: Tue, 1 Jun 2021 16:22:08 +0530 Message-Id: <20210601105218.29185-12-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Load plane color luts as part of atomic plane updates. This will be done only if the plane color luts are changed. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 3 +++ drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 + drivers/gpu/drm/i915/display/intel_color.c | 9 +++++++++ 3 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 36f52a1d7552..5de9c98beaf6 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -513,6 +513,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state, struct intel_plane_state *new_plane_state = intel_atomic_get_new_plane_state(state, plane); + if (new_plane_state->uapi.color_mgmt_changed) + intel_color_load_plane_luts(&new_plane_state->uapi); + if (new_plane_state->uapi.visible || new_plane_state->planar_slave) { intel_update_plane(plane, new_crtc_state, new_plane_state); diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index c809f522a710..1ba3b524cee2 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -66,5 +66,6 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state); int intel_plane_color_init(struct drm_plane *plane); +void intel_color_load_plane_luts(const struct drm_plane_state *plane_state); #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 4e5733573fd8..6d57a47d8a60 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -22,6 +22,7 @@ * */ +#include "intel_atomic_plane.h" #include "intel_color.h" #include "intel_de.h" #include "intel_display_types.h" @@ -2311,6 +2312,14 @@ static void d13_plane_load_luts(const struct drm_plane_state *plane_state) } } +void intel_color_load_plane_luts(const struct drm_plane_state *plane_state) +{ + struct drm_device *dev = plane_state->plane->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + + dev_priv->display.load_plane_luts(plane_state); +} + int intel_plane_color_init(struct drm_plane *plane) { struct drm_i915_private *dev_priv = to_i915(plane->dev); From patchwork Tue Jun 1 10:52:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09453C4708F for ; Tue, 1 Jun 2021 10:16:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C770961396 for ; Tue, 1 Jun 2021 10:16:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C770961396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E37F96E9FD; Tue, 1 Jun 2021 10:16:27 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id B10146E9F8; Tue, 1 Jun 2021 10:16:25 +0000 (UTC) IronPort-SDR: JBlVQffW70CdvObLPA+L6PnHWyukd3rkg/jLROSzlU5IQkhqrJbQXgIbomzrfbFLdfn2VzlLL5 xWKRGOKPcVxg== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550011" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550011" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:25 -0700 IronPort-SDR: Im/zkkUO31HB/fw+7t83aeoCfB+SKlGwp7yhsjWEz1DuvRHI1ls1ExVIlNAbs2SqSwe/QN9dJe 179dsaReEZZA== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431338" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:23 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 12/21] drm: Add Plane CTM property Date: Tue, 1 Jun 2021 16:22:09 +0530 Message-Id: <20210601105218.29185-13-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a blob property for plane CSC usage. Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++ drivers/gpu/drm/drm_atomic_uapi.c | 10 ++++++++++ drivers/gpu/drm/drm_color_mgmt.c | 11 +++++++++++ include/drm/drm_plane.h | 15 +++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 6e358067cb7a..fafb8af1c9cb 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -314,6 +314,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, if (state->degamma_lut) drm_property_blob_get(state->degamma_lut); + if (state->ctm) + drm_property_blob_get(state->ctm); state->color_mgmt_changed = false; } @@ -363,6 +365,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_property_blob_put(state->fb_damage_clips); drm_property_blob_put(state->degamma_lut); + drm_property_blob_put(state->ctm); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index ce3cb65d415e..6af2afe362ff 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -604,6 +604,14 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == plane->ctm_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->ctm, + val, + sizeof(struct drm_color_ctm), -1, + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -675,6 +683,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane, } else if (property == plane->degamma_lut_property) { *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0; + } else if (property == plane->ctm_property) { + *val = (state->ctm) ? state->ctm->base.id : 0; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 29d0fc1e52b5..83832adf3adf 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -602,6 +602,10 @@ EXPORT_SYMBOL(drm_plane_create_color_properties); * engine, thereby making the content as linear for further color * processing. * + * ctm_property: + * Blob property which allows a userspace to provide CTM coefficients + * to do color space conversion or any other enhancement by doing a + * matrix multiplication using the h/w CTM processing engine */ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, struct drm_plane *plane, @@ -623,6 +627,13 @@ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, plane->degamma_lut_property = prop; + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "PLANE_CTM", 0); + if (!prop) + return -ENOMEM; + + plane->ctm_property = prop; + return 0; } EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties); diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index bbd0033ed1d2..83d11918333b 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -252,6 +252,14 @@ struct drm_plane_state { */ struct drm_property_blob *degamma_lut; + /** + * @ctm: + * + * Color transformation matrix. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is a &struct drm_color_ctm. + */ + struct drm_property_blob *ctm; + u8 color_mgmt_changed : 1; }; @@ -776,6 +784,13 @@ struct drm_plane { * used to convert the framebuffer's colors to linear gamma. */ struct drm_property *degamma_lut_property; + + /** + * @plane_ctm_property: Optional Plane property to set the + * matrix used to convert colors after the lookup in the + * degamma LUT. + */ + struct drm_property *ctm_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) From patchwork Tue Jun 1 10:52:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D85C47092 for ; Tue, 1 Jun 2021 10:16:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4FDB60FD8 for ; Tue, 1 Jun 2021 10:16:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E4FDB60FD8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B9276E9F5; Tue, 1 Jun 2021 10:16:29 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 99D8D6E9FE; Tue, 1 Jun 2021 10:16:27 +0000 (UTC) IronPort-SDR: zc9rjJzVDmT2rIaHoBcNMSGIFFIUCxaFbKWO5ehu9nuUZ9IIaYrNVhNXjMIaKfHIWqTfxltqFQ SE5R6gsWns1g== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550019" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550019" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:27 -0700 IronPort-SDR: 6QqiDCPCLpbSCXrbMfMCPu7gZdrPaRB8ROj5KAn6Xt5ikfUiE34anM0K8SpgK8v65e0XkAzDlL EijzoNxBJbSQ== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431344" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:25 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 13/21] drm: Add helper to attach Plane ctm property Date: Tue, 1 Jun 2021 16:22:10 +0530 Message-Id: <20210601105218.29185-14-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a DRM helper to attach ctm property. Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_color_mgmt.c | 10 ++++++++++ include/drm/drm_plane.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 83832adf3adf..5c3138497b9c 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -654,6 +654,16 @@ void drm_plane_attach_degamma_properties(struct drm_plane *plane) } EXPORT_SYMBOL(drm_plane_attach_degamma_properties); +void drm_plane_attach_ctm_property(struct drm_plane *plane) +{ + if (!plane->ctm_property) + return; + + drm_object_attach_property(&plane->base, + plane->ctm_property, 0); +} +EXPORT_SYMBOL(drm_plane_attach_ctm_property); + int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges, diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 83d11918333b..4557f59cf3cf 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -886,6 +886,7 @@ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, struct drm_plane *plane, int num_values); void drm_plane_attach_degamma_properties(struct drm_plane *plane); +void drm_plane_attach_ctm_property(struct drm_plane *plane); int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges, From patchwork Tue Jun 1 10:52:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69672C47080 for ; Tue, 1 Jun 2021 10:16:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3592560FD8 for ; Tue, 1 Jun 2021 10:16:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3592560FD8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B2946E9FF; Tue, 1 Jun 2021 10:16:32 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 804F86EA00; Tue, 1 Jun 2021 10:16:29 +0000 (UTC) IronPort-SDR: q4n2Xl9WFnQrILHl6tFBkacynV7ShOAp07DMVrPotNWBDwqanAP3u2pB9Y6Tcdu7iHwgGG/QDV VvFXs5TwcxSw== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550024" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550024" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:29 -0700 IronPort-SDR: yjGpDNy0Lshp4q3fVVAx/m+omVi2u9CtQMIEJ+fJ2lAe6/6JP+1jTghzhTNpM7j4FyCWyMlfbw qj/uUjvM4gWg== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431353" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:27 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 14/21] drm/i915/xelpd: Define Plane CSC Registers Date: Tue, 1 Jun 2021 16:22:11 +0530 Message-Id: <20210601105218.29185-15-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Define Register macros for plane CSC. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 43 +++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ede7dca440e2..df8500a86e9d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7397,6 +7397,49 @@ enum { #define PLANE_COLOR_CTL(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) +/* Plane CSC Registers */ +#define _PLANE_CSC_RY_GY_1_A 0x70210 +#define _PLANE_CSC_RY_GY_2_A 0x70310 + +#define _PLANE_CSC_RY_GY_1_B 0x71210 +#define _PLANE_CSC_RY_GY_2_B 0x71310 + +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ + _PLANE_CSC_RY_GY_1_B) +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ + _PLANE_INPUT_CSC_RY_GY_2_B) +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) + +#define _PLANE_CSC_PREOFF_HI_1_A 0x70228 +#define _PLANE_CSC_PREOFF_HI_2_A 0x70328 + +#define _PLANE_CSC_PREOFF_HI_1_B 0x71228 +#define _PLANE_CSC_PREOFF_HI_2_B 0x71328 + +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ + _PLANE_CSC_PREOFF_HI_1_B) +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ + _PLANE_CSC_PREOFF_HI_2_B) +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ + (index) * 4) + +#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 +#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 + +#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 +#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 + +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ + _PLANE_CSC_POSTOFF_HI_1_B) +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ + _PLANE_CSC_POSTOFF_HI_2_B) +#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ + (index) * 4) + #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 From patchwork Tue Jun 1 10:52:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B800C47092 for ; Tue, 1 Jun 2021 10:16:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A13261396 for ; Tue, 1 Jun 2021 10:16:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A13261396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1629D6EA02; Tue, 1 Jun 2021 10:16:33 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 98EB26EA01; Tue, 1 Jun 2021 10:16:31 +0000 (UTC) IronPort-SDR: ZIudHiwGzAvZk4Dqc/JR7xAafAjn41SSoUlFUyXaBKrw4DWMmsIWUqvMphMoxz5oxuchROmQN5 L5W8WEc5QlVg== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550029" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550029" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:31 -0700 IronPort-SDR: Yu1SgrePCtBxoCVbM+NHUMEHwTPY9pDpJBRX99BBVHxXODXMtDM4QeZwA/CM9QH5AimqcPEI8m FWc/4L2KEgiA== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431365" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:29 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 15/21] drm/i915/xelpd: Enable Plane CSC Date: Tue, 1 Jun 2021 16:22:12 +0530 Message-Id: <20210601105218.29185-16-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement plane CSC for ICL+ Signed-off-by: Uma Shankar --- .../gpu/drm/i915/display/intel_atomic_plane.c | 5 +- drivers/gpu/drm/i915/display/intel_color.c | 82 +++++++++++++++++++ .../drm/i915/display/skl_universal_plane.c | 4 + drivers/gpu/drm/i915/i915_reg.h | 1 + 4 files changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 5de9c98beaf6..ec7646790892 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -499,6 +499,7 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); struct skl_ddb_entry entries_y[I915_MAX_PLANES]; struct skl_ddb_entry entries_uv[I915_MAX_PLANES]; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 update_mask = new_crtc_state->update_planes; struct intel_plane *plane; @@ -513,8 +514,10 @@ void skl_update_planes_on_crtc(struct intel_atomic_state *state, struct intel_plane_state *new_plane_state = intel_atomic_get_new_plane_state(state, plane); - if (new_plane_state->uapi.color_mgmt_changed) + if (new_plane_state->uapi.color_mgmt_changed) { intel_color_load_plane_luts(&new_plane_state->uapi); + dev_priv->display.load_plane_csc_matrix(&new_plane_state->uapi); + } if (new_plane_state->uapi.visible || new_plane_state->planar_slave) { diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 6d57a47d8a60..8b4f653b213d 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -2119,6 +2119,83 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state) } } +static void icl_load_plane_csc_matrix(const struct drm_plane_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + struct drm_color_ctm *ctm; + const u64 *input; + u16 coeffs[9] = {}; + u16 postoff = 0; + int i; + + if (!icl_is_hdr_plane(dev_priv, plane) || !state->ctm) + return; + + ctm = state->ctm->data; + input = ctm->matrix; + + /* + * Convert fixed point S31.32 input to format supported by the + * hardware. + */ + for (i = 0; i < ARRAY_SIZE(coeffs); i++) { + u64 abs_coeff = ((1ULL << 63) - 1) & input[i]; + + /* + * Clamp input value to min/max supported by + * hardware. + */ + abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); + + /* sign bit */ + if (CTM_COEFF_NEGATIVE(input[i])) + coeffs[i] |= 1 << 15; + + if (abs_coeff < CTM_COEFF_0_125) + coeffs[i] |= (3 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 12); + else if (abs_coeff < CTM_COEFF_0_25) + coeffs[i] |= (2 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 11); + else if (abs_coeff < CTM_COEFF_0_5) + coeffs[i] |= (1 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 10); + else if (abs_coeff < CTM_COEFF_1_0) + coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9); + else if (abs_coeff < CTM_COEFF_2_0) + coeffs[i] |= (7 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 8); + else + coeffs[i] |= (6 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 7); + } + + intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), + coeffs[0] << 16 | coeffs[1]); + intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), + coeffs[2] << 16); + + intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), + coeffs[3] << 16 | coeffs[4]); + intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), + coeffs[5] << 16); + + intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), + coeffs[6] << 16 | coeffs[7]); + intel_de_write(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), + coeffs[8] << 16); + + intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0); + intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0); + intel_de_write(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0); + + intel_de_write(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff); + intel_de_write(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff); + intel_de_write(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff); +} + /* FIXME input bpc? */ static const struct drm_color_lut_range d13_degamma_hdr[] = { /* segment 1 */ @@ -2343,7 +2420,12 @@ int intel_plane_color_init(struct drm_plane *plane) LUT_TYPE_DEGAMMA); dev_priv->display.load_plane_luts = d13_plane_load_luts; + dev_priv->display.load_plane_csc_matrix = icl_load_plane_csc_matrix; + drm_plane_attach_degamma_properties(plane); + + if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id)) + drm_plane_attach_ctm_property(plane); } return ret; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index aadb984fdf77..6ba670b6a5c9 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -965,6 +965,10 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, if (plane_state->uapi.degamma_lut) plane_color_ctl |= PLANE_PRE_CSC_GAMMA_ENABLE; + /* FIXME needs hw.ctm */ + if (plane_state->uapi.ctm) + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; + plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index df8500a86e9d..a8e35357aea0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7187,6 +7187,7 @@ enum { #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) +#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */ #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ #define PLANE_PRE_CSC_GAMMA_ENABLE (1 << 14) From patchwork Tue Jun 1 10:52:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F707C4708F for ; Tue, 1 Jun 2021 10:16:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1AA3D60FD8 for ; Tue, 1 Jun 2021 10:16:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1AA3D60FD8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D8C4C6EA04; Tue, 1 Jun 2021 10:16:35 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 899E56EA01; Tue, 1 Jun 2021 10:16:33 +0000 (UTC) IronPort-SDR: aVoIKHINOk+fsgAa8gV3nLivGAe+/AnP9p7PwyI+Va7++OdkA0QCFaZxYUCFUaa+SqQM1Y9FYa ZgPYnoKR2BXA== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550041" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550041" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:33 -0700 IronPort-SDR: 5orLAjv/frdVdZTfB/GgUZN94dVcWhCmhYzT52l/gAip4lEpXnP0WLePtsAXsOLEv/hGcQode5 TovJbICK6U/A== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431376" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:31 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 16/21] drm: Add Plane Gamma Mode property Date: Tue, 1 Jun 2021 16:22:13 +0530 Message-Id: <20210601105218.29185-17-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add Plane Gamma Mode as a blob property. This is an enum property with values as blob_id's and exposes the various gamma modes supported and the lut ranges. Getting the blob id in userspace, user can get the mode supported and also the range of gamma mode supported with number of lut coefficients. It can then set one of the modes using this enum property. Lut values will be sent through a separate GAMMA_LUT blob property. Signed-off-by: Uma Shankar Signed-off-by: Bhanuprakash Modem --- drivers/gpu/drm/drm_atomic_uapi.c | 4 ++++ drivers/gpu/drm/drm_color_mgmt.c | 26 ++++++++++++++++++++++++++ include/drm/drm_plane.h | 14 ++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 6af2afe362ff..6e3958491d10 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -612,6 +612,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == plane->gamma_mode_property) { + state->gamma_mode = val; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -685,6 +687,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane, state->degamma_lut->base.id : 0; } else if (property == plane->ctm_property) { *val = (state->ctm) ? state->ctm->base.id : 0; + } else if (property == plane->gamma_mode_property) { + *val = state->gamma_mode; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 5c3138497b9c..02367e691cf3 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -606,6 +606,13 @@ EXPORT_SYMBOL(drm_plane_create_color_properties); * Blob property which allows a userspace to provide CTM coefficients * to do color space conversion or any other enhancement by doing a * matrix multiplication using the h/w CTM processing engine + * + * gamma_mode_property: + * Blob property which advertizes the possible gamma modes and + * lut ranges supported by the platform. This allows userspace + * to query and get the plane gamma color caps and choose the + * appropriate gamma mode and create lut values accordingly + * */ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, struct drm_plane *plane, @@ -634,6 +641,13 @@ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, plane->ctm_property = prop; + prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, + "PLANE_GAMMA_MODE", num_values); + if (!prop) + return -ENOMEM; + + plane->gamma_mode_property = prop; + return 0; } EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties); @@ -664,6 +678,16 @@ void drm_plane_attach_ctm_property(struct drm_plane *plane) } EXPORT_SYMBOL(drm_plane_attach_ctm_property); +void drm_plane_attach_gamma_properties(struct drm_plane *plane) +{ + if (!plane->gamma_mode_property) + return; + + drm_object_attach_property(&plane->base, + plane->gamma_mode_property, 0); +} +EXPORT_SYMBOL(drm_plane_attach_gamma_properties); + int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges, @@ -676,6 +700,8 @@ int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, if (type == LUT_TYPE_DEGAMMA) prop = plane->degamma_mode_property; + else + prop = plane->gamma_mode_property; if (!prop) return -EINVAL; diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 4557f59cf3cf..a7b7c8599702 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -260,6 +260,13 @@ struct drm_plane_state { */ struct drm_property_blob *ctm; + /** + * @gamma_mode: This is a blob_id and exposes the platform capabilities + * wrt to various gamma modes and the respective lut ranges. This also + * helps user select a gamma mode amongst the supported ones. + */ + u32 gamma_mode; + u8 color_mgmt_changed : 1; }; @@ -791,6 +798,12 @@ struct drm_plane { * degamma LUT. */ struct drm_property *ctm_property; + + /** + * @gamma_mode_property: Optional Plane property to set the LUT + * used to convert the framebuffer's colors to non-linear gamma. + */ + struct drm_property *gamma_mode_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) @@ -887,6 +900,7 @@ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, int num_values); void drm_plane_attach_degamma_properties(struct drm_plane *plane); void drm_plane_attach_ctm_property(struct drm_plane *plane); +void drm_plane_attach_gamma_properties(struct drm_plane *plane); int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges, From patchwork Tue Jun 1 10:52:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF4AC47092 for ; Tue, 1 Jun 2021 10:16:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BCB3E61396 for ; Tue, 1 Jun 2021 10:16:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BCB3E61396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E2C36EA06; Tue, 1 Jun 2021 10:16:38 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5C0356EA06; Tue, 1 Jun 2021 10:16:36 +0000 (UTC) IronPort-SDR: JWu8HlbaV7utNd5cqB+NrS5Vs7Qd4KaH9kw42GO5DjNqUC4W8KWjjHelMuSs+EOUa9PG3hiKJ8 bj5gUvv5Lz+A== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550049" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550049" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:35 -0700 IronPort-SDR: asM4Jj+EGZuqvC/e0kBgQcJcyWtlbINVqHRkxR5AV5Kj6RdqDpLh1CdE5dtQp5B9s2oWGJBMzJ TK1LP/N4Ftbw== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431383" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:33 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 17/21] drm: Add Plane Gamma Lut property Date: Tue, 1 Jun 2021 16:22:14 +0530 Message-Id: <20210601105218.29185-18-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add Plane Gamma Lut as a blob property. Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++ drivers/gpu/drm/drm_atomic_uapi.c | 10 ++++++++++ drivers/gpu/drm/drm_color_mgmt.c | 18 ++++++++++++++++++ include/drm/drm_plane.h | 14 ++++++++++++++ 4 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index fafb8af1c9cb..7ddf6e4b956b 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -316,6 +316,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, drm_property_blob_get(state->degamma_lut); if (state->ctm) drm_property_blob_get(state->ctm); + if (state->gamma_lut) + drm_property_blob_get(state->gamma_lut); state->color_mgmt_changed = false; } @@ -366,6 +368,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_property_blob_put(state->fb_damage_clips); drm_property_blob_put(state->degamma_lut); drm_property_blob_put(state->ctm); + drm_property_blob_put(state->gamma_lut); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 6e3958491d10..4f5b7f76208d 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -614,6 +614,13 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, return ret; } else if (property == plane->gamma_mode_property) { state->gamma_mode = val; + } else if (property == plane->gamma_lut_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->gamma_lut, + val, -1, sizeof(struct drm_color_lut_ext), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (property == config->prop_fb_damage_clips) { ret = drm_atomic_replace_property_blob_from_id(dev, &state->fb_damage_clips, @@ -689,6 +696,9 @@ drm_atomic_plane_get_property(struct drm_plane *plane, *val = (state->ctm) ? state->ctm->base.id : 0; } else if (property == plane->gamma_mode_property) { *val = state->gamma_mode; + } else if (property == plane->gamma_lut_property) { + *val = (state->gamma_lut) ? + state->gamma_lut->base.id : 0; } else if (property == config->prop_fb_damage_clips) { *val = (state->fb_damage_clips) ? state->fb_damage_clips->base.id : 0; diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 02367e691cf3..b5b3ff7f654d 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -613,6 +613,11 @@ EXPORT_SYMBOL(drm_plane_create_color_properties); * to query and get the plane gamma color caps and choose the * appropriate gamma mode and create lut values accordingly * + * gamma_lut_property: + * Blob property which allows a userspace to provide LUT values + * to apply gamma curve using the h/w plane degamma processing + * engine, thereby making the content as non-linear. + * */ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, struct drm_plane *plane, @@ -648,6 +653,13 @@ int drm_plane_create_color_mgmt_properties(struct drm_device *dev, plane->gamma_mode_property = prop; + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "PLANE_GAMMA_LUT", 0); + if (!prop) + return -ENOMEM; + + plane->gamma_lut_property = prop; + return 0; } EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties); @@ -685,6 +697,12 @@ void drm_plane_attach_gamma_properties(struct drm_plane *plane) drm_object_attach_property(&plane->base, plane->gamma_mode_property, 0); + + if (!plane->gamma_lut_property) + return; + + drm_object_attach_property(&plane->base, + plane->gamma_lut_property, 0); } EXPORT_SYMBOL(drm_plane_attach_gamma_properties); diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index a7b7c8599702..8989bb1aa46c 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -267,6 +267,14 @@ struct drm_plane_state { */ u32 gamma_mode; + /* @gamma_lut: + * + * Lookup table for converting framebuffer pixel data after applying the + * color conversion matrix @ctm. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is an array of &struct drm_color_lut_ext. + */ + struct drm_property_blob *gamma_lut; + u8 color_mgmt_changed : 1; }; @@ -804,6 +812,12 @@ struct drm_plane { * used to convert the framebuffer's colors to non-linear gamma. */ struct drm_property *gamma_mode_property; + + /** + * @gamma_lut_property: Optional Plane property to set the LUT + * used to convert the framebuffer's colors to non-linear gamma. + */ + struct drm_property *gamma_lut_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) From patchwork Tue Jun 1 10:52:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37D0DC47097 for ; Tue, 1 Jun 2021 10:16:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0C526613D2 for ; Tue, 1 Jun 2021 10:16:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0C526613D2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32ECB6EA0A; Tue, 1 Jun 2021 10:16:39 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 61FF36EA06; Tue, 1 Jun 2021 10:16:37 +0000 (UTC) IronPort-SDR: NvO9uQR5mwC6INqbkEHOPBjH2mpsw4gQlglcF/qbEPbmuo47hoeBCX8WaEDDDkXuHQXwPLsAyl fBDvJhrHtNtA== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550052" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550052" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:37 -0700 IronPort-SDR: pr9z4WMQPXXzwLiVn+rVpvws1wSVMn01E0ttL3BFIYn4AG904ojQwbJ7D4Lt5446PI0sIeMaj2 4bfHYRugCTZw== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431397" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:35 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 18/21] drm/i915/xelpd: Define and Initialize Plane Gamma Lut range Date: Tue, 1 Jun 2021 16:22:15 +0530 Message-Id: <20210601105218.29185-19-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Define the structure with XE_LPD gamma lut ranges. HDR and SDR planes have different capabilities, implemented respective structure for the HDR planes. Degamma and GAMMA has same Lut caps for SDR planes, extended the same. Initialize the mode range caps as well. Signed-off-by: Uma Shankar Signed-off-by: Bhanuprakash Modem --- drivers/gpu/drm/i915/display/intel_color.c | 112 ++++++++++++++++++--- 1 file changed, 99 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 8b4f653b213d..7f091dd0bb19 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -2248,7 +2248,7 @@ static const struct drm_color_lut_range d13_degamma_hdr[] = { }; /* FIXME input bpc? */ -static const struct drm_color_lut_range d13_degamma_sdr[] = { +static const struct drm_color_lut_range d13_gamma_degamma_sdr[] = { /* segment 1 */ { .flags = (DRM_MODE_LUT_GAMMA | @@ -2298,6 +2298,63 @@ static const struct drm_color_lut_range d13_degamma_sdr[] = { }, }; + /* FIXME input bpc? */ +static const struct drm_color_lut_range d13_gamma_hdr[] = { + /* + * ToDo: Add Segment 1 + * There is an optional fine segment added with 9 lut values + * Will be added later + */ + + /* segment 2 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = (1 << 24) - 1, + .min = 0, .max = (1 << 24) - 1, + }, + /* segment 3 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 24) - 1, .end = 1 << 24, + .min = 0, .max = 1 << 24, + }, + /* Segment 4 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 1 << 24, .end = 3 << 24, + .min = 0, .max = (3 << 24), + }, + /* Segment 5 */ + { + .flags = (DRM_MODE_LUT_GAMMA | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 3 << 24, .end = 7 << 24, + .min = 0, .max = (7 << 24), + }, +}; + static void d13_program_plane_degamma_lut(const struct drm_plane_state *state, struct drm_color_lut_ext *degamma_lut, u32 offset) @@ -2407,26 +2464,55 @@ int intel_plane_color_init(struct drm_plane *plane) ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no degamma", NULL, 0, LUT_TYPE_DEGAMMA); - if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id)) + if (ret) + return ret; + + ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no gamma", + NULL, 0, + LUT_TYPE_GAMMA); + if (ret) + return ret; + + if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id)) { ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "plane degamma", d13_degamma_hdr, sizeof(d13_degamma_hdr), LUT_TYPE_DEGAMMA); - else - ret = drm_plane_color_add_gamma_degamma_mode_range(plane, - "plane degamma", - d13_degamma_sdr, - sizeof(d13_degamma_sdr), + if (ret) + return ret; + + ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "plane gamma", + d13_gamma_hdr, + sizeof(d13_gamma_hdr), + LUT_TYPE_GAMMA); + if (ret) + return ret; + } else { + ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "plane degamma", + d13_gamma_degamma_sdr, + sizeof(d13_gamma_degamma_sdr), LUT_TYPE_DEGAMMA); + if (ret) + return ret; + + ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "plane gamma", + d13_gamma_degamma_sdr, + sizeof(d13_gamma_degamma_sdr), + LUT_TYPE_GAMMA); + if (ret) + return ret; + } + } - dev_priv->display.load_plane_luts = d13_plane_load_luts; - dev_priv->display.load_plane_csc_matrix = icl_load_plane_csc_matrix; + dev_priv->display.load_plane_luts = d13_plane_load_luts; + dev_priv->display.load_plane_csc_matrix = icl_load_plane_csc_matrix; - drm_plane_attach_degamma_properties(plane); + drm_plane_attach_degamma_properties(plane); - if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id)) - drm_plane_attach_ctm_property(plane); - } + if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id)) + drm_plane_attach_ctm_property(plane); + + drm_plane_attach_gamma_properties(plane); return ret; } From patchwork Tue Jun 1 10:52:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4982CC4708F for ; Tue, 1 Jun 2021 10:16:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 12C7F613AB for ; Tue, 1 Jun 2021 10:16:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 12C7F613AB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 086846EA0E; Tue, 1 Jun 2021 10:16:42 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 831766EA08; Tue, 1 Jun 2021 10:16:39 +0000 (UTC) IronPort-SDR: 25YwmkxKAlTc9MdPc9NSQe31EBJ80ecDcu9z/hPyIFNJ/Q7MaHWeO/rS+q336O72fV3F9fM8ZA QMIn2aMAfrmg== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550060" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550060" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:39 -0700 IronPort-SDR: 8PQDJpI9wHE5Ho1IKuZeoZDNf0VIwLVwW7c7e5XTn72WvshH8JvEcpvZgEYqsFMO5unuRDKEcx Mzkcn5F/nnBw== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431408" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:37 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 19/21] drm/i915/xelpd: Add register definitions for Plane Gamma Date: Tue, 1 Jun 2021 16:22:16 +0530 Message-Id: <20210601105218.29185-20-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add macros to define Plane Gamma registers Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 73 +++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a8e35357aea0..2ebc92104f64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -11398,6 +11398,79 @@ enum skl_power_gate { _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \ _PLANE_PRE_CSC_GAMC_DATA_2(pipe)) +/* Display13 Plane Gamma Reg */ +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A 0x70160 +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B 0x71160 +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A 0x70260 +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B 0x71260 +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \ + _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \ + _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B) +#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \ + _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A 0x70164 +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B 0x71164 +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A 0x70264 +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B 0x71264 +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \ + _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \ + _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B) +#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \ + _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701d8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711d8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702d8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712d8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \ + _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \ + _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B) +#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \ + _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701dc +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711dc +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702dc +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712dc +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \ + _PLANE_POST_CSC_GAMC_DATA_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \ + _PLANE_POST_CSC_GAMC_DATA_ENH_2_B) +#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \ + _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_INDEX_1_A 0x704d8 +#define _PLANE_POST_CSC_GAMC_INDEX_1_B 0x714d8 +#define _PLANE_POST_CSC_GAMC_INDEX_2_A 0x705d8 +#define _PLANE_POST_CSC_GAMC_INDEX_2_B 0x715d8 +#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_1_A, \ + _PLANE_POST_CSC_GAMC_INDEX_1_B) +#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_2_A, \ + _PLANE_POST_CSC_GAMC_INDEX_2_B) +#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \ + _PLANE_POST_CSC_GAMC_INDEX_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_DATA_1_A 0x704dc +#define _PLANE_POST_CSC_GAMC_DATA_1_B 0x714dc +#define _PLANE_POST_CSC_GAMC_DATA_2_A 0x705dc +#define _PLANE_POST_CSC_GAMC_DATA_2_B 0x715dc +#define _PLANE_POST_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_1_A, \ + _PLANE_POST_CSC_GAMC_DATA_1_B) +#define _PLANE_POST_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_2_A, \ + _PLANE_POST_CSC_GAMC_DATA_2_B) +#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_1(pipe), \ + _PLANE_POST_CSC_GAMC_DATA_2(pipe)) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) From patchwork Tue Jun 1 10:52:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12291001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2B58C47093 for ; Tue, 1 Jun 2021 10:16:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8038F60FD8 for ; Tue, 1 Jun 2021 10:16:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8038F60FD8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E526B6EA08; Tue, 1 Jun 2021 10:16:42 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 890026EA08; Tue, 1 Jun 2021 10:16:41 +0000 (UTC) IronPort-SDR: zxTOGIIu6gPSOJ/5/hvW1eDp7HhmxoCETwiNrpRLRBtTwpf1Si9fmyJeYrCT1kJyl1NOKKg6ur ScTizE7DsWqg== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550062" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550062" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:41 -0700 IronPort-SDR: NFIyOqh37A/hZB3JVLRJ+RHPA3ff38t+vy7/D46tzCsB9XyBtHeOCEb5s/SxfRcCuQ3dTdy7IJ C1KueyolHWEA== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431425" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:39 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 20/21] drm/i915/xelpd: Program Plane Gamma Registers Date: Tue, 1 Jun 2021 16:22:17 +0530 Message-Id: <20210601105218.29185-21-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Extract the LUT and program plane gamma registers. Enabled multi segmented lut as well. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 89 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 9 ++- 2 files changed, 94 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 7f091dd0bb19..daf2148fb2df 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -27,6 +27,9 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_sprite.h" + +#include "skl_universal_plane.h" + #include #define CTM_COEFF_SIGN (1ULL << 63) @@ -2434,16 +2437,102 @@ static void d13_program_plane_degamma_lut(const struct drm_plane_state *state, } } +static void d13_program_plane_gamma_lut(const struct drm_plane_state *state, + struct drm_color_lut_ext *gamma_lut, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u32 i, lut_size; + + if (icl_is_hdr_plane(dev_priv, plane)) { + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), + offset | PLANE_PAL_PREC_AUTO_INCREMENT); + if (gamma_lut) { + lut_size = 32; + for (i = 0; i < lut_size; i++) { + u64 word = drm_color_lut_extract_ext(gamma_lut[i].green, 24); + u32 lut_val = (word & 0xffffff); + + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), + lut_val); + } + + do { + /* Program the max register to clamp values > 1.0. */ + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), + gamma_lut[i].green); + } while (i++ < 34); + } else { + lut_size = 32; + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); + } + + do { + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), + 1 << 24); + } while (i++ < 34); + } + + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); + } else { + lut_size = 32; + /* + * First 3 planes are HDR, so reduce by 3 to get to the right + * SDR plane offset + */ + plane = plane - 3; + + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX(pipe, plane, 0), + offset | PLANE_PAL_PREC_AUTO_INCREMENT); + + if (gamma_lut) { + for (i = 0; i < lut_size; i++) + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), + gamma_lut[i].green & 0xffff); + /* Program the max register to clamp values > 1.0. */ + while (i < 35) + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), + gamma_lut[i++].green & 0x3ffff); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1); + + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), v); + } + + do { + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + } while (i++ < 34); + } + + intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX(pipe, plane, 0), 0); + } +} + static void d13_plane_load_luts(const struct drm_plane_state *plane_state) { const struct drm_property_blob *degamma_lut_blob = plane_state->degamma_lut; + const struct drm_property_blob *gamma_lut_blob = + plane_state->gamma_lut; struct drm_color_lut_ext *degamma_lut = NULL; + struct drm_color_lut_ext *gamma_lut = NULL; if (degamma_lut_blob) { degamma_lut = degamma_lut_blob->data; d13_program_plane_degamma_lut(plane_state, degamma_lut, 0); } + + if (gamma_lut_blob) { + gamma_lut = gamma_lut_blob->data; + d13_program_plane_gamma_lut(plane_state, gamma_lut, 0); + } } void intel_color_load_plane_luts(const struct drm_plane_state *plane_state) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2ebc92104f64..6ab4adbe7f56 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7187,10 +7187,11 @@ enum { #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) -#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */ -#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ -#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ -#define PLANE_PRE_CSC_GAMMA_ENABLE (1 << 14) +#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */ +#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ +#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ +#define PLANE_POST_CSC_GAMMA_MULTI_SEGMENT_ENABLE (1 << 15) +#define PLANE_PRE_CSC_GAMMA_ENABLE (1 << 14) #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17) #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) From patchwork Tue Jun 1 10:52:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12291003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36FE6C47092 for ; Tue, 1 Jun 2021 10:16:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B3B261396 for ; Tue, 1 Jun 2021 10:16:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0B3B261396 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DDB0C6EA16; Tue, 1 Jun 2021 10:16:45 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 66E3B6EA0F; Tue, 1 Jun 2021 10:16:43 +0000 (UTC) IronPort-SDR: 07vvwqMoAlEROzACjpyT/hkTdRDJHaUpD8E/N3f4kD0KocC3vWZhEyOrnx3dumyoHMQn2Edy3o UK9B2F3Ly8ZQ== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="203550063" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="203550063" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:43 -0700 IronPort-SDR: bHqSmD5y0kbxtCAFVm05bFgxofmHqJWvUpqw4I+xw+6osEVK0ZIrz2MJ44873/dsMJQ64cvwUP 1JosHPK1AaxQ== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="482431431" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:16:41 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 21/21] drm/i915/xelpd: Enable plane gamma Date: Tue, 1 Jun 2021 16:22:18 +0530 Message-Id: <20210601105218.29185-22-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601105218.29185-1-uma.shankar@intel.com> References: <20210601105218.29185-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable plane gamma feature in check callbacks. Decide based on the user input. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 6ba670b6a5c9..5d527d12ec45 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -959,7 +959,9 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); u32 plane_color_ctl = 0; - plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; + /* FIXME needs hw.gamma_lut */ + if (!plane_state->uapi.gamma_lut) + plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; /* FIXME needs hw.degamma_lut */ if (plane_state->uapi.degamma_lut)