From patchwork Tue Jun 1 20:10:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 12292177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 364DFC47080 for ; Tue, 1 Jun 2021 20:10:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19E3A613DD for ; Tue, 1 Jun 2021 20:10:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234656AbhFAUMQ (ORCPT ); Tue, 1 Jun 2021 16:12:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234638AbhFAUMP (ORCPT ); Tue, 1 Jun 2021 16:12:15 -0400 Received: from mail-oo1-xc30.google.com (mail-oo1-xc30.google.com [IPv6:2607:f8b0:4864:20::c30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75A37C06174A for ; Tue, 1 Jun 2021 13:10:31 -0700 (PDT) Received: by mail-oo1-xc30.google.com with SMTP id j17-20020a4ad6d10000b02901fef5280522so84953oot.0 for ; Tue, 01 Jun 2021 13:10:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QcUUMExtnu0Erc+KV6ZLS5k3H19BD2zY2/L6Th+LVvs=; b=HYrYh1I8tDUYUIrssrpdcJcKrijkLQvDplLmwbrnKEolJDbNUacH0VTBj7j0+iK9ZR 0iqS2Pfr/gQmDjBIyokiAchJiyicRqeWhbna9R0TZM6Ne2G4mYxIUHW5isEyuOfzBmAv 6/vrPBowiFxMhcieAa0tO5HIWEeRGPmvt2WYlk4vuzbMV0YX4muMq4g1dvJcxpHdg1Xm OX4rHlEIru0aL9KjhJ76RbUF8m2An45FTkVNln8cs//jeUiirRVsZ/8gyXuJHFbP6JaB yVVRl/J6OY3N1wg/5ujle+Pptdw87jDeNzvgzaigWVy9sKocS5QmkDNOlAPdLUM8X4fv v7uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QcUUMExtnu0Erc+KV6ZLS5k3H19BD2zY2/L6Th+LVvs=; b=qP2ZzB2gchYEtj5X+jICJIhXP1rulGR++OAGnfEotnfsXyjYSDM3QlhGOStSLY08t2 zM/QnpbOr2zHKKQVR9FMmg5VRQ4YLyBxmeGKKUITlpiyL4C8Gki5SfoMYPfzBlk6sgqr 9GpY8zUv8EunU/XNJYX2tZd/UiINiR95rKoQLmVIRpjSeeulD1s/ncVm3uwMJpfqnU57 8FF+zTmapht9NUNyMMF5YBwJNOe9zPlG8i7GgNHszSAEFvw1hvyT+0QS9bGbK5agXSPJ BL6k4zTVen0CX3TRMIpUgns/zjkBu0zN2ACLWlknhDgz+KnMJuTFbEctrxsrH0SXXNeg hMmQ== X-Gm-Message-State: AOAM5305jS1zal3lu1Bk4DCGZ+7zqKsrdoG9rCqTBdx9b92IM19hXS/H u+4S08mVTtD+jkFrJMjNlN3liK6pBbI= X-Google-Smtp-Source: ABdhPJyfYNvCuMl5zFmhxki/Kb1XoDS0IsWbq1QMPdOCAgCmGmZJWjuBvTeJiTPly57HWh9iMUewXw== X-Received: by 2002:a4a:d809:: with SMTP id f9mr15514840oov.71.1622578230370; Tue, 01 Jun 2021 13:10:30 -0700 (PDT) Received: from wintermute.localdomain (cpe-76-183-134-35.tx.res.rr.com. [76.183.134.35]) by smtp.gmail.com with ESMTPSA id p25sm468118ood.4.2021.06.01.13.10.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jun 2021 13:10:29 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [PATCH v3 1/4] dt-bindings: rockchip-sfc: Bindings for Rockchip serial flash controller Date: Tue, 1 Jun 2021 15:10:18 -0500 Message-Id: <20210601201021.4406-2-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601201021.4406-1-macroalpha82@gmail.com> References: <20210601201021.4406-1-macroalpha82@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Chris Morgan Add bindings for the Rockchip serial flash controller. New device specific parameter of rockchip,sfc-no-dma included in documentation. Signed-off-by: Chris Morgan --- .../devicetree/bindings/spi/rockchip,sfc.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/rockchip,sfc.yaml diff --git a/Documentation/devicetree/bindings/spi/rockchip,sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip,sfc.yaml new file mode 100644 index 000000000000..d5f8edd621ae --- /dev/null +++ b/Documentation/devicetree/bindings/spi/rockchip,sfc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/rockchip,sfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Serial Flash Controller (SFC) + +maintainers: + - Heiko Stuebner + - Chris Morgan + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + oneOf: + - const: rockchip,px30-sfc + - const: rockchip,rk1806-sfc + - const: rockchip,rk1808-sfc + - const: rockchip,rk312x-sfc + - const: rockchip,rk3308-sfc + - const: rockchip,rv1108-sfc + - items: + - const: rockchip,rk3036-sfc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + items: + - const: ahb + - const: sfc + + power-domains: + maxItems: 1 + + rockchip,sfc-no-dma: + vendor,bool-property: + descrption: Boolean value for disabling DMA + type: boolean + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + sfc: spi@ff3a0000 { + compatible = "rockchip,px30-sfc","rockchip,rk3036-sfc"; + reg = <0x0 0xff3a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "sfc", "ahb"; + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; + pinctrl-names = "default"; + power-domains = <&power PX30_PD_MMC_NAND>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <108000000>; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; + }; + +... From patchwork Tue Jun 1 20:10:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 12292183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C8FCC47096 for ; Tue, 1 Jun 2021 20:10:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F36E4613DD for ; Tue, 1 Jun 2021 20:10:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234684AbhFAUMR (ORCPT ); Tue, 1 Jun 2021 16:12:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234513AbhFAUMQ (ORCPT ); Tue, 1 Jun 2021 16:12:16 -0400 Received: from mail-oi1-x229.google.com (mail-oi1-x229.google.com [IPv6:2607:f8b0:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 044B9C061756 for ; Tue, 1 Jun 2021 13:10:33 -0700 (PDT) Received: by mail-oi1-x229.google.com with SMTP id v142so135805oie.9 for ; Tue, 01 Jun 2021 13:10:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GvHDvO42zm+LGIZt6ODU7o5NKP34l0hqjz1XHn+RlvM=; b=K1itZtzq86Jz/ISJgR2PR7Vh7/esGCvzy5n+E08+JJ8i203PFsetfCQCjwVAPySK0Q nhMtA94PMl5dWus5cZzQ3i4/CFPUx6QCgZh6dQHQ0AmIZQxk2JMLRKkklB1vig0/XOi/ x4xOuQKsZcEeEVayv21Lq1m55USnoQ+VG2XP02aqjvrBuOV3mtCWud2JjWkYvpwTz590 X46VBnRIEae1hGpqHfaSy8MOLqaBm6XeiNolGNb/bQav77HtATxoOH+ArjlojcHZxCwU S5J4pOACC6FzwiY0ubVUiyr+j4uMfFnAdizB4GS+i+1gtExrH8+/qqOI4yl9gLRwAlAa Qlnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GvHDvO42zm+LGIZt6ODU7o5NKP34l0hqjz1XHn+RlvM=; b=FwZkZwfY6zpuPGwfntTiwEYyyYSejyLgy4h97uoVYDM2NkxKUuAdE7x+Gk6VoJaXEt XlYjJJX3T60El9mMPdVPwIkJYs7B2CF105g1SDLVWzKwfI6p/BqFJZ19I0rBJAngnerQ JsW5mpY21dwaH27R/gGV6yMhiIesJthaGxKk1SiwkEAKbS+km/KI+LwqCU9yO3OAdrPm Rf+wYCqGWLhFXx2D00EAEw5262yilFpRlPrhKx3JMAos60tBbjccLnzI4BAkcsNzVgq1 uwIsYJpHiXC0xDAGm3FbydONWaLlYTZ4FHBptWGZupl7kuP5LFDDrTIpdru/77fggdvv FiVg== X-Gm-Message-State: AOAM533DLyU8x0YiG2LEBCgwu5fpqw31ObsQm7jzAhjkeGMOrhosCVAf WylB+1g7+Eo0AOao4yyS4sZ4jWcWZgA= X-Google-Smtp-Source: ABdhPJwh6Bp8LrSHqRxd5Mxwyl/abH0eE+J3jqMrbl2iQw4djhqNWq1ZnSyhxe6BZmHLiPtkE96ezA== X-Received: by 2002:aca:d417:: with SMTP id l23mr19304680oig.97.1622578231679; Tue, 01 Jun 2021 13:10:31 -0700 (PDT) Received: from wintermute.localdomain (cpe-76-183-134-35.tx.res.rr.com. [76.183.134.35]) by smtp.gmail.com with ESMTPSA id p25sm468118ood.4.2021.06.01.13.10.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jun 2021 13:10:31 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [PATCH v3 2/4] spi: rockchip-sfc: add rockchip serial flash controller driver Date: Tue, 1 Jun 2021 15:10:19 -0500 Message-Id: <20210601201021.4406-3-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601201021.4406-1-macroalpha82@gmail.com> References: <20210601201021.4406-1-macroalpha82@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Chris Morgan Add the rockchip serial flash controller (SFC) driver. Signed-off-by: Chris Morgan --- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-rockchip-sfc.c | 861 +++++++++++++++++++++++++++++++++ 3 files changed, 871 insertions(+) create mode 100644 drivers/spi/spi-rockchip-sfc.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f4481fe48bf0..4d81ba7841e2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -658,6 +658,15 @@ config SPI_ROCKCHIP The main usecase of this controller is to use spi flash as boot device. +config SPI_ROCKCHIP_SFC + tristate "Rockchip Serial Flash Controller (SFC)" + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on HAS_IOMEM && HAS_DMA + help + This enables support for Rockchip serial flash controller. This + is a specialized controller used to access SPI flash on some + Rockchip SOCs. + config SPI_RB4XX tristate "Mikrotik RB4XX SPI master" depends on SPI_MASTER && ATH79 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 13e54c45e9df..699db95c8441 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o obj-$(CONFIG_SPI_QUP) += spi-qup.o obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o +obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c new file mode 100644 index 000000000000..c039f96d2327 --- /dev/null +++ b/drivers/spi/spi-rockchip-sfc.c @@ -0,0 +1,861 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Rockchip Serial Flash Controller Driver + * + * Copyright (c) 2017, Rockchip Inc. + * Author: Shawn Lin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* System control */ +#define SFC_CTRL 0x0 +#define SFC_CTRL_COMMON_BITS_1 0x0 +#define SFC_CTRL_COMMON_BITS_2 0x1 +#define SFC_CTRL_COMMON_BITS_4 0x2 +#define SFC_CTRL_DATA_BITS_SHIFT 12 +#define SFC_CTRL_ADDR_BITS_SHIFT 10 +#define SFC_CTRL_CMD_BITS_SHIFT 8 +#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) + +/* Interrupt mask */ +#define SFC_IMR 0x4 +#define SFC_IMR_RX_FULL BIT(0) +#define SFC_IMR_RX_UFLOW BIT(1) +#define SFC_IMR_TX_OFLOW BIT(2) +#define SFC_IMR_TX_EMPTY BIT(3) +#define SFC_IMR_TRAN_FINISH BIT(4) +#define SFC_IMR_BUS_ERR BIT(5) +#define SFC_IMR_NSPI_ERR BIT(6) +#define SFC_IMR_DMA BIT(7) + +/* Interrupt clear */ +#define SFC_ICLR 0x8 +#define SFC_ICLR_RX_FULL BIT(0) +#define SFC_ICLR_RX_UFLOW BIT(1) +#define SFC_ICLR_TX_OFLOW BIT(2) +#define SFC_ICLR_TX_EMPTY BIT(3) +#define SFC_ICLR_TRAN_FINISH BIT(4) +#define SFC_ICLR_BUS_ERR BIT(5) +#define SFC_ICLR_NSPI_ERR BIT(6) +#define SFC_ICLR_DMA BIT(7) + +/* FIFO threshold level */ +#define SFC_FTLR 0xc +#define SFC_FTLR_TX_SHIFT 0 +#define SFC_FTLR_TX_MASK 0x1f +#define SFC_FTLR_RX_SHIFT 8 +#define SFC_FTLR_RX_MASK 0x1f + +/* Reset FSM and FIFO */ +#define SFC_RCVR 0x10 +#define SFC_RCVR_RESET BIT(0) + +/* Enhanced mode */ +#define SFC_AX 0x14 + +/* Address Bit number */ +#define SFC_ABIT 0x18 + +/* Interrupt status */ +#define SFC_ISR 0x1c +#define SFC_ISR_RX_FULL_SHIFT BIT(0) +#define SFC_ISR_RX_UFLOW_SHIFT BIT(1) +#define SFC_ISR_TX_OFLOW_SHIFT BIT(2) +#define SFC_ISR_TX_EMPTY_SHIFT BIT(3) +#define SFC_ISR_TX_FINISH_SHIFT BIT(4) +#define SFC_ISR_BUS_ERR_SHIFT BIT(5) +#define SFC_ISR_NSPI_ERR_SHIFT BIT(6) +#define SFC_ISR_DMA_SHIFT BIT(7) + +/* FIFO status */ +#define SFC_FSR 0x20 +#define SFC_FSR_TX_IS_FULL BIT(0) +#define SFC_FSR_TX_IS_EMPTY BIT(1) +#define SFC_FSR_RX_IS_EMPTY BIT(2) +#define SFC_FSR_RX_IS_FULL BIT(3) +#define SFC_FSR_TXLV_MASK GENMASK(12, 8) +#define SFC_FSR_TXLV_SHIFT 8 +#define SFC_FSR_RXLV_MASK GENMASK(20, 16) +#define SFC_FSR_RXLV_SHIFT 16 + +/* FSM status */ +#define SFC_SR 0x24 +#define SFC_SR_IS_IDLE 0x0 +#define SFC_SR_IS_BUSY 0x1 + +/* Raw interrupt status */ +#define SFC_RISR 0x28 +#define SFC_RISR_RX_FULL BIT(0) +#define SFC_RISR_RX_UNDERFLOW BIT(1) +#define SFC_RISR_TX_OVERFLOW BIT(2) +#define SFC_RISR_TX_EMPTY BIT(3) +#define SFC_RISR_TRAN_FINISH BIT(4) +#define SFC_RISR_BUS_ERR BIT(5) +#define SFC_RISR_NSPI_ERR BIT(6) +#define SFC_RISR_DMA BIT(7) + +/* Master trigger */ +#define SFC_DMA_TRIGGER 0x80 + +/* Src or Dst addr for master */ +#define SFC_DMA_ADDR 0x84 + +/* Command */ +#define SFC_CMD 0x100 +#define SFC_CMD_IDX_SHIFT 0 +#define SFC_CMD_DUMMY_SHIFT 8 +#define SFC_CMD_DIR_RD 0 +#define SFC_CMD_DIR_WR 1 +#define SFC_CMD_DIR_SHIFT 12 +#define SFC_CMD_ADDR_ZERO (0x0 << 14) +#define SFC_CMD_ADDR_24BITS (0x1 << 14) +#define SFC_CMD_ADDR_32BITS (0x2 << 14) +#define SFC_CMD_ADDR_FRS (0x3 << 14) +#define SFC_CMD_TRAN_BYTES_SHIFT 16 +#define SFC_CMD_CS_SHIFT 30 + +/* Address */ +#define SFC_ADDR 0x104 + +/* Data */ +#define SFC_DATA 0x108 + +/* The controller and documentation reports that it supports up to 4 CS + * devices (0-3), however I have only been able to test a single CS (CS 0) + * due to the configuration of my device. + */ +#define SFC_MAX_CHIPSELECT_NUM 4 + +/* The SFC can transfer max 16KB - 1 at one time + * we set it to 15.5KB here for alignment. + */ +#define SFC_MAX_TRANS_BYTES (512 * 31) + +/* Maximum clock values from datasheet suggest keeping clock value under + * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver + * has a minimum of 10MHz and a default of 80MHz which seems reasonable. + */ +#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000) +#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000) +#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000) + +#define SFC_CMD_DUMMY(x) \ + ((x) << SFC_CMD_DUMMY_SHIFT) + +enum rockchip_sfc_iftype { + IF_TYPE_STD, + IF_TYPE_DUAL, + IF_TYPE_QUAD, +}; + +struct rockchip_sfc; +struct rockchip_sfc_chip_priv { + u8 cs; + u32 clk_rate; + struct rockchip_sfc *sfc; +}; + +struct rockchip_sfc { + struct device *dev; + void __iomem *regbase; + struct clk *hclk; + struct clk *clk; + /* virtual mapped addr for dma_buffer */ + void *buffer; + dma_addr_t dma_buffer; + struct completion cp; + struct rockchip_sfc_chip_priv flash[SFC_MAX_CHIPSELECT_NUM]; + u8 num_chip; + bool use_dma; +}; + +static int rockchip_sfc_get_if_type(const struct spi_mem_op *op, + struct rockchip_sfc *sfc) +{ + if (op->data.buswidth == 2) + return IF_TYPE_DUAL; + else if (op->data.buswidth == 4) + return IF_TYPE_QUAD; + else if (op->data.buswidth == 1) + return IF_TYPE_STD; + + dev_err(sfc->dev, "unsupported SPI read mode\n"); + + return -EINVAL; +} + +static int rockchip_sfc_reset(struct rockchip_sfc *sfc) +{ + int err; + u32 status; + + writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); + + err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, + !(status & SFC_RCVR_RESET), 20, + jiffies_to_usecs(HZ)); + if (err) + dev_err(sfc->dev, "SFC reset never finished\n"); + + /* Still need to clear the masked interrupt from RISR */ + writel_relaxed(SFC_ICLR_RX_FULL | SFC_ICLR_RX_UFLOW | + SFC_ICLR_TX_OFLOW | SFC_ICLR_TX_EMPTY | + SFC_ICLR_TRAN_FINISH | SFC_ICLR_BUS_ERR | + SFC_ICLR_NSPI_ERR | SFC_ICLR_DMA, + sfc->regbase + SFC_ICLR); + + dev_dbg(sfc->dev, "reset\n"); + + return err; +} + +static int rockchip_sfc_init(struct rockchip_sfc *sfc) +{ + int err; + + err = clk_set_rate(sfc->clk, SFC_DEFAULT_SPEED_HZ); + if (err) + return err; + + err = rockchip_sfc_reset(sfc); + if (err) + return err; + + /* Mask all eight interrupts */ + writel_relaxed(0xff, sfc->regbase + SFC_IMR); + + writel_relaxed(SFC_CTRL_PHASE_SEL_NEGETIVE, sfc->regbase + SFC_CTRL); + + return 0; +} + +static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr) +{ + u32 fsr = readl_relaxed(sfc->regbase + SFC_FSR); + int level; + + if (wr) + level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; + else + level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; + + return level; +} + +static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout) +{ + unsigned long deadline = jiffies + timeout; + int level; + + while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) { + if (time_after_eq(jiffies, deadline)) { + dev_warn(sfc->dev, "%s fifo timeout\n", wr ? "write" : "read"); + return -ETIMEDOUT; + } + udelay(1); + } + + return level; +} + +/* The SFC_CTRL register is a global control register, + * when the controller is in busy state(SFC_SR), + * SFC_CTRL cannot be set. + */ +static void rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, u32 timeout_us) +{ + u32 status; + int ret; + + ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, + !(status & SFC_SR_IS_BUSY), + 20, timeout_us); + if (ret) { + dev_err(sfc->dev, "wait sfc idle timeout\n"); + rockchip_sfc_reset(sfc); + } +} + +static void rockchip_sfc_setup_ctrl(struct rockchip_sfc *sfc) +{ + u32 reg; + + reg = IF_TYPE_STD << SFC_CTRL_DATA_BITS_SHIFT; + reg |= IF_TYPE_STD << SFC_CTRL_ADDR_BITS_SHIFT; + reg |= IF_TYPE_STD << SFC_CTRL_CMD_BITS_SHIFT; + reg |= SFC_CTRL_PHASE_SEL_NEGETIVE; + + rockchip_sfc_wait_idle(sfc, 10000); + + writel_relaxed(reg, sfc->regbase + SFC_CTRL); +} + +static int rockchip_sfc_op_reg(struct rockchip_sfc_chip_priv *priv, + u8 opcode, int len, u8 optype) +{ + struct rockchip_sfc *sfc = priv->sfc; + u32 reg; + + rockchip_sfc_setup_ctrl(sfc); + + reg = opcode << SFC_CMD_IDX_SHIFT; + reg |= len << SFC_CMD_TRAN_BYTES_SHIFT; + reg |= priv->cs << SFC_CMD_CS_SHIFT; + reg |= optype << SFC_CMD_DIR_SHIFT; + writel_relaxed(reg, sfc->regbase + SFC_CMD); + + return 0; +} + +static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) +{ + u8 bytes = len & 0x3; + u32 dwords; + int tx_level; + u32 write_words; + u32 tmp = 0; + + dwords = len >> 2; + while (dwords) { + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, HZ); + if (tx_level < 0) + return tx_level; + write_words = min_t(u32, tx_level, dwords); + iowrite32_rep(sfc->regbase + SFC_DATA, buf, write_words); + buf += write_words << 2; + dwords -= write_words; + } + + /* write the rest non word aligned bytes */ + if (bytes) { + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, HZ); + if (tx_level < 0) + return tx_level; + memcpy(&tmp, buf, bytes); + writel_relaxed(tmp, sfc->regbase + SFC_DATA); + } + + return len; +} + +static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) +{ + u8 bytes = len & 0x3; + u32 dwords; + u8 read_words; + int rx_level; + int tmp; + + /* word aligned access only */ + dwords = len >> 2; + while (dwords) { + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, HZ); + if (rx_level < 0) + return rx_level; + read_words = min_t(u32, rx_level, dwords); + ioread32_rep(sfc->regbase + SFC_DATA, buf, read_words); + buf += read_words << 2; + dwords -= read_words; + } + + /* read the rest non word aligned bytes */ + if (bytes) { + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, HZ); + if (rx_level < 0) + return rx_level; + tmp = readl_relaxed(sfc->regbase + SFC_DATA); + memcpy(buf, &tmp, bytes); + } + + return len; +} + +static int rockchip_sfc_read_reg(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = priv->sfc; + int ret; + int trans; + size_t n_rx = op->data.nbytes; + u8 opcode = op->cmd.opcode; + u8 *rxbuf = op->data.buf.in; + + trans = min_t(int, n_rx, SFC_MAX_TRANS_BYTES); + ret = rockchip_sfc_op_reg(priv, opcode, trans, SFC_CMD_DIR_RD); + if (ret) + return ret; + + ret = rockchip_sfc_read_fifo(sfc, rxbuf, trans); + if (ret < 0) + return ret; + + return 0; +} + +static int rockchip_sfc_write_reg(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = priv->sfc; + int ret; + size_t n_tx = op->data.nbytes; + u8 opcode = op->cmd.opcode; + const u8 *txbuf = op->data.buf.out; + + ret = rockchip_sfc_op_reg(priv, opcode, n_tx, SFC_CMD_DIR_WR); + if (ret) + return ret; + ret = rockchip_sfc_write_fifo(sfc, txbuf, n_tx); + if (ret < 0) + return ret; + + return 0; +} + +static int rockchip_sfc_setup_transfer(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, + loff_t from_to, size_t len, u8 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + u8 if_type = IF_TYPE_STD; + u8 addr_width = op->addr.nbytes; + u8 read_dummy_bits = op->dummy.nbytes << 3; + u32 reg; + + if (op_type == SFC_CMD_DIR_RD) + if_type = rockchip_sfc_get_if_type(op, sfc); + + rockchip_sfc_wait_idle(sfc, 10000); + + writel_relaxed((if_type << SFC_CTRL_DATA_BITS_SHIFT) | + (IF_TYPE_STD << SFC_CTRL_ADDR_BITS_SHIFT) | + (IF_TYPE_STD << SFC_CTRL_CMD_BITS_SHIFT) | + SFC_CTRL_PHASE_SEL_NEGETIVE, + sfc->regbase + SFC_CTRL); + + reg = op->cmd.opcode << SFC_CMD_IDX_SHIFT; + + reg |= op_type << SFC_CMD_DIR_SHIFT; + reg |= (addr_width == 4) ? + SFC_CMD_ADDR_32BITS : SFC_CMD_ADDR_24BITS; + + reg |= priv->cs << SFC_CMD_CS_SHIFT; + reg |= len << SFC_CMD_TRAN_BYTES_SHIFT; + + if (op_type == SFC_CMD_DIR_RD) + reg |= SFC_CMD_DUMMY(read_dummy_bits); + + writel_relaxed(reg, sfc->regbase + SFC_CMD); + writel_relaxed(from_to, sfc->regbase + SFC_ADDR); + + return 0; +} + +static int rockchip_sfc_do_dma_transfer(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, loff_t from_to, + dma_addr_t dma_buf, size_t len, u8 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + u32 reg; + int err = 0; + + init_completion(&sfc->cp); + + writel_relaxed(SFC_ICLR_RX_FULL | SFC_ICLR_RX_UFLOW | + SFC_ICLR_TX_OFLOW | SFC_ICLR_TX_EMPTY | + SFC_ICLR_TRAN_FINISH | SFC_ICLR_BUS_ERR | + SFC_ICLR_NSPI_ERR | SFC_ICLR_DMA, + sfc->regbase + SFC_ICLR); + + /* Enable transfer complete interrupt */ + reg = readl_relaxed(sfc->regbase + SFC_IMR); + reg &= ~SFC_IMR_TRAN_FINISH; + writel_relaxed(reg, sfc->regbase + SFC_IMR); + + err = rockchip_sfc_setup_transfer(priv, op, from_to, len, op_type); + if (err < 0) + return err; + + writel_relaxed(dma_buf, sfc->regbase + SFC_DMA_ADDR); + + /* + * Start dma but note that the sfc->dma_buffer is derived from + * dmam_alloc_coherent so we don't actually need any sync operations + * for coherent dma memory. + */ + writel(0x1, sfc->regbase + SFC_DMA_TRIGGER); + + /* Wait for the interrupt. */ + if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) { + dev_err(sfc->dev, "DMA wait for transfer finish timeout\n"); + err = -ETIMEDOUT; + } + + writel_relaxed(SFC_ICLR_RX_FULL | SFC_ICLR_RX_UFLOW | + SFC_ICLR_TX_OFLOW | SFC_ICLR_TX_EMPTY | + SFC_ICLR_TRAN_FINISH | SFC_ICLR_BUS_ERR | + SFC_ICLR_NSPI_ERR | SFC_ICLR_DMA, + sfc->regbase + SFC_ICLR); + /* Disable transfer finish interrupt */ + reg = readl_relaxed(sfc->regbase + SFC_IMR); + reg |= SFC_IMR_TRAN_FINISH; + writel_relaxed(reg, sfc->regbase + SFC_IMR); + + if (err) { + rockchip_sfc_reset(sfc); + return err; + } + + return 0; +} + +static inline int rockchip_sfc_pio_write(struct rockchip_sfc *sfc, u_char *buf, + size_t len) +{ + return rockchip_sfc_write_fifo(sfc, buf, len); +} + +static inline int rockchip_sfc_pio_read(struct rockchip_sfc *sfc, u_char *buf, + size_t len) +{ + return rockchip_sfc_read_fifo(sfc, buf, len); +} + +static int rockchip_sfc_pio_transfer(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, loff_t from_to, size_t len, + u_char *buf, u8 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + size_t trans; + int ret; + + trans = min_t(size_t, SFC_MAX_TRANS_BYTES, len); + ret = rockchip_sfc_setup_transfer(priv, op, from_to, trans, op_type); + if (ret < 0) + return ret; + + if (op_type == SFC_CMD_DIR_WR) + ret = rockchip_sfc_pio_write(sfc, buf, trans); + else + ret = rockchip_sfc_pio_read(sfc, buf, trans); + + return ret; +} + +static int rockchip_sfc_dma_transfer(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, loff_t from_to, size_t len, + u_char *buf, u8 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + size_t trans; + int ret; + + trans = min_t(size_t, SFC_MAX_TRANS_BYTES, len); + + if (op_type == SFC_CMD_DIR_WR) + memcpy(sfc->buffer, buf, trans); + + ret = rockchip_sfc_do_dma_transfer(priv, op, from_to, sfc->dma_buffer, + trans, op_type); + if (ret) { + dev_warn(sfc->dev, "DMA timeout\n"); + return ret; + } + + if (op_type == SFC_CMD_DIR_RD) + memcpy(buf, sfc->buffer, trans); + + return trans; +} + +static ssize_t rockchip_sfc_do_rd_wr(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op, loff_t from_to, size_t len, + u_char *buf, u32 op_type) +{ + struct rockchip_sfc *sfc = priv->sfc; + + /* DMA can only handle word aligned transfer chunks */ + if (likely(sfc->use_dma) && !(len & 0x3)) + return rockchip_sfc_dma_transfer(priv, op, from_to, len, buf, op_type); + else + return rockchip_sfc_pio_transfer(priv, op, from_to, len, buf, op_type); +} + +static ssize_t rockchip_sfc_read(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op) +{ + loff_t from = op->addr.val; + size_t len = op->data.nbytes; + u_char *read_buf = op->data.buf.in; + + return rockchip_sfc_do_rd_wr(priv, op, from, len, read_buf, SFC_CMD_DIR_RD); +} + +static ssize_t rockchip_sfc_write(struct rockchip_sfc_chip_priv *priv, + const struct spi_mem_op *op) +{ + loff_t to = op->addr.val; + size_t len = op->data.nbytes; + const u_char *write_buf = op->data.buf.out; + + return rockchip_sfc_do_rd_wr(priv, op, to, len, (u_char *)write_buf, SFC_CMD_DIR_WR); +} + +static int rockchip_sfc_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); + struct rockchip_sfc_chip_priv *priv = &sfc->flash[mem->spi->chip_select]; + + if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { + if (!op->addr.nbytes) + return rockchip_sfc_read_reg(priv, op); + + return rockchip_sfc_read(priv, op); + } + + if (!op->addr.nbytes || !op->data.buf.out) + return rockchip_sfc_write_reg(priv, op); + + return rockchip_sfc_write(priv, op); +} + +static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); + struct rockchip_sfc_chip_priv *priv = &sfc->flash[mem->spi->chip_select]; + int ret; + + ret = clk_set_rate(sfc->clk, priv->clk_rate); + if (ret) + return ret; + + ret = rockchip_sfc_mem_process(mem, op); + if (ret < 0) { + dev_err(&mem->spi->dev, "operation failed with %d\n", ret); + return ret; + } + + return 0; +} + +static const char *rockchip_sfc_get_name(struct spi_mem *mem) +{ + struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); + struct device *dev = sfc->dev; + + return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); +} + +static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { + .exec_op = rockchip_sfc_exec_mem_op, + .get_name = rockchip_sfc_get_name, +}; + +static int rockchip_sfc_register(struct device_node *np, + struct rockchip_sfc *sfc) +{ + struct device *dev = sfc->dev; + int ret; + + ret = of_property_read_u8(np, "reg", &sfc->flash[sfc->num_chip].cs); + if (ret) { + dev_err(dev, "No reg property for %s\n", + np->full_name); + return ret; + } + + ret = of_property_read_u32(np, "spi-max-frequency", + &sfc->flash[sfc->num_chip].clk_rate); + if (ret) { + dev_err(dev, "No spi-max-frequency property for %s\n", + np->full_name); + return ret; + } + + sfc->flash[sfc->num_chip].sfc = sfc; + sfc->num_chip++; + return 0; +} + +static int rockchip_sfc_register_all(struct rockchip_sfc *sfc) +{ + struct device *dev = sfc->dev; + struct device_node *np; + int ret; + + for_each_available_child_of_node(dev->of_node, np) { + ret = rockchip_sfc_register(np, sfc); + if (ret) + dev_err(dev, "Failed to register all chips\n"); + return ret; + + if (sfc->num_chip >= SFC_MAX_CHIPSELECT_NUM) { + dev_warn(dev, "Exceeds the max cs limitation\n"); + break; + } + } + + return 0; +} + +static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id) +{ + struct rockchip_sfc *sfc = dev_id; + u32 reg; + + reg = readl(sfc->regbase + SFC_RISR); + + /* Clear interrupt */ + writel_relaxed(reg, sfc->regbase + SFC_ICLR); + + if (reg & SFC_RISR_TRAN_FINISH) + complete(&sfc->cp); + + return IRQ_HANDLED; +} + +static int rockchip_sfc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spi_master *master; + struct resource *res; + struct rockchip_sfc *sfc; + int ret; + + master = spi_alloc_master(&pdev->dev, sizeof(*sfc)); + if (!master) { + dev_err(&pdev->dev, "spi_alloc_master failed\n"); + return -ENOMEM; + } + + master->mem_ops = &rockchip_sfc_mem_ops; + master->dev.of_node = pdev->dev.of_node; + master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; + master->min_speed_hz = SFC_MIN_SPEED_HZ; + master->max_speed_hz = SFC_MAX_SPEED_HZ; + + sfc = spi_master_get_devdata(master); + sfc->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sfc->regbase = devm_ioremap_resource(dev, res); + if (IS_ERR(sfc->regbase)) + return PTR_ERR(sfc->regbase); + + sfc->clk = devm_clk_get(&pdev->dev, "sfc"); + if (IS_ERR(sfc->clk)) { + dev_err(&pdev->dev, "Failed to get sfc interface clk\n"); + return PTR_ERR(sfc->clk); + } + + sfc->hclk = devm_clk_get(&pdev->dev, "ahb"); + if (IS_ERR(sfc->hclk)) { + dev_err(&pdev->dev, "Failed to get sfc ahb clk\n"); + return PTR_ERR(sfc->hclk); + } + + sfc->use_dma = !of_property_read_bool(sfc->dev->of_node, + "rockchip,sfc-no-dma"); + + if (sfc->use_dma) { + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) { + dev_warn(dev, "Unable to set dma mask\n"); + return ret; + } + + sfc->buffer = dmam_alloc_coherent(dev, SFC_MAX_TRANS_BYTES, + &sfc->dma_buffer, + GFP_KERNEL); + if (!sfc->buffer) + return -ENOMEM; + } + + ret = clk_prepare_enable(sfc->hclk); + if (ret) { + dev_err(&pdev->dev, "Failed to enable ahb clk\n"); + goto err_hclk; + } + + ret = clk_prepare_enable(sfc->clk); + if (ret) { + dev_err(&pdev->dev, "Failed to enable interface clk\n"); + goto err_clk; + } + + /* Find the irq */ + ret = platform_get_irq(pdev, 0); + if (ret < 0) { + dev_err(dev, "Failed to get the irq\n"); + goto err_irq; + } + + ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler, + 0, pdev->name, sfc); + if (ret) { + dev_err(dev, "Failed to request irq\n"); + goto err_irq; + } + + sfc->num_chip = 0; + ret = rockchip_sfc_init(sfc); + if (ret) + goto err_irq; + + ret = rockchip_sfc_register_all(sfc); + if (ret) + goto err_irq; + + ret = devm_spi_register_master(dev, master); + if (ret) + goto err_irq; + + return 0; + +err_irq: + clk_disable_unprepare(sfc->clk); +err_clk: + clk_disable_unprepare(sfc->hclk); +err_hclk: + return ret; +} + +static int rockchip_sfc_remove(struct platform_device *pdev) +{ + struct rockchip_sfc *sfc = platform_get_drvdata(pdev); + + clk_disable_unprepare(sfc->clk); + clk_disable_unprepare(sfc->hclk); + return 0; +} + +static const struct of_device_id rockchip_sfc_dt_ids[] = { + { .compatible = "rockchip,rk3036-sfc"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids); + +static struct platform_driver rockchip_sfc_driver = { + .driver = { + .name = "rockchip-sfc", + .of_match_table = rockchip_sfc_dt_ids, + }, + .probe = rockchip_sfc_probe, + .remove = rockchip_sfc_remove, +}; +module_platform_driver(rockchip_sfc_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver"); +MODULE_AUTHOR("Shawn Lin "); From patchwork Tue Jun 1 20:10:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 12292181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39AD4C47093 for ; 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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id p25sm468118ood.4.2021.06.01.13.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jun 2021 13:10:32 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [PATCH v3 3/4] arm64: dts: rockchip: Add SFC to PX30 Date: Tue, 1 Jun 2021 15:10:20 -0500 Message-Id: <20210601201021.4406-4-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601201021.4406-1-macroalpha82@gmail.com> References: <20210601201021.4406-1-macroalpha82@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the PX30 SOC. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 09baa8a167ce..1f4feb53e270 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -966,6 +966,18 @@ emmc: mmc@ff390000 { status = "disabled"; }; + sfc: spi@ff3a0000 { + compatible = "rockchip,px30-sfc","rockchip,rk3036-sfc"; + reg = <0x0 0xff3a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "sfc", "ahb"; + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>; + pinctrl-names = "default"; + power-domains = <&power PX30_PD_MMC_NAND>; + status = "disabled"; + }; + nfc: nand-controller@ff3b0000 { compatible = "rockchip,px30-nfc"; reg = <0x0 0xff3b0000 0x0 0x4000>; @@ -1967,6 +1979,32 @@ flash_bus8: flash-bus8 { }; }; + serial_flash { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <1 RK_PA0 3 &pcfg_pull_none>, + <1 RK_PA1 3 &pcfg_pull_none>, + <1 RK_PA2 3 &pcfg_pull_none>, + <1 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <1 RK_PA0 3 &pcfg_pull_none>, + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs: sfc-cs { + rockchip,pins = + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <1 RK_PB1 3 &pcfg_pull_none>; + }; + }; + lcdc { lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { rockchip,pins = From patchwork Tue Jun 1 20:10:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 12292185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB77BC47080 for ; Tue, 1 Jun 2021 20:10:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C66E660FD8 for ; Tue, 1 Jun 2021 20:10:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234671AbhFAUMS (ORCPT ); Tue, 1 Jun 2021 16:12:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234707AbhFAUMR (ORCPT ); Tue, 1 Jun 2021 16:12:17 -0400 Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BEDEC061574 for ; Tue, 1 Jun 2021 13:10:35 -0700 (PDT) Received: by mail-oi1-x234.google.com with SMTP id u11so591423oiv.1 for ; Tue, 01 Jun 2021 13:10:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S1IlgvnVJwHgpqMHaCMFQfQ+LU3PHCxwl3hNw4XjuSw=; b=EeNU8PFN5nikWcHPD/AwUBoiScDgl3EWWa8zrjb9U/cIEJaY/YIDjVHe2I+r9DlqRz keTAwHu+jIwm+1KlgwWXVTU6efE2liPqXwTj2+SqgtNecF85PawwDOJ+CD2PnjSEJpRM Hho76fCx8UppcH6i+Y2LYtrUGMIZjP6pbStqRwo/EEdDqyYlu03GH4zXLTNpxUu7LpW3 cMCwetoqLRXuJ3YcBIbMVwMtyek4TGjTprNx8g4DQP4ZLQuip7yEDnnBZ+B9rRavhwOu 5/OsJ2FecXsBtzrQOa94o9MZDjM+jP+O8QLEcDmgLkduywyVbnLhZPmKjpIWuypuioHy ZlHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S1IlgvnVJwHgpqMHaCMFQfQ+LU3PHCxwl3hNw4XjuSw=; b=jMWh/DJD3rMOLH+LuvsJyiNJFrnC1MUd5SNunhP7mqBuJ272FlGVQwPA94PEcoiinw 3EswX1YMeqbgrPazIIMus6XuGsUdL5th7PCEcKUEDRaNpYXqt8Izju0KHHQhHjHylhwD yDIKc4KpfcNMES7Ru5N3inuW1A7cz35l2ohcVHhOOQzZyuxGeBNr9b3UsXE6OsAOu3JT HGuqELTr2y5CZMaGvbZiiuZVRoVFXLOjHsn9Nsn+Fdy5MfM6oU3qpPK78z6sl7kejZE+ mIyCVI99uJSFWL/fQ5ZP+4pAdnQKST2UkjFYkObMm1CWSjW2+SGzZpu8epcfbfxj2b3Z f4BA== X-Gm-Message-State: AOAM533ftoW5O3x/iOAV4ix8a6nRQO8qkN9OEdef6mzTzNrc3oqdyfbx yTwZlp8E5KaLJFPuVZD+IDb9JoWVAqA= X-Google-Smtp-Source: ABdhPJz9bgTRA0/4PRS/IEFOuAyN5MObDSPJSbOquTl1lnc/ePqcF0ozUNWfTLHywvolDHjhWICuXg== X-Received: by 2002:aca:1c18:: with SMTP id c24mr7158644oic.139.1622578234094; Tue, 01 Jun 2021 13:10:34 -0700 (PDT) Received: from wintermute.localdomain (cpe-76-183-134-35.tx.res.rr.com. [76.183.134.35]) by smtp.gmail.com with ESMTPSA id p25sm468118ood.4.2021.06.01.13.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jun 2021 13:10:33 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [PATCH v4 4/4] arm64: dts: rockchip: Enable SFC for Odroid Go Advance Date: Tue, 1 Jun 2021 15:10:21 -0500 Message-Id: <20210601201021.4406-5-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601201021.4406-1-macroalpha82@gmail.com> References: <20210601201021.4406-1-macroalpha82@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Chris Morgan This enables the Rockchip Serial Flash Controller for the Odroid Go Advance. Note that while the attached SPI NOR flash and the controller both support quad read mode, only 2 of the required 4 pins are present. The rx and tx bus width is set to 2 for this reason. Signed-off-by: Chris Morgan --- .../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts index 49c97f76df77..46f1d2f356cc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -484,6 +484,22 @@ &sdmmc { status = "okay"; }; +&sfc { + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <108000000>; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &tsadc { status = "okay"; };