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Tue, 01 Jun 2021 17:15:03 -0700 (PDT) From: Nobuhiro Iwamatsu To: Michael Turquette , Stephen Boyd , Rob Herring , Michal Simek Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Nobuhiro Iwamatsu Subject: [PATCH v2] dt-bindings: clk: zynqmp: convert bindings to YAML Date: Wed, 2 Jun 2021 09:14:49 +0900 Message-Id: <20210602001449.780075-1-iwamatsu@nigauri.org> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210601_171506_885832_60A15FE6 X-CRM114-Status: GOOD ( 21.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert common clock for Xilinx Zynq MPSoC SoC bindings documentation to YAML. Signed-off-by: Nobuhiro Iwamatsu --- v2: Fix warning with DT_CHECKER_FLAGS=-m. .../bindings/clock/xlnx,zynqmp-clk.txt | 63 --------- .../bindings/clock/xlnx,zynqmp-clk.yaml | 63 +++++++++ .../mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 ------------------ 3 files changed, 63 insertions(+), 190 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml delete mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt deleted file mode 100644 index 391ee1a60bed4a..00000000000000 --- a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt +++ /dev/null @@ -1,63 +0,0 @@ --------------------------------------------------------------------------- -Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using -Zynq MPSoC firmware interface --------------------------------------------------------------------------- -The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock -tree. It reads required input clock frequencies from the devicetree and acts -as clock provider for all clock consumers of PS clocks. - -See clock_bindings.txt for more information on the generic clock bindings. - -Required properties: - - #clock-cells: Must be 1 - - compatible: Must contain: "xlnx,zynqmp-clk" - - clocks: List of clock specifiers which are external input - clocks to the given clock controller. Please refer - the next section to find the input clocks for a - given controller. - - clock-names: List of clock names which are exteral input clocks - to the given clock controller. Please refer to the - clock bindings for more details. - -Input clocks for zynqmp Ultrascale+ clock controller: - -The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock -inputs. These required clock inputs are: - - pss_ref_clk (PS reference clock) - - video_clk (reference clock for video system ) - - pss_alt_ref_clk (alternative PS reference clock) - - aux_ref_clk - - gt_crx_ref_clk (transceiver reference clock) - -The following strings are optional parameters to the 'clock-names' property in -order to provide an optional (E)MIO clock source: - - swdt0_ext_clk - - swdt1_ext_clk - - gem0_emio_clk - - gem1_emio_clk - - gem2_emio_clk - - gem3_emio_clk - - mio_clk_XX # with XX = 00..77 - - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51 - - -Output clocks are registered based on clock information received -from firmware. Output clocks indexes are mentioned in -include/dt-bindings/clock/xlnx-zynqmp-clk.h. - -------- -Example -------- - -firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - method = "smc"; - zynqmp_clk: clock-controller { - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clk"; - clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; - clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml new file mode 100644 index 00000000000000..e7a1384fb646e4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq Ultrascale+ MPSoC clock controller Device Tree Bindings + +maintainers: + - Michal Simek + +description: | + The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock + tree. It reads required input clock frequencies from the devicetree and acts + as clock provider for all clock consumers of PS clocks. + +properties: + compatible: + const: xlnx,zynqmp-clk + + "#clock-cells": + const: 1 + + clocks: + description: | + List of clock specifiers which are external input + clocks to the given clock controller. + items: + - description: PS reference clock + - description: reference clock for video system + - description: alternative PS reference clock + - description: auxiliary reference clock + - description: transceiver reference clock + + clock-names: + items: + - const: pss_ref_clk + - const: video_clk + - const: pss_alt_ref_clk + - const: aux_ref_clk + - const: gt_crx_ref_clk + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + firmware { + zynqmp_firmware: zynqmp-firmware { + zynqmp_clk: clock-controller { + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt deleted file mode 100644 index ad76edccf88166..00000000000000 --- a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt +++ /dev/null @@ -1,127 +0,0 @@ -Xilinx IPI Mailbox Controller -======================================== - -The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage -messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI -agent owns registers used for notification and buffers for message. - - +-------------------------------------+ - | Xilinx ZynqMP IPI Controller | - +-------------------------------------+ - +--------------------------------------------------+ -ATF | | - | | - | | - +--------------------------+ | - | | - | | - +--------------------------------------------------+ - +------------------------------------------+ - | +----------------+ +----------------+ | -Hardware | | IPI Agent | | IPI Buffers | | - | | Registers | | | | - | | | | | | - | +----------------+ +----------------+ | - | | - | Xilinx IPI Agent Block | - +------------------------------------------+ - - -Controller Device Node: -=========================== -Required properties: --------------------- -IPI agent node: -- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox" -- interrupt-parent: Phandle for the interrupt controller -- interrupts: Interrupt information corresponding to the - interrupt-names property. -- xlnx,ipi-id: local Xilinx IPI agent ID -- #address-cells: number of address cells of internal IPI mailbox nodes -- #size-cells: number of size cells of internal IPI mailbox nodes - -Internal IPI mailbox node: -- reg: IPI buffers address ranges -- reg-names: Names of the reg resources. It should have: - * local_request_region - - IPI request msg buffer written by local and read - by remote - * local_response_region - - IPI response msg buffer written by local and read - by remote - * remote_request_region - - IPI request msg buffer written by remote and read - by local - * remote_response_region - - IPI response msg buffer written by remote and read - by local -- #mbox-cells: Shall be 1. It contains: - * tx(0) or rx(1) channel -- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is - connected to. - -Optional properties: --------------------- -- method: The method of accessing the IPI agent registers. - Permitted values are: "smc" and "hvc". Default is - "smc". - -Client Device Node: -=========================== -Required properties: --------------------- -- mboxes: Standard property to specify a mailbox - (See ./mailbox.txt) -- mbox-names: List of identifier strings for each mailbox - channel. - -Example: -=========================== - zynqmp_ipi { - compatible = "xlnx,zynqmp-ipi-mailbox"; - interrupt-parent = <&gic>; - interrupts = <0 29 4>; - xlnx,ipi-id = <0>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* APU<->RPU0 IPI mailbox controller */ - ipi_mailbox_rpu0: mailbox@ff990400 { - reg = <0xff990400 0x20>, - <0xff990420 0x20>, - <0xff990080 0x20>, - <0xff9900a0 0x20>; - reg-names = "local_request_region", - "local_response_region", - "remote_request_region", - "remote_response_region"; - #mbox-cells = <1>; - xlnx,ipi-id = <1>; - }; - /* APU<->RPU1 IPI mailbox controller */ - ipi_mailbox_rpu1: mailbox@ff990440 { - reg = <0xff990440 0x20>, - <0xff990460 0x20>, - <0xff990280 0x20>, - <0xff9902a0 0x20>; - reg-names = "local_request_region", - "local_response_region", - "remote_request_region", - "remote_response_region"; - #mbox-cells = <1>; - xlnx,ipi-id = <2>; - }; - }; - rpu0 { - ... - mboxes = <&ipi_mailbox_rpu0 0>, - <&ipi_mailbox_rpu0 1>; - mbox-names = "tx", "rx"; - }; - rpu1 { - ... - mboxes = <&ipi_mailbox_rpu1 0>, - <&ipi_mailbox_rpu1 1>; - mbox-names = "tx", "rx"; - };