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Wed, 2 Jun 2021 11:11:08 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 04:11:07 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 11:11:07 +0000 Received: from r-arch-stor03.mtr.labs.mlnx (172.20.187.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 11:11:04 +0000 From: Max Gurtovoy To: , , , , CC: , , , , , Max Gurtovoy Subject: [PATCH 1/3] mm,memory_hotplug: export mhp min alignment Date: Wed, 2 Jun 2021 14:10:53 +0300 Message-ID: <20210602111055.10480-2-mgurtovoy@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210602111055.10480-1-mgurtovoy@nvidia.com> References: <20210602111055.10480-1-mgurtovoy@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1961e6ff-87e5-4867-4430-08d925b71f80 X-MS-TrafficTypeDiagnostic: DM6PR12MB3244: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:247; 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E.g, it disallows all operations smaller than a sub-section and only allow operations smaller than a section for SPARSEMEM_VMEMMAP. Export the alignment restrictions for mhp users. Signed-off-by: Max Gurtovoy --- include/linux/memory_hotplug.h | 5 +++++ mm/memory_hotplug.c | 33 +++++++++++++++++++-------------- 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/include/linux/memory_hotplug.h b/include/linux/memory_hotplug.h index 28f32fd00fe9..c55a9049b11e 100644 --- a/include/linux/memory_hotplug.h +++ b/include/linux/memory_hotplug.h @@ -76,6 +76,7 @@ struct mhp_params { bool mhp_range_allowed(u64 start, u64 size, bool need_mapping); struct range mhp_get_pluggable_range(bool need_mapping); +unsigned long mhp_get_min_align(void); /* * Zone resizing functions @@ -248,6 +249,10 @@ void mem_hotplug_done(void); ___page; \ }) +static inline unsigned long mhp_get_min_align(void) +{ + return 0; +} static inline unsigned zone_span_seqbegin(struct zone *zone) { return 0; diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c index 9e86e9ee0a10..161bb6704a9b 100644 --- a/mm/memory_hotplug.c +++ b/mm/memory_hotplug.c @@ -270,24 +270,29 @@ void __init register_page_bootmem_info_node(struct pglist_data *pgdat) } #endif /* CONFIG_HAVE_BOOTMEM_INFO_NODE */ +/* + * Disallow all operations smaller than a sub-section and only + * allow operations smaller than a section for + * SPARSEMEM_VMEMMAP. Note that check_hotplug_memory_range() + * enforces a larger memory_block_size_bytes() granularity for + * memory that will be marked online, so this check should only + * fire for direct arch_{add,remove}_memory() users outside of + * add_memory_resource(). + */ +unsigned long mhp_get_min_align(void) +{ + if (IS_ENABLED(CONFIG_SPARSEMEM_VMEMMAP)) + return PAGES_PER_SUBSECTION; + return PAGES_PER_SECTION; +} +EXPORT_SYMBOL_GPL(mhp_get_min_align); + + static int check_pfn_span(unsigned long pfn, unsigned long nr_pages, const char *reason) { - /* - * Disallow all operations smaller than a sub-section and only - * allow operations smaller than a section for - * SPARSEMEM_VMEMMAP. Note that check_hotplug_memory_range() - * enforces a larger memory_block_size_bytes() granularity for - * memory that will be marked online, so this check should only - * fire for direct arch_{add,remove}_memory() users outside of - * add_memory_resource(). - */ - unsigned long min_align; + unsigned long min_align = mhp_get_min_align(); - if (IS_ENABLED(CONFIG_SPARSEMEM_VMEMMAP)) - min_align = PAGES_PER_SUBSECTION; - else - min_align = PAGES_PER_SECTION; if (!IS_ALIGNED(pfn, min_align) || !IS_ALIGNED(nr_pages, min_align)) { WARN(1, "Misaligned __%s_pages min_align: %#lx start: %#lx end: %#lx\n", reason, min_align, pfn, pfn + nr_pages - 1); From patchwork Wed Jun 2 11:10:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Gurtovoy X-Patchwork-Id: 12293853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9846EC47083 for ; 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Wed, 2 Jun 2021 11:11:15 +0000 Received: from r-arch-stor03.mtr.labs.mlnx (172.20.187.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 11:11:08 +0000 From: Max Gurtovoy To: , , , , CC: , , , , , Max Gurtovoy Subject: [PATCH 2/3] PCI/P2PMEM: introduce pci_p2pdma_align_size API Date: Wed, 2 Jun 2021 14:10:54 +0300 Message-ID: <20210602111055.10480-3-mgurtovoy@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210602111055.10480-1-mgurtovoy@nvidia.com> References: <20210602111055.10480-1-mgurtovoy@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a7c7314b-72fd-4ecf-405b-08d925b723bb X-MS-TrafficTypeDiagnostic: DM5PR12MB2566: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2803; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4FZwKIdPcbLoWeu1MRi3mChqBsqR8lxVebJUx3OC29ThwQf2JPbI9qO3L00xCdCJ/RcePmFhOVrpmI/+o57kU8q3ojk/q/qwwdU4RpjevCaaV+5TzebTb69x/PcNTzLcwyUNXz0LDCCk36p/aKQnKmycZ63kAExKIpmTs2ubC05JY7EIRKvaYCXDZYl+WRDBtsm0L2lF7Q859C8HDTIRtUew7gbVgsWxYULP3C5PKNqm8amG9W4bkqiuAElG5HjJJSoAIBKzknsOw6VDtSurLXyWaLrGCro4vD4xg6HbUQJ8p9ofY757zwP4u9EnId5MVOHNFyj9+Y82/JBsyBw2mABtqkY1rmGBAFa4DlhGeaeDSq9K0bv9DjXCUbxEeQOYjvEEvg6pAwslwzZhyYmIQyuIJ6z6YGXesfT7wtWPeGX3Y5lWBNPJn/KhhBNyMDGmSMPQcyVk63I7taXJcGLHrVcNt3eOQsjrphaIXuFA8al7HYMAUuwtn13rBZwBc7Bb5uxOGGANtIHPTViGD09byNRWVmQCYP6pEgma4SsaylwMxBBiP4fqeUWxk/jhvebjDw7DbHMBnVw41kEBmysmCVBloPn5TxNlUEllQ3il/1sKYP1LmPWDDFqkeMAB1to+Cs88zX1gAiWUxPETDJa5R/NAPElUNgKPHmQcQSoFO5IzrQCwB5DJger5J6AKQd6+ X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(396003)(346002)(136003)(376002)(39860400002)(36840700001)(46966006)(36756003)(6666004)(2616005)(54906003)(110136005)(478600001)(82310400003)(4326008)(186003)(8936002)(426003)(7636003)(2906002)(83380400001)(336012)(356005)(82740400003)(36860700001)(5660300002)(1076003)(26005)(107886003)(47076005)(316002)(36906005)(86362001)(70206006)(8676002)(70586007)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 11:11:15.7373 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7c7314b-72fd-4ecf-405b-08d925b723bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2566 X-Rspamd-Queue-Id: 82D6E50904B2 Authentication-Results: imf01.hostedemail.com; dkim=pass header.d=Nvidia.com header.s=selector2 header.b=SELfwH8i; dmarc=pass (policy=none) header.from=nvidia.com; spf=none (imf01.hostedemail.com: domain of mgurtovoy@nvidia.com has no SPF policy when checking 40.107.92.81) smtp.mailfrom=mgurtovoy@nvidia.com X-Rspamd-Server: rspam03 X-Stat-Signature: t93o37tausfdkn4hknm95org8r1pyodu X-HE-Tag: 1622632264-425640 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: The mhp layer has alignment restrictions that may cause a failure in adding a large P2PMEM that has non-aligned number of pages. The new API pci_p2pdma_align_size will align the P2PMEM size to be inline with the mhp restrictions. Signed-off-by: Max Gurtovoy --- drivers/pci/p2pdma.c | 23 +++++++++++++++++++++++ include/linux/pci-p2pdma.h | 5 +++++ 2 files changed, 28 insertions(+) diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c index 196382630363..d232bc4ada2b 100644 --- a/drivers/pci/p2pdma.c +++ b/drivers/pci/p2pdma.c @@ -220,6 +220,29 @@ int pci_p2pdma_add_resource(struct pci_dev *pdev, int bar, size_t size, } EXPORT_SYMBOL_GPL(pci_p2pdma_add_resource); +/** + * pci_p2pdma_align_size - align p2p memory size + * @size: size of the initial memory to align before adding. + * + * The size will be aligned according to mph alignment rules. This function + * should be called before adding new p2pdma resource since non-aligned memory + * will not be added. + */ +size_t pci_p2pdma_align_size(size_t size) +{ + unsigned int min_align, nr_pages; + + min_align = mhp_get_min_align(); + nr_pages = size >> PAGE_SHIFT; + if (!IS_ALIGNED(nr_pages, min_align)) { + nr_pages = ALIGN_DOWN(nr_pages, min_align); + size = nr_pages << PAGE_SHIFT; + } + + return size; +} +EXPORT_SYMBOL_GPL(pci_p2pdma_align_size); + /* * Note this function returns the parent PCI device with a * reference taken. It is the caller's responsibility to drop diff --git a/include/linux/pci-p2pdma.h b/include/linux/pci-p2pdma.h index 8318a97c9c61..33a8fce52bec 100644 --- a/include/linux/pci-p2pdma.h +++ b/include/linux/pci-p2pdma.h @@ -38,6 +38,7 @@ int pci_p2pdma_enable_store(const char *page, struct pci_dev **p2p_dev, bool *use_p2pdma); ssize_t pci_p2pdma_enable_show(char *page, struct pci_dev *p2p_dev, bool use_p2pdma); +size_t pci_p2pdma_align_size(size_t size); #else /* CONFIG_PCI_P2PDMA */ static inline int pci_p2pdma_add_resource(struct pci_dev *pdev, int bar, size_t size, u64 offset) @@ -105,6 +106,10 @@ static inline ssize_t pci_p2pdma_enable_show(char *page, { return sprintf(page, "none\n"); } +static inline size_t pci_p2pdma_align_size(size_t size) +{ + return 0; +} #endif /* CONFIG_PCI_P2PDMA */ From patchwork Wed Jun 2 11:10:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Gurtovoy X-Patchwork-Id: 12293855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC077C4708F for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 11:11:23.9151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e31bf6c-e93b-49a2-d480-08d925b728a6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.36];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3937 X-Rspamd-Queue-Id: 6EC6036D Authentication-Results: imf29.hostedemail.com; dkim=pass header.d=Nvidia.com header.s=selector2 header.b="eUbN/G1i"; dmarc=pass (policy=none) header.from=nvidia.com; spf=none (imf29.hostedemail.com: domain of mgurtovoy@nvidia.com has no SPF policy when checking 40.107.94.50) smtp.mailfrom=mgurtovoy@nvidia.com X-Rspamd-Server: rspam03 X-Stat-Signature: nxkd5i3pp55brh5ye147if6zidbsrd46 X-HE-Tag: 1622632270-347174 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: P2PMEM is using mhp framework to connect to the memory subsystem. In case the CMB size is not compatible to mhp alignment, the CMB mapping will fail. Use pci_p2pdma_align_size to align CMB size in order to successfully map non-aligned original CMB. Signed-off-by: Max Gurtovoy --- drivers/nvme/host/pci.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index a29b170701fc..1197263b4cd0 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -1817,6 +1817,7 @@ static void nvme_map_cmb(struct nvme_dev *dev) u64 size, offset; resource_size_t bar_size; struct pci_dev *pdev = to_pci_dev(dev->dev); + unsigned long nr_pages, min_align; int bar; if (dev->cmb_size) @@ -1856,6 +1857,12 @@ static void nvme_map_cmb(struct nvme_dev *dev) if (size > bar_size - offset) size = bar_size - offset; + size = pci_p2pdma_align_size(size); + if (!size) { + dev_warn(dev->ctrl.device, "CMB size is 0 after alignment\n"); + return; + } + if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { dev_warn(dev->ctrl.device, "failed to register the CMB\n");