From patchwork Thu Jun 3 22:44:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Brost X-Patchwork-Id: 12298321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EE3FC47082 for ; Thu, 3 Jun 2021 22:27:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E383D613F1 for ; Thu, 3 Jun 2021 22:27:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E383D613F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BE0586F53C; Thu, 3 Jun 2021 22:27:23 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F5C16F52A; Thu, 3 Jun 2021 22:27:20 +0000 (UTC) IronPort-SDR: iNiQHNub60nqfhJUJflxHfuD48tvnAQMiodpZqjAoN2q+r93/Lq2YNWTjmS+SwRbJkCQIuKQsU nFEVj+G8Z30g== X-IronPort-AV: E=McAfee;i="6200,9189,10004"; a="183852266" X-IronPort-AV: E=Sophos;i="5.83,246,1616482800"; d="scan'208";a="183852266" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2021 15:26:53 -0700 IronPort-SDR: ZMdtxofGpRb7HaFk3l6H823wz1JcPYszwXDAalTgOmMsnhYdEn2fO3g1mZ31wFXqWDPsSYw9WV hanVGR8PQ2IQ== X-IronPort-AV: E=Sophos;i="5.83,246,1616482800"; d="scan'208";a="475236900" Received: from dhiatt-server.jf.intel.com ([10.54.81.3]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2021 15:26:53 -0700 From: Matthew Brost To: Subject: [PATCH 1/2] drm/i915/guc: Replace CTB array with explicit members Date: Thu, 3 Jun 2021 15:44:43 -0700 Message-Id: <20210603224444.37086-1-matthew.brost@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Michal Wajdeczko Upcoming GuC firmware will always require just two CTBs and we also plan to configure them with different sizes, so definining them as array is no longer suitable. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Reviewed-by: Matthew Brost Reported-by: kernel test robot --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46 ++++++++++++----------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 7 +++- 2 files changed, 30 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index 34c582105860..882ae1ed41b0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -168,10 +168,10 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) struct intel_guc *guc = ct_to_guc(ct); struct guc_ct_buffer_desc *desc; u32 blob_size; + u32 cmds_size; void *blob; u32 *cmds; int err; - int i; GEM_BUG_ON(ct->vma); @@ -207,15 +207,23 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); - /* store pointers to desc and cmds */ - for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) { - GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV)); + /* store pointers to desc and cmds for send ctb */ + desc = blob; + cmds = blob + PAGE_SIZE / 2; + cmds_size = PAGE_SIZE / 4; + CT_DEBUG(ct, "%s desc %#p cmds %#p size %u\n", "send", + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size); - desc = blob + PAGE_SIZE / 4 * i; - cmds = blob + PAGE_SIZE / 4 * i + PAGE_SIZE / 2; + guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size); - guc_ct_buffer_init(&ct->ctbs[i], desc, cmds, PAGE_SIZE / 4); - } + /* store pointers to desc and cmds for recv ctb */ + desc = blob + PAGE_SIZE / 4; + cmds = blob + PAGE_SIZE / 4 + PAGE_SIZE / 2; + cmds_size = PAGE_SIZE / 4; + CT_DEBUG(ct, "%s desc %#p cmds %#p size %u\n", "recv", + ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size); + + guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size); return 0; } @@ -246,7 +254,6 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) u32 base, cmds; void *blob; int err; - int i; GEM_BUG_ON(ct->enabled); @@ -257,28 +264,25 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) /* blob should start with send descriptor */ blob = __px_vaddr(ct->vma->obj); - GEM_BUG_ON(blob != ct->ctbs[CTB_SEND].desc); + GEM_BUG_ON(blob != ct->ctbs.send.desc); /* (re)initialize descriptors */ - for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) { - GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV)); + cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); + guc_ct_buffer_reset(&ct->ctbs.send, cmds); - cmds = base + ptrdiff(ct->ctbs[i].cmds, blob); - CT_DEBUG(ct, "%d: cmds addr=%#x\n", i, cmds); - - guc_ct_buffer_reset(&ct->ctbs[i], cmds); - } + cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); + guc_ct_buffer_reset(&ct->ctbs.recv, cmds); /* * Register both CT buffers starting with RECV buffer. * Descriptors are in first half of the blob. */ - err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_RECV].desc, blob), + err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.recv.desc, blob), INTEL_GUC_CT_BUFFER_TYPE_RECV); if (unlikely(err)) goto err_out; - err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_SEND].desc, blob), + err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.send.desc, blob), INTEL_GUC_CT_BUFFER_TYPE_SEND); if (unlikely(err)) goto err_deregister; @@ -341,7 +345,7 @@ static int ct_write(struct intel_guc_ct *ct, u32 len /* in dwords */, u32 fence) { - struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_SEND]; + struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; struct guc_ct_buffer_desc *desc = ctb->desc; u32 head = desc->head; u32 tail = desc->tail; @@ -557,7 +561,7 @@ static inline bool ct_header_is_response(u32 header) static int ct_read(struct intel_guc_ct *ct, u32 *data) { - struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_RECV]; + struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; struct guc_ct_buffer_desc *desc = ctb->desc; u32 head = desc->head; u32 tail = desc->tail; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index 4009e2dd0de4..fc9486779e87 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -47,8 +47,11 @@ struct intel_guc_ct { struct i915_vma *vma; bool enabled; - /* buffers for sending(0) and receiving(1) commands */ - struct intel_guc_ct_buffer ctbs[2]; + /* buffers for sending and receiving commands */ + struct { + struct intel_guc_ct_buffer send; + struct intel_guc_ct_buffer recv; + } ctbs; struct { u32 last_fence; /* last fence used to send request */ From patchwork Thu Jun 3 22:44:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Brost X-Patchwork-Id: 12298319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52486C47082 for ; Thu, 3 Jun 2021 22:27:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1906061405 for ; Thu, 3 Jun 2021 22:27:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1906061405 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8DA576F52A; Thu, 3 Jun 2021 22:27:22 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A3386F537; Thu, 3 Jun 2021 22:27:21 +0000 (UTC) IronPort-SDR: Xl4fzlCF1mc0x5alVNch7R402JW09IpE11/UhMrB8vSo2RiAlF8qhTO69YzWD1zBw9e0yhTbo/ ZHQw1vbWI90A== X-IronPort-AV: E=McAfee;i="6200,9189,10004"; a="183852267" X-IronPort-AV: E=Sophos;i="5.83,246,1616482800"; d="scan'208";a="183852267" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2021 15:26:53 -0700 IronPort-SDR: oybbXG9M6TuB/hDM96LWHzn3ItRYC7xoLS4z62B6mCuRNwA1t22+8wxIC318qpTX0AZLQO26JO qO8LImIjexLw== X-IronPort-AV: E=Sophos;i="5.83,246,1616482800"; d="scan'208";a="475236903" Received: from dhiatt-server.jf.intel.com ([10.54.81.3]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2021 15:26:53 -0700 From: Matthew Brost To: Subject: [PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers Date: Thu, 3 Jun 2021 15:44:44 -0700 Message-Id: <20210603224444.37086-2-matthew.brost@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210603224444.37086-1-matthew.brost@intel.com> References: <20210603224444.37086-1-matthew.brost@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Michal Wajdeczko Future GuC will require CTB buffers sizes to be multiple of 4K. Make these changes now as this shouldn't impact us too much. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Reviewed-by: Matthew Brost Cc: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 60 ++++++++++++----------- 1 file changed, 32 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index 882ae1ed41b0..8d70f637640b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -38,6 +38,32 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CT_PROBE_ERROR(_ct, _fmt, ...) \ i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) +/** + * DOC: CTB Blob + * + * We allocate single blob to hold both CTB descriptors and buffers: + * + * +--------+-----------------------------------------------+------+ + * | offset | contents | size | + * +========+===============================================+======+ + * | 0x0000 | H2G `CTB Descriptor`_ (send) | | + * +--------+-----------------------------------------------+ 4K | + * | 0x0800 | G2H `CTB Descriptor`_ (recv) | | + * +--------+-----------------------------------------------+------+ + * | 0x1000 | H2G `CT Buffer`_ (send) | n*4K | + * | | | | + * +--------+-----------------------------------------------+------+ + * | 0x1000 | G2H `CT Buffer`_ (recv) | m*4K | + * | + n*4K | | | + * +--------+-----------------------------------------------+------+ + * + * Size of each `CT Buffer`_ must be multiple of 4K. + * As we don't expect too many messages, for now use minimum sizes. + */ +#define CTB_DESC_SIZE ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K) +#define CTB_H2G_BUFFER_SIZE (SZ_4K) +#define CTB_G2H_BUFFER_SIZE (SZ_4K) + struct ct_request { struct list_head link; u32 fence; @@ -175,29 +201,7 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) GEM_BUG_ON(ct->vma); - /* We allocate 1 page to hold both descriptors and both buffers. - * ___________..................... - * |desc (SEND)| : - * |___________| PAGE/4 - * :___________....................: - * |desc (RECV)| : - * |___________| PAGE/4 - * :_______________________________: - * |cmds (SEND) | - * | PAGE/4 - * |_______________________________| - * |cmds (RECV) | - * | PAGE/4 - * |_______________________________| - * - * Each message can use a maximum of 32 dwords and we don't expect to - * have more than 1 in flight at any time, so we have enough space. - * Some logic further ahead will rely on the fact that there is only 1 - * page and that it is always mapped, so if the size is changed the - * other code will need updating as well. - */ - - blob_size = PAGE_SIZE; + blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE + CTB_G2H_BUFFER_SIZE; err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma, &blob); if (unlikely(err)) { CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n", @@ -209,17 +213,17 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) /* store pointers to desc and cmds for send ctb */ desc = blob; - cmds = blob + PAGE_SIZE / 2; - cmds_size = PAGE_SIZE / 4; + cmds = blob + 2 * CTB_DESC_SIZE; + cmds_size = CTB_H2G_BUFFER_SIZE; CT_DEBUG(ct, "%s desc %#p cmds %#p size %u\n", "send", ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size); guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size); /* store pointers to desc and cmds for recv ctb */ - desc = blob + PAGE_SIZE / 4; - cmds = blob + PAGE_SIZE / 4 + PAGE_SIZE / 2; - cmds_size = PAGE_SIZE / 4; + desc = blob + CTB_DESC_SIZE; + cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; + cmds_size = CTB_G2H_BUFFER_SIZE; CT_DEBUG(ct, "%s desc %#p cmds %#p size %u\n", "recv", ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);