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Fri, 4 Jun 2021 09:10:54 +0000 From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, dongas86@gmail.com, shawnguo@kernel.org, kernel@pengutronix.de, abel.vesa@nxp.com, Dong Aisheng Subject: [PATCH 01/10] clk: imx: scu: add more scu clocks Date: Fri, 4 Jun 2021 17:09:34 +0800 Message-Id: <20210604090943.3519350-2-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604090943.3519350-1-aisheng.dong@nxp.com> References: <20210604090943.3519350-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) To DB9PR04MB8477.eurprd04.prod.outlook.com (2603:10a6:10:2c3::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.24 via Frontend Transport; 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Signed-off-by: Dong Aisheng Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-imx8qxp.c | 152 +++++++++++++++++++++++++++++++++- 1 file changed, 150 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index f3cdd6449212..b1dd6ed685f9 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -25,6 +25,14 @@ static const char *dc0_sels[] = { "dc0_bypass0_clk", }; +static const char * const dc1_sels[] = { + "clk_dummy", + "clk_dummy", + "dc1_pll0_clk", + "dc1_pll1_clk", + "dc1_bypass0_clk", +}; + static const char *enet0_rgmii_txc_sels[] = { "enet0_ref_div", "dummy", @@ -35,6 +43,54 @@ static const char *enet1_rgmii_txc_sels[] = { "dummy", }; +static const char * const hdmi_sels[] = { + "clk_dummy", + "hdmi_dig_pll_clk", + "clk_dummy", + "clk_dummy", + "hdmi_av_pll_clk", +}; + +static const char * const hdmi_rx_sels[] = { + "clk_dummy", + "hdmi_rx_dig_pll_clk", + "clk_dummy", + "clk_dummy", + "hdmi_rx_bypass_clk", +}; + +static const char * const lcd_pxl_sels[] = { + "clk_dummy", + "clk_dummy", + "clk_dummy", + "clk_dummy", + "lcd_pxl_bypass_div_clk", +}; + +static const char * const mipi_sels[] = { + "clk_dummy", + "clk_dummy", + "mipi_pll_div2_clk", + "clk_dummy", + "clk_dummy", +}; + +static const char * const lcd_sels[] = { + "clk_dummy", + "clk_dummy", + "clk_dummy", + "clk_dummy", + "elcdif_pll", +}; + +static const char * const pi_pll0_sels[] = { + "clk_dummy", + "pi_dpll_clk", + "clk_dummy", + "clk_dummy", + "clk_dummy", +}; + static int imx8qxp_clk_probe(struct platform_device *pdev) { struct device_node *ccm_node = pdev->dev.of_node; @@ -48,6 +104,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) /* ARM core */ imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU); + imx_clk_scu("a53_clk", IMX_SC_R_A53, IMX_SC_PM_CLK_CPU); + imx_clk_scu("a72_clk", IMX_SC_R_A72, IMX_SC_PM_CLK_CPU); /* LSIO SS */ imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER); @@ -66,25 +124,42 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER); imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER); - /* ADMA SS */ + /* DMA SS */ imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER); imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER); imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER); imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("uart4_clk", IMX_SC_R_UART_4, IMX_SC_PM_CLK_PER); + imx_clk_scu("sim0_clk", IMX_SC_R_EMVSIM_0, IMX_SC_PM_CLK_PER); imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER); imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER); imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER); imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER); imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("can1_clk", IMX_SC_R_CAN_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("can2_clk", IMX_SC_R_CAN_2, IMX_SC_PM_CLK_PER); imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER); imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER); imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER); imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER); + imx_clk_scu("i2c4_clk", IMX_SC_R_I2C_4, IMX_SC_PM_CLK_PER); imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER); imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER); imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("adc1_clk", IMX_SC_R_ADC_1, IMX_SC_PM_CLK_PER); imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER); - imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER); + imx_clk_scu2("lcd_clk", lcd_sels, ARRAY_SIZE(lcd_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER); + imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("lcd_pxl_bypass_div_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("elcdif_pll", IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL); + + /* Audio SS */ + imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("audio_pll1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu("audio_pll_div_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("audio_pll_div_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("audio_rec_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("audio_rec_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC1); /* Connectivity */ imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER); @@ -94,11 +169,13 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV); imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK); imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_gate_gpr_scu("enet0_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true); imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0); imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER); imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV); imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK); imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_gate_gpr_scu("enet1_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true); imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0); imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER); @@ -114,30 +191,101 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS); imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("dc1_pll0_clk", IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc1_pll1_clk", IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu("dc1_bypass0_clk", IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("dc1_bypass1_clk", IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS); + /* MIPI-LVDS SS */ + imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER); imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); + imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS); + imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY); imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER); + + imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER); imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); + + imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS); + imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS); + imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY); imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds0_i2c0_clk", IMX_SC_R_LVDS_0_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds0_i2c1_clk", IMX_SC_R_LVDS_0_I2C_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds0_pwm0_clk", IMX_SC_R_LVDS_0_PWM_0, IMX_SC_PM_CLK_PER); + + imx_clk_scu("lvds1_i2c0_clk", IMX_SC_R_LVDS_1_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds1_i2c1_clk", IMX_SC_R_LVDS_1_I2C_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("lvds1_pwm0_clk", IMX_SC_R_LVDS_1_PWM_0, IMX_SC_PM_CLK_PER); + /* MIPI CSI SS */ imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER); imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC); imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER); imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi1_core_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi1_esc_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_MISC); + imx_clk_scu("mipi_csi1_i2c0_clk", IMX_SC_R_CSI_1_I2C_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("mipi_csi1_pwm0_clk", IMX_SC_R_CSI_1_PWM_0, IMX_SC_PM_CLK_PER); + + /* Parallel Interface SS */ + imx_clk_scu("pi_dpll_clk", IMX_SC_R_PI_0_PLL, IMX_SC_PM_CLK_PLL); + imx_clk_scu2("pi_per_div_clk", pi_pll0_sels, ARRAY_SIZE(pi_pll0_sels), IMX_SC_R_PI_0, IMX_SC_PM_CLK_PER); + imx_clk_scu("pi_mclk_div_clk", IMX_SC_R_PI_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("pi_i2c0_div_clk", IMX_SC_R_PI_0_I2C_0, IMX_SC_PM_CLK_PER); /* GPU SS */ imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER); imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC); + imx_clk_scu("gpu_core1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_PER); + imx_clk_scu("gpu_shader1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_MISC); + + /* CM40 SS */ + imx_clk_scu("cm40_i2c_div", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER); + imx_clk_scu("cm40_lpuart_div", IMX_SC_R_M4_0_UART, IMX_SC_PM_CLK_PER); + + /* CM41 SS */ + imx_clk_scu("cm41_i2c_div", IMX_SC_R_M4_1_I2C, IMX_SC_PM_CLK_PER); + + /* HDMI TX SS */ + imx_clk_scu("hdmi_dig_pll_clk", IMX_SC_R_HDMI_PLL_0, IMX_SC_PM_CLK_PLL); + imx_clk_scu("hdmi_av_pll_clk", IMX_SC_R_HDMI_PLL_1, IMX_SC_PM_CLK_PLL); + imx_clk_scu2("hdmi_pixel_mux_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("hdmi_pixel_link_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("hdmi_ipg_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC4); + imx_clk_scu("hdmi_i2c0_clk", IMX_SC_R_HDMI_I2C_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("hdmi_hdp_core_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("hdmi_pxl_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC3); + imx_clk_scu("hdmi_i2s_bypass_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_BYPASS); + imx_clk_scu("hdmi_i2s_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_MISC0); + + /* HDMI RX SS */ + imx_clk_scu("hdmi_rx_i2s_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("hdmi_rx_spdif_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC1); + imx_clk_scu("hdmi_rx_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("hdmi_rx_i2c0_clk", IMX_SC_R_HDMI_RX_I2C_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("hdmi_rx_pwm_clk", IMX_SC_R_HDMI_RX_PWM_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu("hdmi_rx_spdif_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC0); + imx_clk_scu2("hdmi_rx_hd_ref_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC1); + imx_clk_scu2("hdmi_rx_hd_core_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("hdmi_rx_pxl_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC3); + imx_clk_scu("hdmi_rx_i2s_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC4); + ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks); if (ret) imx_clk_scu_unregister(); From patchwork Fri Jun 4 09:09:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 12299177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A356C07E94 for ; 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dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from DB9PR04MB8477.eurprd04.prod.outlook.com (2603:10a6:10:2c3::11) by DU2PR04MB8917.eurprd04.prod.outlook.com (2603:10a6:10:2e0::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.21; Fri, 4 Jun 2021 09:10:58 +0000 Received: from DB9PR04MB8477.eurprd04.prod.outlook.com ([fe80::508:d95f:f63b:714a]) by DB9PR04MB8477.eurprd04.prod.outlook.com ([fe80::508:d95f:f63b:714a%7]) with mapi id 15.20.4195.024; Fri, 4 Jun 2021 09:10:58 +0000 From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, dongas86@gmail.com, shawnguo@kernel.org, kernel@pengutronix.de, abel.vesa@nxp.com, "Guoniu.zhou" , Dong Aisheng Subject: [PATCH 02/10] clk: imx: scu: add parallel port clock ops Date: Fri, 4 Jun 2021 17:09:35 +0800 Message-Id: <20210604090943.3519350-3-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604090943.3519350-1-aisheng.dong@nxp.com> References: <20210604090943.3519350-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) To DB9PR04MB8477.eurprd04.prod.outlook.com (2603:10a6:10:2c3::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.24 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 80DV7Ki66zWM84bvAwAj6nIGK7S0eRI55xJMJzJuXtsBn10dyzyRa+kmPjrrJYgdikIoM5Y0At2OI8MKngSbpc85HSguC40w+t8xttDK6NLxkpuV++8hOX0IAwvk3F1tf479kx/UaQV6ziQYsxFf2gVXJD053cK3IkAYqDqSL6nz/Y0nbqL0MgiQFiFyt7/pdNflEsxAi/NSasRrFv7dmFQiYU2bEFZSx/k56iK8DOMQfFvBwimju/D+kKZKTosDxyOi7VBJC4PozYmtwFI/XiSby/4OMZkhRA7HeseDdTEwW/w3Qje5s1KWSpKEbxUut0gOWgahE/D1Fe0GkQ/cjgD2Nz2Eow4dxsMxmxw8hyrKojLbI+KvXpG2SZ8vce1EDeVkQxdBZcCd679nlHp5a6x1XElVz0TeQUs68rULnic3wm49VSXqy1qrNptbur4bCQFMYFqijkt0UvDmHpX7GqngD5Boaeb8JTAToctsq0acjcINZUUoJY1epkhbnf1S0XRWB9mW+GTDLZ15LoAywJTbkK6Z2LtCKorab7QOaV5oyOjk5RX0Wyti4r3NTafj2Afx3TExmOda5kKT4DlSlhfTM3jpA4Vn1LzB+S16JYD6LOt2slpcrLMSwJLC7bPOVcDdDmdKO2gPQlesSTF3L8UWJSN8PFmomfC7JSwra+Bq7DdMA22z6MiVOyLmyj+6nmGBWw98vVoFEjG4CXlb0jh5NIru/Ntq2k+I6UEWoT+TV9LEyeM6mVaGHn8KZlJEA2f7XFUz0SUtrrabNKgNlolwimn/F/+FKXAdKFcUX1wzhOV+3vDi29eHThAoTRzwptwILxFfo4PnYXrl2XFyfMZ7K9NykMEK1Zyk8VfKt4vQd0v8MX5CP9OGL1SvkvLV9D2+EakVH4RycO0dxOQEh+vcPFde/9oHv0v1AL49Nyha/LhjTilGbpknOfRsmMfX2eo61a1+X9lji+IiPOETlU3c4FwjclygGmYMMrUtzRx36Fi+JUT6Hp2YBOJr792X+xN66tyLbKdlvRDcMP4u52jdFLi6Ucv7OEU5Fl51JVpWvoRe1PRxPErIjXnBUw9fQoNYxcJYqtRKK/ouKKuezMiuh4bvEoORxLBnmVSUP/0bnMYSSXqbGDpn/ycj+UVjbY67yEG3eIViUUZ4C3yQXTuEeL297djDKuMNQvJGna7ArId1NTAaugCIfk5MqCh8JIp7Y+KooMFENFC88jkDF1lJyQLuKUiugrWppeQIa4KsVDmy5zp021I5ovPKN6QCkw88Uy17hm8jOyWC3Zuao93uThb6XIyXoivvAzlr4Vyj3LPrEo+vfEQzLEGDYeDo X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8aa11b81-f53c-4d2d-6a0d-08d92738aa37 X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB8477.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2021 09:10:57.9963 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5bHwYZgO221PpqYXdshwdJ8Rjze2lHU6sLT8LLRxBh27NVVfPAdssbUepwBL6uODtajvJuQxDE1i+gulJD9ciw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8917 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: "Guoniu.zhou" Because digital pll for parallel interface is on by default, and not provide enable/disable function by scu, so add the related ops for this kind of clocks. Signed-off-by: Guoniu.zhou Signed-off-by: Dong Aisheng Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-scu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index f4efb3b76c86..680b2650fd45 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -425,6 +425,12 @@ static const struct clk_ops clk_scu_cpu_ops = { .unprepare = clk_scu_unprepare, }; +static const struct clk_ops clk_scu_pi_ops = { + .recalc_rate = clk_scu_recalc_rate, + .round_rate = clk_scu_round_rate, + .set_rate = clk_scu_set_rate, +}; + struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) @@ -445,6 +451,8 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, init.ops = &clk_scu_ops; if (rsrc_id == IMX_SC_R_A35) init.ops = &clk_scu_cpu_ops; + else if (rsrc_id == IMX_SC_R_PI_0_PLL) + init.ops = &clk_scu_pi_ops; else init.ops = &clk_scu_ops; init.parent_names = parents; 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Fri, 4 Jun 2021 09:11:01 +0000 From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, dongas86@gmail.com, shawnguo@kernel.org, kernel@pengutronix.de, abel.vesa@nxp.com, Dong Aisheng Subject: [PATCH 03/10] clk: imx: scu: bypass cpu clock save and restore Date: Fri, 4 Jun 2021 17:09:36 +0800 Message-Id: <20210604090943.3519350-4-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604090943.3519350-1-aisheng.dong@nxp.com> References: <20210604090943.3519350-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) To DB9PR04MB8477.eurprd04.prod.outlook.com (2603:10a6:10:2c3::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.24 via Frontend Transport; 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No need save and restore. Signed-off-by: Dong Aisheng Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-scu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 680b2650fd45..d87a1a1b297e 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -538,6 +538,11 @@ static int imx_clk_scu_probe(struct platform_device *pdev) static int __maybe_unused imx_clk_scu_suspend(struct device *dev) { struct clk_scu *clk = dev_get_drvdata(dev); + u32 rsrc_id = clk->rsrc_id; + + if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) || + (rsrc_id == IMX_SC_R_A72)) + return 0; clk->rate = clk_hw_get_rate(&clk->hw); clk->is_enabled = clk_hw_is_enabled(&clk->hw); @@ -554,8 +559,13 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev) static int __maybe_unused imx_clk_scu_resume(struct device *dev) { struct clk_scu *clk = dev_get_drvdata(dev); + u32 rsrc_id = clk->rsrc_id; int ret = 0; + if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) || + (rsrc_id == IMX_SC_R_A72)) + return 0; + if (clk->rate) { ret = clk_scu_set_rate(&clk->hw, clk->rate, 0); dev_dbg(dev, "restore rate %d %s\n", clk->rate, From patchwork Fri Jun 4 09:09:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 12299181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEE81C07E94 for ; Fri, 4 Jun 2021 09:11:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A6E0961411 for ; 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Signed-off-by: Dong Aisheng Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-scu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index d87a1a1b297e..95fcac7f73b6 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -512,6 +512,7 @@ static int imx_clk_scu_probe(struct platform_device *pdev) ret = pm_runtime_get_sync(dev); if (ret) { + pm_genpd_remove_device(dev); pm_runtime_disable(dev); return ret; } From patchwork Fri Jun 4 09:09:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 12299183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CCB7C07E94 for ; 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So bypass it's enable status restore. Signed-off-by: Dong Aisheng Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-scu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 95fcac7f73b6..2537e68ded16 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -573,7 +573,7 @@ static int __maybe_unused imx_clk_scu_resume(struct device *dev) !ret ? "success" : "failed"); } - if (clk->is_enabled) { + if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) { ret = clk_scu_prepare(&clk->hw); dev_dbg(dev, "restore enabled state %s\n", !ret ? "success" : "failed"); From patchwork Fri Jun 4 09:09:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 12299185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F80DC07E94 for ; Fri, 4 Jun 2021 09:11:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 07AE5613EA for ; Fri, 4 Jun 2021 09:11:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229973AbhFDJM6 (ORCPT ); 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Fri, 4 Jun 2021 09:11:10 +0000 From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, dongas86@gmail.com, shawnguo@kernel.org, kernel@pengutronix.de, abel.vesa@nxp.com, Anson Huang , Dong Aisheng Subject: [PATCH 06/10] clk: imx: scu: Add A53 frequency scaling support Date: Fri, 4 Jun 2021 17:09:39 +0800 Message-Id: <20210604090943.3519350-7-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604090943.3519350-1-aisheng.dong@nxp.com> References: <20210604090943.3519350-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) To DB9PR04MB8477.eurprd04.prod.outlook.com (2603:10a6:10:2c3::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.24 via Frontend Transport; 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Signed-off-by: Anson Huang Signed-off-by: Dong Aisheng --- drivers/clk/imx/clk-scu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 2537e68ded16..8b3eb58e6d12 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -273,7 +273,7 @@ static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate, struct arm_smccc_res res; unsigned long cluster_id; - if (clk->rsrc_id == IMX_SC_R_A35) + if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53) cluster_id = 0; else return -EINVAL; @@ -449,7 +449,7 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, init.name = name; init.ops = &clk_scu_ops; - if (rsrc_id == IMX_SC_R_A35) + if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53) init.ops = &clk_scu_cpu_ops; else if (rsrc_id == IMX_SC_R_PI_0_PLL) init.ops = &clk_scu_pi_ops; From patchwork Fri Jun 4 09:09:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 12299187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DD4CC07E94 for ; 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Signed-off-by: Anson Huang Signed-off-by: Dong Aisheng --- drivers/clk/imx/clk-scu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 8b3eb58e6d12..9f7ad3ca1039 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -275,6 +275,8 @@ static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate, if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53) cluster_id = 0; + else if (clk->rsrc_id == IMX_SC_R_A72) + cluster_id = 1; else return -EINVAL; @@ -449,7 +451,7 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, init.name = name; init.ops = &clk_scu_ops; - if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53) + if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || rsrc_id == IMX_SC_R_A72) init.ops = &clk_scu_cpu_ops; else if (rsrc_id == IMX_SC_R_PI_0_PLL) init.ops = &clk_scu_pi_ops; From patchwork Fri Jun 4 09:09:41 2021 Content-Type: text/plain; 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Fri, 4 Jun 2021 09:11:17 +0000 From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, dongas86@gmail.com, shawnguo@kernel.org, kernel@pengutronix.de, abel.vesa@nxp.com, Anson Huang , Dong Aisheng Subject: [PATCH 08/10] clk: imx: scu: Only save DC SS clock using non-cached clock rate Date: Fri, 4 Jun 2021 17:09:41 +0800 Message-Id: <20210604090943.3519350-9-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604090943.3519350-1-aisheng.dong@nxp.com> References: <20210604090943.3519350-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) To DB9PR04MB8477.eurprd04.prod.outlook.com (2603:10a6:10:2c3::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.24 via Frontend Transport; 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Signed-off-by: Anson Huang Signed-off-by: Dong Aisheng --- drivers/clk/imx/clk-scu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 9f7ad3ca1039..37919ffc46a2 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -547,7 +547,14 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev) (rsrc_id == IMX_SC_R_A72)) return 0; - clk->rate = clk_hw_get_rate(&clk->hw); + /* DC SS needs to handle bypass clock using non-cached clock rate */ + if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 || + clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 || + clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 || + clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1) + clk->rate = clk_scu_recalc_rate(&clk->hw, 0); + else + clk->rate = clk_hw_get_rate(&clk->hw); clk->is_enabled = clk_hw_is_enabled(&clk->hw); if (clk->rate) From patchwork Fri Jun 4 09:09:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 12299191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5221BC4708F for ; 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Signed-off-by: Dong Aisheng --- drivers/clk/imx/clk-scu.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 37919ffc46a2..597cd2754370 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -50,6 +50,8 @@ struct clk_scu { u8 clk_type; /* for state save&restore */ + struct clk_hw *parent; + u8 parent_index; bool is_enabled; u32 rate; }; @@ -337,6 +339,8 @@ static u8 clk_scu_get_parent(struct clk_hw *hw) return 0; } + clk->parent_index = msg.data.resp.parent; + return msg.data.resp.parent; } @@ -345,6 +349,7 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index) struct clk_scu *clk = to_clk_scu(hw); struct imx_sc_msg_set_clock_parent msg; struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; hdr->ver = IMX_SC_RPC_VERSION; hdr->svc = IMX_SC_RPC_SVC_PM; @@ -355,7 +360,16 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index) msg.clk = clk->clk_type; msg.parent = index; - return imx_scu_call_rpc(ccm_ipc_handle, &msg, true); + ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true); + if (ret) { + pr_err("%s: failed to set clock parent %d\n", + clk_hw_get_name(hw), ret); + return ret; + } + + clk->parent_index = index; + + return 0; } static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource, @@ -547,6 +561,8 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev) (rsrc_id == IMX_SC_R_A72)) return 0; + clk->parent = clk_hw_get_parent(&clk->hw); + /* DC SS needs to handle bypass clock using non-cached clock rate */ if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 || clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 || @@ -557,6 +573,10 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev) clk->rate = clk_hw_get_rate(&clk->hw); clk->is_enabled = clk_hw_is_enabled(&clk->hw); + if (clk->parent) + dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent), + clk->parent_index); + if (clk->rate) dev_dbg(dev, "save rate %d\n", clk->rate); @@ -576,6 +596,13 @@ static int __maybe_unused imx_clk_scu_resume(struct device *dev) (rsrc_id == IMX_SC_R_A72)) return 0; + if (clk->parent) { + ret = clk_scu_set_parent(&clk->hw, clk->parent_index); + dev_dbg(dev, "restore parent %s idx %u %s\n", + clk_hw_get_name(clk->parent), + clk->parent_index, !ret ? "success" : "failed"); + } + if (clk->rate) { ret = clk_scu_set_rate(&clk->hw, clk->rate, 0); dev_dbg(dev, "restore rate %d %s\n", clk->rate, From patchwork Fri Jun 4 09:09:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 12299193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBC19C4708F for ; Fri, 4 Jun 2021 09:11:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD61C613F3 for ; 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dmarc=none action=none header.from=nxp.com; Received: from DB9PR04MB8477.eurprd04.prod.outlook.com (2603:10a6:10:2c3::11) by DU2PR04MB8502.eurprd04.prod.outlook.com (2603:10a6:10:2d1::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.23; Fri, 4 Jun 2021 09:11:23 +0000 Received: from DB9PR04MB8477.eurprd04.prod.outlook.com ([fe80::508:d95f:f63b:714a]) by DB9PR04MB8477.eurprd04.prod.outlook.com ([fe80::508:d95f:f63b:714a%7]) with mapi id 15.20.4195.024; Fri, 4 Jun 2021 09:11:23 +0000 From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, dongas86@gmail.com, shawnguo@kernel.org, kernel@pengutronix.de, abel.vesa@nxp.com, Nitin Garg , Dong Aisheng Subject: [PATCH 10/10] clk: imx: scu: Do not enable runtime PM for CPU clks Date: Fri, 4 Jun 2021 17:09:43 +0800 Message-Id: <20210604090943.3519350-11-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604090943.3519350-1-aisheng.dong@nxp.com> References: <20210604090943.3519350-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) To DB9PR04MB8477.eurprd04.prod.outlook.com (2603:10a6:10:2c3::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR0601CA0010.apcprd06.prod.outlook.com (2603:1096:3::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.24 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 59ZGlZGmG6D1BEAeuBqAlcEso3PxHisw0/MhYqG4HB2OU2DNLzaki970/uS3ni6rA0OFoth4BlVbN8M2UIOA0V6uHJJqo5PcyHeJ7toenY03MV3mr6G/noG++tXULoUPWxNMw3URfR1yj3BbgEYWb7ZRpAjNXSI7mxl+CutfOMEfWqUUDshQfKn5mE5AXsbac3QFQL8KeSrNIvGjOZkNC/X1yhppDM0smfhNn3YwC7aH5k2MbZ9gfxEgYkZf97CfUcQdNs+VcMeT3Cl0bKiGWUPwPSePuxbYqU+dIM4dq+0dABtLlNXE2MQ89QznIUUiENYB6nHTQpHPmzhxb0wjHWBIUXanvpsVYHsB2nvyeW1CMI0XI3xGmGVYEeqXdf2NJkRmS2a9hIN/z0w5ZfS/ga9m7x34UMiA1sCD+nT7XZ/ms4NSu8ctDDIq53+zRZalyzXZgh03dgwPPsszYoXIXSUJgATT8m6ruf7xLoRZDxkR/iAPxt78X/sTO5ID9gULxCv1pUsCeG4sWv/7dO9KMQwiDw4UZOoJ9qrgbpc9DlHsves1YAwlRNIVwTRrqZkKugblrOI+UXPPK0/L9eBjC18PZGHWZiqlvxGTUO9PY3GmusvYcQpkn+7o+PGHNIcBR8f9avotgBH2noC299lMgSKOoFKrTiFpx2+fwi5zJ/pGY+dayQX4A6So/APrfkZCn0d1LCVpAoNlEZiW0fOONDVpIAWbhLE8JP9VN7hsr/BmSXPcJ/qlto/uq2UcCS5sMiQzGpZ3cdpWiQ3QGXNPhGz+IDz0hGh0gFLbgfmDaZ3BcMrumpR2q2t9pHGx52ZHpUWVSLgwuO9klRDo7GjaoFkQe84Z146bNBaazNrBKi5UFIaKf8zkg6MYJpUemCuGHpYRBX3nQp07zLeXLFg3qHkRbeCsL5dc0xA8/szes/th9DUz1dJUmu3WqrKGG/SU+e4SRqeqhv0egscCCRcYK08HSDz+TNfni/abYOV6qOPOXqNrH1bS5WgdyKsAeeF+QOPy/rAhfIuiGpJrZPP4f5aQBXzdl3Wyqsg3GbHlOqosqXqGRiV/Tp2S8FYFw8Prva2qc0DM2D6Xwn0x4kvpASFR8ZqgCU7T8dk3UN/FpmUDEWp2QJPh2Mdn/OAECcpTGxXkRNZ0ZNFh0EaVG0/tQJypnwRoLiAI9dCMZbefmcWn3G5q2bhTIAMNCoIDiy82r/D2ym2pYJ/dVFK9AW39l7hGu/8a5Knj7lNtWcN8pEzYzNWumiAXZ4A83Uf8wZLBe1rPTgRRkl+gLyZndqUYAc2iHUFScvZMgI5GhR/xBRhumQdUwplu+WTaDkiAGYQX X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 528c5fef-7320-4d06-2a81-08d92738b93c X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB8477.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2021 09:11:23.0489 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: miP8fTMNWHluvV9UhCAPWXhqbzVnfU358jegwsNjCHFWebUZy6VSqXLg6Mz35K7jlTC5N28+qkZwIyOdRFJTlA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8502 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Nitin Garg Since CPU clocks are managed by CPUFREQ and ATF, do not enable runtime PM otherwise rpm gets out of status as cpufreq also manages clock states. Signed-off-by: Nitin Garg Signed-off-by: Dong Aisheng --- drivers/clk/imx/clk-scu.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 597cd2754370..083da31dc3ea 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -521,16 +521,19 @@ static int imx_clk_scu_probe(struct platform_device *pdev) struct clk_hw *hw; int ret; - pm_runtime_set_suspended(dev); - pm_runtime_set_autosuspend_delay(dev, 50); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(dev); - - ret = pm_runtime_get_sync(dev); - if (ret) { - pm_genpd_remove_device(dev); - pm_runtime_disable(dev); - return ret; + if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) || + (clk->rsrc == IMX_SC_R_A72))) { + pm_runtime_set_suspended(dev); + pm_runtime_set_autosuspend_delay(dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(dev); + + ret = pm_runtime_get_sync(dev); + if (ret) { + pm_genpd_remove_device(dev); + pm_runtime_disable(dev); + return ret; + } } hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents, @@ -543,8 +546,11 @@ static int imx_clk_scu_probe(struct platform_device *pdev) clk->hw = hw; list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]); - pm_runtime_mark_last_busy(&pdev->dev); - pm_runtime_put_autosuspend(&pdev->dev); + if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) || + (clk->rsrc == IMX_SC_R_A72))) { + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + } dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc, clk->clk_type);