From patchwork Tue Jun 8 03:16:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kewei Xu X-Patchwork-Id: 12305229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 834E8C47082 for ; Tue, 8 Jun 2021 03:20:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 504D661078 for ; Tue, 8 Jun 2021 03:20:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 504D661078 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GRPBtu4I2zBUKjwyA7vHINvKXdxcVr444IffDyVdCo8=; b=zumNOP0CMAeBVR EB2pCa189Fiy5m2haBTdtIZRJvNMvir7o56sj3H14t0Iz9g8pDykp6YHIJJKaG648UT2bFQSSh/Zm pZXzgXY6R69iOqZREkpNfgcglIABtk9iQVxSr7sJCwJ8mFA//+0klWZvw0SgyetSQ9MLraAZf16h+ JQQH6VSRgE/hZ9a+gtQ+FwiM999lofw/Vqa257Ca7kgp8xQUcqdq8jku1ViR0sodh+d5CYuUISKxF 3V0unj0n+4wOkotwPYA4LPCwpjDJ7iEG/RUn6vlQoMmYR/W91z/Aj6Jg826Cfh0d6b/4ux2S1btlQ LAX7Eu+ovcL17A/WwoHw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqSFV-006Eik-DI; Tue, 08 Jun 2021 03:17:53 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqSFP-006EgR-AR; Tue, 08 Jun 2021 03:17:51 +0000 X-UUID: 3aa7ea0f2e824767b125821cf5521d3e-20210607 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Pt3AMawz5FG/qTN6qkhCigOvaWKnxaiX6OvqzCO97sg=; b=N2eVO32J30BTCNOvDkFGGEzu+NDAt9Ql4ga12/TavnKnQQOf7pgqFwbe5pp9HA9/amwcIZ6z4UnIClT5CYbm2SZnzCX9l5IcEyylVJDYdbehrShwjMB9HsvTLmEKrtBcGeETlUHIoO9hXdZPSV5LxVYT9hDQIk01UQAe3pGEYhE=; X-UUID: 3aa7ea0f2e824767b125821cf5521d3e-20210607 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1112376948; Mon, 07 Jun 2021 20:17:43 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Jun 2021 20:17:41 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Jun 2021 11:17:40 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Jun 2021 11:17:39 +0800 From: Kewei Xu To: CC: , , , , , , , , , , , Subject: [PATCH 1/3] dt-bindings: i2c: update bindings for MT8195 SoC Date: Tue, 8 Jun 2021 11:16:38 +0800 Message-ID: <1623122200-1896-2-git-send-email-kewei.xu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1623122200-1896-1-git-send-email-kewei.xu@mediatek.com> References: <1623122200-1896-1-git-send-email-kewei.xu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210607_201747_398902_73B2A1D5 X-CRM114-Status: GOOD ( 10.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: "Kewei.Xu" Add a DT binding documentation for the MT8195 soc. Signed-off-by: Kewei.Xu Reviewed-by: Matthias Brugger Acked-by: Rob Herring --- Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt index 7f0194f..7c4915bc 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt @@ -15,6 +15,7 @@ Required properties: "mediatek,mt8173-i2c": for MediaTek MT8173 "mediatek,mt8183-i2c": for MediaTek MT8183 "mediatek,mt8192-i2c": for MediaTek MT8192 + "mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195 "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516 - reg: physical base address of the controller and dma base, length of memory mapped region. From patchwork Tue Jun 8 03:16:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kewei Xu X-Patchwork-Id: 12305231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6DBFC47082 for ; Tue, 8 Jun 2021 03:21:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A393560FF1 for ; Tue, 8 Jun 2021 03:21:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A393560FF1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Id6TkomBkV+0LGIjF5O1shkp3kJlgEVklV1p2nlG3HY=; b=yKia+XN8h1w3nJ 3+VIPFNAOqcts34//4s697SvqaJlk8IFkv0ncZ0bTT5/MW/Dm5auyiVFAOXJswvlxYFpJSqeVFhK1 s/mRRknM6IvzSOM9z+HCs3M/LLVd4lM/R/x64m1BESeaz3UGh8DaC+6EGeBxlVplgnvMUhCoAn6Mk JleXfxfAFQmuW95Fq35/wmFF5ugVisYoILoZYUC54QlenvpKMJeam2yFDUt8pzMyyCXxcxyBkAEOg L5fxuYIS4IQqq1zvGiLM+CG4ntPl5assUGEVWi60KhkEbuugEMRKvX7APRMbJP1zz5dGlNeXwWx54 MtE8G+3TDHWQ0hiffiQQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqSHY-006F0m-Vq; Tue, 08 Jun 2021 03:20:01 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqSHS-006Eza-Bg; Tue, 08 Jun 2021 03:19:58 +0000 X-UUID: 572c6e5b7bad4394998bcef346610009-20210607 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FY7Ce0xJvq4LJ731PRwTtnud7YE8r70EXPGDlBMrlRw=; b=QXH7SGXSXDo2rnClGx+4xtjlKMDdCGUJHTgXsSoLYSrEavnyC/el4OnU5t/7NydNKV1b0rXR6svr8xaNyeeAUoiCUxLvnxfOpMh4WeKwRXHow1r+Z6VPOcueigc6NkkjUz5qfIglq/oLhyTIdlwF+fBZ39iw5srh+AwBLdWgtvo=; X-UUID: 572c6e5b7bad4394998bcef346610009-20210607 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1926612906; Mon, 07 Jun 2021 20:19:51 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Jun 2021 20:17:42 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Jun 2021 11:17:40 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Jun 2021 11:17:40 +0800 From: Kewei Xu To: CC: , , , , , , , , , , , Subject: [PATCH 2/3] i2c: mediatek: Dump i2c/dma register when a timeout occurs Date: Tue, 8 Jun 2021 11:16:39 +0800 Message-ID: <1623122200-1896-3-git-send-email-kewei.xu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1623122200-1896-1-git-send-email-kewei.xu@mediatek.com> References: <1623122200-1896-1-git-send-email-kewei.xu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210607_201954_436037_57FA61A2 X-CRM114-Status: GOOD ( 13.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: "Kewei.Xu" When a timeout error occurs in i2c transter, it is usually related to the i2c/dma IP hardware configuration. Therefore, the purpose of this patch is to dump the key register values of i2c/dma when a timeout occurs in i2c for debugging. Signed-off-by: Kewei.Xu --- drivers/i2c/busses/i2c-mt65xx.c | 97 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index 5ddfa4e..e65a41e 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -125,6 +125,7 @@ enum I2C_REGS_OFFSET { OFFSET_HS, OFFSET_SOFTRESET, OFFSET_DCM_EN, + OFFSET_MULTI_DMA, OFFSET_PATH_DIR, OFFSET_DEBUGSTAT, OFFSET_DEBUGCTRL, @@ -192,8 +193,9 @@ enum I2C_REGS_OFFSET { [OFFSET_TRANSFER_LEN_AUX] = 0x44, [OFFSET_CLOCK_DIV] = 0x48, [OFFSET_SOFTRESET] = 0x50, + [OFFSET_MULTI_DMA] = 0x84, [OFFSET_SCL_MIS_COMP_POINT] = 0x90, - [OFFSET_DEBUGSTAT] = 0xe0, + [OFFSET_DEBUGSTAT] = 0xe4, [OFFSET_DEBUGCTRL] = 0xe8, [OFFSET_FIFO_STAT] = 0xf4, [OFFSET_FIFO_THRESH] = 0xf8, @@ -828,6 +830,96 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) return 0; } +static void i2c_dump_register(struct mtk_i2c *i2c) +{ + dev_err(i2c->dev, "SLAVE_ADDR[0x%x]: 0x%x, INTR_MASK[0x%x]: 0x%x\n", + OFFSET_SLAVE_ADDR, + (mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR)), + OFFSET_INTR_MASK, + (mtk_i2c_readw(i2c, OFFSET_INTR_MASK))); + dev_err(i2c->dev, "INTR_STAT[0x%x]: 0x%x, CONTROL[0x%x]: 0x%x\n", + OFFSET_INTR_STAT, + (mtk_i2c_readw(i2c, OFFSET_INTR_STAT)), + OFFSET_CONTROL, + (mtk_i2c_readw(i2c, OFFSET_CONTROL))); + dev_err(i2c->dev, "TRANSFER_LEN[0x%x]: 0x%x, TRANSAC_LEN[0x%x]: 0x%x\n", + OFFSET_TRANSFER_LEN, + (mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN)), + OFFSET_TRANSAC_LEN, + (mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN))); + dev_err(i2c->dev, "DELAY_LEN[0x%x]: 0x%x, HTIMING[0x%x]: 0x%x\n", + OFFSET_DELAY_LEN, + (mtk_i2c_readw(i2c, OFFSET_DELAY_LEN)), + OFFSET_TIMING, + (mtk_i2c_readw(i2c, OFFSET_TIMING))); + dev_err(i2c->dev, "OFFSET_START[0x%x]: 0x%x\n", + OFFSET_START, + mtk_i2c_readw(i2c, OFFSET_START)); + dev_err(i2c->dev, "OFFSET_EXT_CONF[0x%x]: 0x%x\n", + OFFSET_EXT_CONF, + mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); + dev_err(i2c->dev, "OFFSET_HS[0x%x]: 0x%x\n", + OFFSET_HS, + mtk_i2c_readw(i2c, OFFSET_HS)); + dev_err(i2c->dev, "OFFSET_IO_CONFIG[0x%x]: 0x%x\n", + OFFSET_IO_CONFIG, + mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); + dev_err(i2c->dev, "OFFSET_FIFO_ADDR_CLR[0x%x]: 0x%x\n", + OFFSET_FIFO_ADDR_CLR, + mtk_i2c_readw(i2c, OFFSET_FIFO_ADDR_CLR)); + dev_err(i2c->dev, "TRANSFER_LEN_AUX[0x%x]: 0x%x\n", + OFFSET_TRANSFER_LEN_AUX, + mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); + dev_err(i2c->dev, "CLOCK_DIV[0x%x]: 0x%x\n", + OFFSET_CLOCK_DIV, + mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV)); + dev_err(i2c->dev, "FIFO_STAT[0x%x]: 0x%x, FIFO_THRESH[0x%x]: 0x%x\n", + OFFSET_FIFO_STAT, + mtk_i2c_readw(i2c, OFFSET_FIFO_STAT), + OFFSET_FIFO_THRESH, + mtk_i2c_readw(i2c, OFFSET_FIFO_THRESH)); + dev_err(i2c->dev, "DCM_EN[0x%x] 0x%x\n", + OFFSET_DCM_EN, + mtk_i2c_readw(i2c, OFFSET_DCM_EN)); + dev_err(i2c->dev, "DEBUGSTAT[0x%x]: 0x%x, DEBUGCTRL[0x%x]: 0x%x\n", + OFFSET_DEBUGSTAT, + (mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)), + OFFSET_DEBUGCTRL, + (mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL))); + + if (i2c->dev_comp->regs == mt_i2c_regs_v2) { + dev_err(i2c->dev, "OFFSET_LTIMING[0x%x]: 0x%x\n", + OFFSET_LTIMING, + mtk_i2c_readw(i2c, OFFSET_LTIMING)); + dev_err(i2c->dev, "MULTI_DMA[0x%x]: 0x%x\n", + OFFSET_MULTI_DMA, + (mtk_i2c_readw(i2c, OFFSET_MULTI_DMA))); + } + + dev_err(i2c->dev, "OFFSET_INT_FLAG = 0x%x\n", + readl(i2c->pdmabase + OFFSET_INT_FLAG)); + dev_err(i2c->dev, "OFFSET_INT_EN = 0x%x\n", + readl(i2c->pdmabase + OFFSET_INT_EN)); + dev_err(i2c->dev, "OFFSET_EN = 0x%x\n", + readl(i2c->pdmabase + OFFSET_EN)); + dev_err(i2c->dev, "OFFSET_RST = 0x%x\n", + readl(i2c->pdmabase + OFFSET_RST)); + dev_err(i2c->dev, "OFFSET_CON = 0x%x\n", + readl(i2c->pdmabase + OFFSET_CON)); + dev_err(i2c->dev, "OFFSET_TX_MEM_ADDR = 0x%x\n", + readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR)); + dev_err(i2c->dev, "OFFSET_RX_MEM_ADDR = 0x%x\n", + readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); + dev_err(i2c->dev, "OFFSET_TX_LEN = 0x%x\n", + readl(i2c->pdmabase + OFFSET_TX_LEN)); + dev_err(i2c->dev, "OFFSET_RX_LEN = 0x%x\n", + readl(i2c->pdmabase + OFFSET_RX_LEN)); + dev_err(i2c->dev, "OFFSET_TX_4G_MODE = 0x%x\n", + readl(i2c->pdmabase + OFFSET_TX_4G_MODE)); + dev_err(i2c->dev, "OFFSET_RX_4G_MODE = 0x%x\n", + readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); +} + static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, int num, int left_num) { @@ -1034,7 +1126,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, } if (ret == 0) { - dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); + dev_err(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); + i2c_dump_register(i2c); mtk_i2c_init_hw(i2c); return -ETIMEDOUT; } From patchwork Tue Jun 8 03:16:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kewei Xu X-Patchwork-Id: 12305241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F2D8C47094 for ; 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Tue, 8 Jun 2021 11:17:40 +0800 From: Kewei Xu To: CC: , , , , , , , , , , , Subject: [PATCH 3/3] i2c: mediatek: Reset the handshake signal between i2c and dma Date: Tue, 8 Jun 2021 11:16:40 +0800 Message-ID: <1623122200-1896-4-git-send-email-kewei.xu@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1623122200-1896-1-git-send-email-kewei.xu@mediatek.com> References: <1623122200-1896-1-git-send-email-kewei.xu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210607_202610_600856_A28544C7 X-CRM114-Status: GOOD ( 10.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: "Kewei.Xu" Due to changes in the hardware design of the handshaking signal between i2c and dma, it is necessary to reset the handshaking signal before each transfer to ensure that the multi-msgs can be transferred correctly. Signed-off-by: Kewei.Xu --- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index e65a41e..ded94f9 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -47,6 +47,9 @@ #define I2C_RD_TRANAC_VALUE 0x0001 #define I2C_SCL_MIS_COMP_VALUE 0x0000 #define I2C_CHN_CLR_FLAG 0x0000 +#define I2C_CLR_DEBUGCTR 0x0000 +#define I2C_RELIABILITY 0x0010 +#define I2C_DMAACK_ENABLE 0x0008 #define I2C_DMA_CON_TX 0x0000 #define I2C_DMA_CON_RX 0x0001 @@ -942,6 +945,17 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, reinit_completion(&i2c->msg_complete); + if (i2c->dev_comp->apdma_sync) { + mtk_i2c_writew(i2c, I2C_CLR_DEBUGCTR, OFFSET_DEBUGCTRL); + writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, + i2c->pdmabase + OFFSET_RST); + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); + mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET); + mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); + mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, + OFFSET_DEBUGCTRL); + } + control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))