From patchwork Wed Jun 9 14:01:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12310207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65B97C48BCD for ; Wed, 9 Jun 2021 14:03:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F55661351 for ; Wed, 9 Jun 2021 14:03:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237249AbhFIOFB (ORCPT ); Wed, 9 Jun 2021 10:05:01 -0400 Received: from mail-wr1-f54.google.com ([209.85.221.54]:40939 "EHLO mail-wr1-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237226AbhFIOE7 (ORCPT ); Wed, 9 Jun 2021 10:04:59 -0400 Received: by mail-wr1-f54.google.com with SMTP id y7so20982706wrh.7; Wed, 09 Jun 2021 07:03:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7yE+bj7E/38rPyfMQ2Y7dkil8U8S07gxBd4g0tEIxB0=; b=WB0mQW93aLe0XCJEduYwuCEbPh8fSgth2vOFaI9jksGO436mZxlTOCOi9B4RCUiW9B YB5Yl1P/wPzg4MUG/7j2k4AHMzYqhD9f82sYCGfw2LGJ4zk6KoId+LUtv2wNxP2nukI3 wotwnRRvd8d17fUr1tww/Dh19h+2xNCpkCVg2FZq4gFFhZ/j3kzBfl/EBcK1b+Z1y49/ ydxGyBsu4lKEfbC1HKolK5fkmgosTJKR203dA0D+OgCKTrw28luKbTD8zs2bzce9JeiM qtp+lID54399quyLhqBQpOAeVbV0CBFh0w8WSYTQZV5VjMgwaKEM4QbIof1fBGwYF2K0 T/aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7yE+bj7E/38rPyfMQ2Y7dkil8U8S07gxBd4g0tEIxB0=; b=D1xKC/ZhZWJ4WgFju5iZpt/+tdD8QKX93qF91aKOxOpn+tZo0CKQ3EHSw4KZ+Z/fxv NkV6POFuZr3iEe7i9CoGRPj5UkaIWFRotHgsW2dkH8BAPM5DjUnpS/gIao6OfEtIJpRh IHLhEUqBNxHMom+Wf03i4h31TrowMzYh4SqZD6tyf3AJxczz8qxoFXFjZER2o3YOBTe4 gi9UUlWe0hKHiv1rqE9zfW6J6gjeH/LQxh+wIiD+o8B9zyTjn9hoXxoQa44Ahhan/mFM euAFWLMgZsncmYemwTauQtR+/0z3ci9Gk/A6G3xKqQcbgwwQUWza/7pBTaIpK251PxHA ns1A== X-Gm-Message-State: AOAM531gB4c26KlLtvZW0300/l8Sky5k6tQlZT3JHH/zE/LPsghhQsSV ns9CDoUJ7snnCgoHY/ieJuowmudRtMANtA== X-Google-Smtp-Source: ABdhPJwcu313t4cHLi5huMgbhItuz+9FzoqplAwz1E0g+t8h/trcjldWLl02okuffAMbvIZ3ozVdGQ== X-Received: by 2002:a5d:6c6d:: with SMTP id r13mr28364425wrz.350.1623247323612; Wed, 09 Jun 2021 07:02:03 -0700 (PDT) Received: from localhost.localdomain (103.red-81-47-144.staticip.rima-tde.net. [81.47.144.103]) by smtp.gmail.com with ESMTPSA id m23sm5673912wms.2.2021.06.09.07.02.02 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Jun 2021 07:02:03 -0700 (PDT) From: Sergio Paracuellos To: linux-pci@vger.kernel.org Cc: linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, devicetree@vger.kernel.org, matthias.bgg@gmail.com, john@phrozen.org, bhelgaas@google.com, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com, linux-kernel@vger.kernel.org, pali@kernel.org Subject: [PATCH v2 1/3] dt-bindings: mt7621-pci: PCIe binding documentation for MT7621 SoCs Date: Wed, 9 Jun 2021 16:01:57 +0200 Message-Id: <20210609140159.20476-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210609140159.20476-1-sergio.paracuellos@gmail.com> References: <20210609140159.20476-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add device tree binding documentation for PCIe in MT7621 SoCs. Signed-off-by: Sergio Paracuellos Reviewed-by: Rob Herring --- .../bindings/pci/mediatek,mt7621-pci.yaml | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml new file mode 100644 index 000000000000..716b77d6c830 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7621 PCIe controller + +maintainers: + - Sergio Paracuellos + +description: |+ + MediaTek MT7621 PCIe subsys supports single Root complex (RC) + with 3 Root Ports. Each Root Ports supports a Gen1 1-lane Link + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: mediatek,mt7621-pci + + reg: + items: + - description: host-pci bridge registers + - description: pcie port 0 RC control registers + - description: pcie port 1 RC control registers + - description: pcie port 2 RC control registers + + ranges: + maxItems: 2 + +patternProperties: + 'pcie@[0-2],0': + type: object + $ref: /schemas/pci/pci-bus.yaml# + + properties: + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + phys: + maxItems: 1 + + required: + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + - resets + - clocks + - phys + - phy-names + - ranges + + unevaluatedProperties: false + +required: + - compatible + - reg + - ranges + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + + pcie: pcie@1e140000 { + compatible = "mediatek,mt7621-pci"; + reg = <0x1e140000 0x100>, + <0x1e142000 0x100>, + <0x1e143000 0x100>, + <0x1e144000 0x100>; + + #address-cells = <3>; + #size-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + device_type = "pci"; + ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */ + <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xF800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 24>; + clocks = <&clkctrl 24>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy0"; + ranges; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 25>; + clocks = <&clkctrl 25>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy1"; + ranges; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstctrl 26>; + clocks = <&clkctrl 26>; + phys = <&pcie2_phy 0>; + phy-names = "pcie-phy2"; + ranges; + }; + }; +... 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[81.47.144.103]) by smtp.gmail.com with ESMTPSA id m23sm5673912wms.2.2021.06.09.07.02.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Jun 2021 07:02:04 -0700 (PDT) From: Sergio Paracuellos To: linux-pci@vger.kernel.org Cc: linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, devicetree@vger.kernel.org, matthias.bgg@gmail.com, john@phrozen.org, bhelgaas@google.com, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com, linux-kernel@vger.kernel.org, pali@kernel.org Subject: [PATCH v2 2/3] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver Date: Wed, 9 Jun 2021 16:01:58 +0200 Message-Id: <20210609140159.20476-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210609140159.20476-1-sergio.paracuellos@gmail.com> References: <20210609140159.20476-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add driver for the PCIe controller of the MT7621 SoC. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos --- arch/mips/ralink/Kconfig | 2 +- drivers/pci/controller/Kconfig | 8 ++ drivers/pci/controller/Makefile | 1 + .../controller}/pci-mt7621.c | 0 drivers/staging/Kconfig | 2 - drivers/staging/Makefile | 1 - drivers/staging/mt7621-pci/Kconfig | 8 -- drivers/staging/mt7621-pci/Makefile | 2 - drivers/staging/mt7621-pci/TODO | 4 - .../mt7621-pci/mediatek,mt7621-pci.txt | 104 ------------------ 10 files changed, 10 insertions(+), 122 deletions(-) rename drivers/{staging/mt7621-pci => pci/controller}/pci-mt7621.c (100%) delete mode 100644 drivers/staging/mt7621-pci/Kconfig delete mode 100644 drivers/staging/mt7621-pci/Makefile delete mode 100644 drivers/staging/mt7621-pci/TODO delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index ec4daa63c5e3..461e33d20c9c 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -56,7 +56,7 @@ choice select MIPS_GIC select COMMON_CLK select CLKSRC_MIPS_GIC - select HAVE_PCI if PCI_MT7621 + select HAVE_PCI select SOC_BUS endchoice diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 2f2c8a1729f9..6b006df87884 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -303,6 +303,14 @@ config PCIE_HISI_ERR Say Y here if you want error handling support for the PCIe controller's errors on HiSilicon HIP SoCs +config PCI_MT7621 + bool "MediaTek MT7621 PCI Controller" + depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST) + select PCI_DRIVERS_GENERIC + default SOC_MT7621 + help + This selects a driver for the MediaTek MT7621 PCI Controller. + source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/mobiveil/Kconfig" source "drivers/pci/controller/cadence/Kconfig" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index 63e3880a3e87..ac902dc4e1a9 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_VMD) += vmd.o obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o +obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ obj-y += mobiveil/ diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/pci/controller/pci-mt7621.c similarity index 100% rename from drivers/staging/mt7621-pci/pci-mt7621.c rename to drivers/pci/controller/pci-mt7621.c diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index b7ae5bdc4eb5..9a21d730ab2b 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kconfig" source "drivers/staging/pi433/Kconfig" -source "drivers/staging/mt7621-pci/Kconfig" - source "drivers/staging/mt7621-dma/Kconfig" source "drivers/staging/ralink-gdma/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 075c979bfe7c..b7b4916761d4 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010) += ks7010/ obj-$(CONFIG_GREYBUS) += greybus/ obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/ obj-$(CONFIG_PI433) += pi433/ -obj-$(CONFIG_PCI_MT7621) += mt7621-pci/ obj-$(CONFIG_SOC_MT7621) += mt7621-dma/ obj-$(CONFIG_DMA_RALINK) += ralink-gdma/ obj-$(CONFIG_SOC_MT7621) += mt7621-dts/ diff --git a/drivers/staging/mt7621-pci/Kconfig b/drivers/staging/mt7621-pci/Kconfig deleted file mode 100644 index ce58042f2f21..000000000000 --- a/drivers/staging/mt7621-pci/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config PCI_MT7621 - tristate "MediaTek MT7621 PCI Controller" - depends on RALINK - select PCI_DRIVERS_GENERIC - help - This selects a driver for the MediaTek MT7621 PCI Controller. - diff --git a/drivers/staging/mt7621-pci/Makefile b/drivers/staging/mt7621-pci/Makefile deleted file mode 100644 index f4e651cf7ce3..000000000000 --- a/drivers/staging/mt7621-pci/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o diff --git a/drivers/staging/mt7621-pci/TODO b/drivers/staging/mt7621-pci/TODO deleted file mode 100644 index d674a9ac85c1..000000000000 --- a/drivers/staging/mt7621-pci/TODO +++ /dev/null @@ -1,4 +0,0 @@ - -- general code review and cleanup - -Cc: NeilBrown diff --git a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt b/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt deleted file mode 100644 index 327a68267309..000000000000 --- a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt +++ /dev/null @@ -1,104 +0,0 @@ -MediaTek MT7621 PCIe controller - -Required properties: -- compatible: "mediatek,mt7621-pci" -- device_type: Must be "pci" -- reg: Base addresses and lengths of the PCIe subsys and root ports. -- bus-range: Range of bus numbers associated with this controller. -- #address-cells: Address representation for root ports (must be 3) -- pinctrl-names : The pin control state names. -- pinctrl-0: The "default" pinctrl state. -- #size-cells: Size representation for root ports (must be 2) -- ranges: Ranges for the PCI memory and I/O regions. -- #interrupt-cells: Must be 1 -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties. - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- status: either "disabled" or "okay". -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of - root ports. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of - root ports. -- reset-gpios: GPIO specs for the reset pins. - -In addition, the device tree node must have sub-nodes describing each PCIe port -interface, having the following mandatory properties: - -Required properties: -- reg: Only the first four bytes are used to refer to the correct bus number - and device number. -- #address-cells: Must be 3 -- #size-cells: Must be 2 -- ranges: Sub-ranges distributed from the PCIe controller node. An empty - property is sufficient. -- bus-range: Range of bus numbers associated with this port. - -Example for MT7621: - - pcie: pcie@1e140000 { - compatible = "mediatek,mt7621-pci"; - reg = <0x1e140000 0x100 /* host-pci bridge registers */ - 0x1e142000 0x100 /* pcie port 0 RC control registers */ - 0x1e143000 0x100 /* pcie port 1 RC control registers */ - 0x1e144000 0x100>; /* pcie port 2 RC control registers */ - - #address-cells = <3>; - #size-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - - device_type = "pci"; - - bus-range = <0 255>; - ranges = < - 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ - 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ - >; - - #interrupt-cells = <1>; - interrupt-map-mask = <0xF0000 0 0 1>; - interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, - <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, - <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - - status = "disabled"; - - resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; - reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; - clock-names = "pcie0", "pcie1", "pcie2"; - - reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>, - <&gpio 8 GPIO_ACTIVE_LOW>, - <&gpio 7 GPIO_ACTIVE_LOW>; - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - bus-range = <0x00 0xff>; - }; - - pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - bus-range = <0x00 0xff>; - }; - - pcie@2,0 { - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - bus-range = <0x00 0xff>; - }; - }; - From patchwork Wed Jun 9 14:01:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12310209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85DB6C48BE0 for ; Wed, 9 Jun 2021 14:03:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D59461351 for ; Wed, 9 Jun 2021 14:03:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237226AbhFIOFD (ORCPT ); Wed, 9 Jun 2021 10:05:03 -0400 Received: from mail-wr1-f41.google.com ([209.85.221.41]:37853 "EHLO mail-wr1-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237227AbhFIOFC (ORCPT ); Wed, 9 Jun 2021 10:05:02 -0400 Received: by mail-wr1-f41.google.com with SMTP id i94so20589360wri.4; Wed, 09 Jun 2021 07:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AYWDI6BG8IdRoFPaJz/bP9vC9WkcUEC9Y1+RTob9aXc=; b=b5m4IM3yjBet0AWST2O9Jpwxqjd2kDUCn92XMVhC72ujjOfkDoVI4N41Z0NTFy5VpE OglH+M9cHy9M3rUqXKcFYPNr3qBW51d5WebmAHdVIjFkUcfVn3F3Y8Q6Rxt5HpJl2DK7 PFdUjeD0uO+NFVCQJHsP2sUMqtC5aA3tbVEKs9gJNFHh3c4rkVAe7k8QLlKkoK5QxtkU o3Gdi6kAVjOU2MnTvDPB5oFQT3IhDOoM/eJyQK9ABnYQvXqYBgT09bo29dStiR32Hakl onIiJnMpNpr6WheKCJTWb8PyeY+SFdBNaflEzsojeh306rMxNJh+2ipkEMCRXTL6/bRb 6M1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AYWDI6BG8IdRoFPaJz/bP9vC9WkcUEC9Y1+RTob9aXc=; b=NNd2FnlS2I6499ZEdHcrcmTKgqKQVHdfgGVu9BhGGHSlhhcl9AJqXKvcsL+Btg+I9T cL4r76wJ+p0Tu4P6rO8Dznm3QU+Dj1gYW4cXwH4l6fSAfaxqpnKb3EYe6uLmSve4TDjF UctlXA1yxJx55nrcQ0yIa4Bophc3KETzItYC3HeslngeZXmtEvsKpy6mMHAiCS7T5VWs LRE0t47lMuQsNvI9Gr81tztaOqlluUjStwFocqv9y4M+q8kHbvVnyWlzrElDRNQTwaVk 4B+3oc4+3HhDeN+L8+/Dae3cOzdP3H76JLHjBXQaULGurvZK/aCApdcgs+f2nNQJAdzu wJcg== X-Gm-Message-State: AOAM533hFj/LViusQeXAmhJz5w+ty5gZ6J5gmXbD23zrFtweMBTOIIfD NmjX6x/yTRLCD6f8qw5jtbTBVDvj125Dfg== X-Google-Smtp-Source: ABdhPJyyaptNj1K8oWVB9T8IptJSFw4/2SNsjIpbwawKmVfW8s1K4w8ilEL0kkh4lazfgShnc3pfhQ== X-Received: by 2002:adf:e401:: with SMTP id g1mr27533771wrm.415.1623247325881; Wed, 09 Jun 2021 07:02:05 -0700 (PDT) Received: from localhost.localdomain (103.red-81-47-144.staticip.rima-tde.net. [81.47.144.103]) by smtp.gmail.com with ESMTPSA id m23sm5673912wms.2.2021.06.09.07.02.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Jun 2021 07:02:05 -0700 (PDT) From: Sergio Paracuellos To: linux-pci@vger.kernel.org Cc: linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, devicetree@vger.kernel.org, matthias.bgg@gmail.com, john@phrozen.org, bhelgaas@google.com, robh+dt@kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com, linux-kernel@vger.kernel.org, pali@kernel.org Subject: [PATCH v2 3/3] MAINTAINERS: add myself as maintainer of the MT7621 PCI controller driver Date: Wed, 9 Jun 2021 16:01:59 +0200 Message-Id: <20210609140159.20476-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210609140159.20476-1-sergio.paracuellos@gmail.com> References: <20210609140159.20476-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add myself as maintainer of the PCie Controlller driver for MT7621 SoCs. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9c55fdcc1514..2e58fba01289 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11574,6 +11574,12 @@ S: Maintained F: Documentation/devicetree/bindings/i2c/i2c-mt7621.txt F: drivers/i2c/busses/i2c-mt7621.c +MEDIATEK MT7621 PCI CONTROLLER DRIVER +M: Sergio Paracuellos +S: Maintained +F: Documentation/devicetree/bindings/pci/mediatek,mt7621-pci.yaml +F: drivers/pci/controller/pci-mt7621.c + MEDIATEK MT7621 PHY PCI DRIVER M: Sergio Paracuellos S: Maintained