From patchwork Thu Jun 10 20:05:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 12313859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8225C48BDF for ; Thu, 10 Jun 2021 20:05:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF4816136D for ; Thu, 10 Jun 2021 20:05:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230416AbhFJUHl (ORCPT ); Thu, 10 Jun 2021 16:07:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230392AbhFJUHl (ORCPT ); Thu, 10 Jun 2021 16:07:41 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B198C061760; Thu, 10 Jun 2021 13:05:32 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id ci15so996864ejc.10; Thu, 10 Jun 2021 13:05:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LoitPLkETiydq84gXJtzggxZISPZQCmNnkixieE36b4=; b=GMguz6OyEOl/Uvt2/gL8nKqtpkTkh1nIQNqm8qA7P5UIKaJC5V5+SrGOPGdBHBYlWH rkYeFNN535MdA0sZ7TXn/8uemgSdLsbwlgvr1hwmayUXCJg18FKPgK2RRfi76/QZg33r eDCNuwQwQIEhIW8/y09/AzcW+VQAD8MFvxY8LPDAD3aFvF0C3OLPLmpQ3baMGCikg1d/ Z7Q60VNCCvZcdpE0E2gjgAsg+NAIdemfUvsNHoX52lMW0dCqpwfCBJFJAQE48YCFpTIb /aUIWm9X77xWUclbwV9xYclqedLyw4fPV6U3mACAtYPbaIy44aAbAVoRhgwjWgpHQo2x WKTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LoitPLkETiydq84gXJtzggxZISPZQCmNnkixieE36b4=; b=QuuFQykj+hTx2y838Yb5rtQhj80H+8ptJzqCkGBTC+FjaxsS+BqDGopXPMzeDN+UIR L5jAn+MEcT2nf8m/wUhim2o1uGo6BzgzPuSLUiXE1CMBLduzaYwoixuxlsok93qmA74P GjfcaFWmbQD35F7jQ0QYiwP1J6V4B2IRPhYh3+75kjigWOboeTJdoOkkvFuUKLjfrGRE bc5Bk7DCm5oN4oumXaNAuWWWpVY423RDgAxYfXsdw4E/dFJZBGSJ4QTjRGPQiZbHDwxu q/zO5YKSLFq/4qyoa3fWFckj38CB2UVhMcMYVt+kNC5CjIyWszamH+2EPaf1tJ04AZAg X5Nw== X-Gm-Message-State: AOAM530ThWwfdgpY2i9aVw+NbnoksJS70QxMFCARI61q4lRjDojrVwI1 pzH+c0H8x+jd/poTi3aFaNQ= X-Google-Smtp-Source: ABdhPJzJZ5JL4OUjg2j4Qk7l1gXhY1gqG//oQ8RpBSTrpixpPVGiqOi7opwqKgap95/c0/YT+6u91w== X-Received: by 2002:a17:906:5293:: with SMTP id c19mr268818ejm.245.1623355530546; Thu, 10 Jun 2021 13:05:30 -0700 (PDT) Received: from localhost.localdomain ([188.24.178.25]) by smtp.gmail.com with ESMTPSA id du7sm1800978edb.1.2021.06.10.13.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 13:05:30 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?Andreas?= =?utf-8?q?_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl S500 SoC Date: Thu, 10 Jun 2021 23:05:21 +0300 Message-Id: <4714d05982b19ac5fec2ed74f54be42d8238e392.1623354574.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Use correct divider registers for the Actions Semi Owl S500 SoC's UART clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - None Changes in v2: - Added Reviewed-by from Mani drivers/clk/actions/owl-s500.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 61bb224f6330..75b7186185b0 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -305,7 +305,7 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, @@ -317,31 +317,31 @@ static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART2CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART3CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART4CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART5CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART6CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p, From patchwork Thu Jun 10 20:05:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 12313865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6360C48BDF for ; Thu, 10 Jun 2021 20:06:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF938613FF for ; Thu, 10 Jun 2021 20:06:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230230AbhFJUIm (ORCPT ); Thu, 10 Jun 2021 16:08:42 -0400 Received: from mail-ed1-f46.google.com ([209.85.208.46]:43878 "EHLO mail-ed1-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230035AbhFJUIm (ORCPT ); Thu, 10 Jun 2021 16:08:42 -0400 Received: by mail-ed1-f46.google.com with SMTP id s6so34480878edu.10; Thu, 10 Jun 2021 13:06:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yec5z1rTz/gbfswMoHozIs3lpOfgznp00BzpVVk/Y+g=; b=NOuXijbMtdHHPd9iVu7KVaqKOLJiCO6mDkLyrAfA8TCBEgbaNfOZSGejLdDs1wzAlu 3grHvfoY1U2GHv23+pdNMdpFQ/2UWGtam+AwbP/Ss2BkbD12kZlc49W3LRrWBjkWD2Zh zKyPwuA4UD7FL7RJvdIZ5jwk++z6gWCgiNsOvnfiRJzj+dSYOkIlnx/YB1F6G+pNu1kk OnzVNL4lDTTM05/aWhmItgYIp5TyT0iXLmRKSryvTxd9rr1a+HJvQa4vbDDDehMaotMT qcsdRITcR49C+Bv5Ig44Rzib47bLAM2dadY1vkLAZzeShDiItV89QZMuZkPgt7nEAHil z7jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yec5z1rTz/gbfswMoHozIs3lpOfgznp00BzpVVk/Y+g=; b=Y1QTbiOnXNPd/XE9J9DCtlv7hhLzKBZ8CHEA5U6tNVxIsaNO0tDSSRJk7zEFJRAwcm v1avkRplsHN4Inip7BWZ0zlQ2RreQFFm5qc8+DmaeQMfTUW1AOw0L1JehAMk+TQ9oSlt aIjQnrdBRRibPpuyLieE5OWAB2WCgPh2UJTRCiHb+7HhExbm6dnAow4yEPMmeDFE5y2z ROLbdjZzwRauvNe2LJJQWtX6N9B8GmPz8IwCzYSAkKXAzS3IrZpkJQelBHqihRLgf2nm q+CN1/BwqeNq6TF/2VQBd1zvIwtMqvAJGXk7LIHS6zBcT1jQpGPqLUeD/VKU60xnqNuZ umTw== X-Gm-Message-State: AOAM5334GBJ/9pOBV9cJ3x+305UTJtlvWbKm5bMJcY1msIZy4fqSWeUy /3FfwNN6e5kT7TGY1qVvNlU= X-Google-Smtp-Source: ABdhPJw8ysHlGGhrLeKg1ByZDwKEQ4Hrf+NERoFbfhuIwwdHbUN7ir+SmisAX+3iBZdTEAx9aU5IhA== X-Received: by 2002:aa7:c753:: with SMTP id c19mr194068eds.33.1623355531760; Thu, 10 Jun 2021 13:05:31 -0700 (PDT) Received: from localhost.localdomain ([188.24.178.25]) by smtp.gmail.com with ESMTPSA id du7sm1800978edb.1.2021.06.10.13.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 13:05:31 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?Andreas?= =?utf-8?q?_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/6] clk: actions: Fix SD clocks factor table on Owl S500 SoC Date: Thu, 10 Jun 2021 23:05:22 +0300 Message-Id: <196c948d708a22b8198c95f064a0f6b6820f9980.1623354574.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Drop the unsupported entries in the factor table used for the SD[0-2] clocks definitions on the Actions Semi Owl S500 SoC. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by tag from Mani Changes in v2: - Re-added entry "{ 24, 1, 25 }" to sd_factor_table, according to the datasheet (V1.8+), this is a valid divider drivers/clk/actions/owl-s500.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 75b7186185b0..42abdf964044 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -127,8 +127,7 @@ static struct clk_factor_table sd_factor_table[] = { { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 }, { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 }, { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 }, - { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 }, - { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 }, + { 24, 1, 25 }, /* bit8: /128 */ { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 }, @@ -137,8 +136,7 @@ static struct clk_factor_table sd_factor_table[] = { { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 }, { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 }, { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 }, - { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 }, - { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 }, + { 280, 1, 25 * 128 }, { 0, 0, 0 }, }; From patchwork Thu Jun 10 20:05:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 12313867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC464C48BD1 for ; Thu, 10 Jun 2021 20:06:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A6DFF61362 for ; Thu, 10 Jun 2021 20:06:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231145AbhFJUIn (ORCPT ); Thu, 10 Jun 2021 16:08:43 -0400 Received: from mail-ed1-f50.google.com ([209.85.208.50]:33503 "EHLO mail-ed1-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230245AbhFJUIm (ORCPT ); Thu, 10 Jun 2021 16:08:42 -0400 Received: by mail-ed1-f50.google.com with SMTP id f5so29499317eds.0; Thu, 10 Jun 2021 13:06:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5s5zP/EpVmQlg+h4gF15kZmB35/4iHQZ0hsmxTTSidA=; b=ZcDHeQCfU3xuLBg/ff8ZVxP3QEJh44QstkFQbqEO/WkAG9OEcz+EccVNsfb/omDjlZ 1Pg/8cPtATJuwnnCuHpWzVh0Y1JAuIUKnq5dc/jnU9+D2s3vTvPN8hF7u5IwuMm5bpMJ OjyF6k9lfYju95dcoQEjmVm85BZErOzPKXdpis4GSXiHV9mrDXw3yMRieXweKHiZJohF c3YkThq/srKQUoNDRqy0kgXjV604wYYaSWjsDLdUyRHEBLL9wSwTc9Gr1PtRhr1FFqGR 2F2OClDV5kTTMrYeUkn7/iwgyyHeQSMyC7JOy9tlOief5d5zSS8VPbnQzdlhsUnz8YLp zvoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5s5zP/EpVmQlg+h4gF15kZmB35/4iHQZ0hsmxTTSidA=; b=W7e7Y2EWCxD2GTPrfSryYDdzAX/xvWhMnkjzjtUhgXWxdvlTR/jHsV4EO+flxnXS6D rTMeSF/DuFENTHXOJkqPUqICQ391PZdelEOyPLUMLwV1J0LnYh6YnAHP0nQwjG2+wFMr plQarJN3fOzG0NwCkH2Y4IhzjXtQRmO2xB7dw5pRhOOyiqEBrUQFRcYgPOsOv2RjYaZx r5Kog1vMa62Ygaw7vEdA5M5Zec0cVSRXnj67UArZgyrS+sN5ZlkTVAw9nu2BbxkuVM0v UxTnE10SzJUQIDSuZ/INfSjcD7tBb1S17Cz88eyBJFnkpL6eNFQjUUYiD5BEbtFnvBf2 ig2w== X-Gm-Message-State: AOAM531GVih/I2q3QkJce5kocaB7hsu3P1K2Mf3iqKPFIMkekO8pKqnd AQCJ3WPW5sb2yVjBxPCeInw= X-Google-Smtp-Source: ABdhPJyivZXimEWadRgV/aYVj01+OaW49bNWMM4ljD6CJm/rvZyowhXl8auyIg1AF7TKHcpl4hSceA== X-Received: by 2002:a50:8dc6:: with SMTP id s6mr242695edh.50.1623355533111; Thu, 10 Jun 2021 13:05:33 -0700 (PDT) Received: from localhost.localdomain ([188.24.178.25]) by smtp.gmail.com with ESMTPSA id du7sm1800978edb.1.2021.06.10.13.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 13:05:32 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?Andreas?= =?utf-8?q?_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 3/6] clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC Date: Thu, 10 Jun 2021 23:05:23 +0300 Message-Id: X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The following clocks of the Actions Semi Owl S500 SoC have been defined to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE, VDE, BISP, SENSOR[0-1] There are several issues involved in this approach: * 'bisp_factor_table[]' describes the configuration of a regular 8-rates divider, so its usage is redundant. Additionally, judging by the BISP clock context, it is incomplete since it maps only 8 out of 12 possible entries. * The clocks mentioned above are not identical in terms of the available rates, therefore cannot rely on the same factor table. Specifically, BISP and SENSOR* are standard 12-rate dividers so their configuration should rely on a proper clock div table, while VCE and VDE require a factor table that is a actually a subset of the one needed for DE[1-2] clocks. Let's fix this by implementing the following: * Add new factor tables 'de_factor_table' and 'hde_factor_table' to properly handle DE[1-2], VCE and VDE clocks. * Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1] clocks converted to OWL_COMP_DIV. * Drop the now unused 'bisp_factor_table[]'. Additionally, drop the CLK_IGNORE_UNUSED flag for SENSOR[0-1] since there is no reason to always keep ON those clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by tag from Mani Changes in v2: - Re-added OWL_GATE_HW to SENSOR[0-1], according to the datasheet they are gated, even though the vendor implementation states the opposite drivers/clk/actions/owl-s500.c | 44 ++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 42abdf964044..42d6899755e6 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -140,9 +140,16 @@ static struct clk_factor_table sd_factor_table[] = { { 0, 0, 0 }, }; -static struct clk_factor_table bisp_factor_table[] = { - { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 }, - { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 }, +static struct clk_factor_table de_factor_table[] = { + { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, + { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, + { 8, 1, 12 }, + { 0, 0, 0 }, +}; + +static struct clk_factor_table hde_factor_table[] = { + { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, + { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, { 0, 0, 0 }, }; @@ -156,6 +163,13 @@ static struct clk_div_table rmii_ref_div_table[] = { { 0, 0 }, }; +static struct clk_div_table std12rate_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, + { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, + { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, + { 0, 0 }, +}; + static struct clk_div_table i2s_div_table[] = { { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 }, @@ -191,39 +205,39 @@ static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNE /* factor clocks */ static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0); -static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0); -static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0); +static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0); +static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); /* composite clocks */ static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VCECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), - OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table), + OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table), 0); static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VDECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0), - OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table), + OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table), 0); -static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p, +static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p, OWL_MUX_HW(CMU_BISPCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), - OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table), + OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table), 0); -static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, +static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), - OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table), - CLK_IGNORE_UNUSED); + OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table), + 0); -static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, +static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), - OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table), - CLK_IGNORE_UNUSED); + OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table), + 0); static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD0CLK, 9, 1), From patchwork Thu Jun 10 20:05:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 12313855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 171FFC48BD1 for ; Thu, 10 Jun 2021 20:05:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E93E56136D for ; Thu, 10 Jun 2021 20:05:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230035AbhFJUHd (ORCPT ); Thu, 10 Jun 2021 16:07:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229941AbhFJUHc (ORCPT ); Thu, 10 Jun 2021 16:07:32 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2167C0617A6; Thu, 10 Jun 2021 13:05:35 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id g8so1060882ejx.1; Thu, 10 Jun 2021 13:05:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Y+aHwlcnZkPSrYqvChf+Kbr1B3VKSxdsI8c9mE1nNE=; b=EpyOQUDfYGJ9ZVtaFp7XUoBlrRBvURH5jncEZ57YlJsClw9ldMcGZFvfOnRbC+2f9m qY+Iu8LMgMpIsFAzJO+gmUgfVklnP0GVVbpUXRHqtN0P447fvA6TeZ7BT5nMjjjTsYq0 dDzpFUvNSOzuy9JQfogqRdX3Sp08hQYnoiliZvZTZWydh12xojayfA0j3vwbWYzdVXOc iAfMR3Br9rJioyHGWSS7Hmin/PmM4jNHaCrGIudThyxTvqsJ1yTsdRGphzVB9lMVPqzM ZIU73VO6/rLAef+j8Lt2c/g8PHpo6HA5c4MKdaQ7VCdM8+opobx7H66Fs+QEN++q0jFs ORBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2Y+aHwlcnZkPSrYqvChf+Kbr1B3VKSxdsI8c9mE1nNE=; b=dzZ+JVBhGz4gk74+NyrQxZHOschsx1dnM2elvwPB4BgPwWq+evBT5lmpdSYFmkko5A y0YEfXZYj5YsH6vFPUdP8fS6lyrRrlAyRwjMEIC7RQo0ZKoBADr45XzOv//cJhorVrEr GxhNNZT0v0MNiC++ClbiVAZSYVQvEMKkL/BDfzFK4lAxKnP6zwEZP2FMMESI41V8Qhlg cK96fnB/HRG8TJxiqnpX7lHa48tVqygTKpFvKyEVWzEyxOpCxRo7BGPaoHQ3rdPautrk uuYg45ZDDNJ2AMJdcX6NT2STwt+ReRbcse5ZWGSXYNoWnWHy7Ti5afbt3K06jJOwT7hH xuzg== X-Gm-Message-State: AOAM531MMkFzvQskxbRU4aLiSSM433s6PeMhDnyD2EvtsmaaBUQ9nrMW 4EtqBm6reJtVzluAhba8ZxSj68pFPes= X-Google-Smtp-Source: ABdhPJw3sTaDY/SYhXrGVqheFvg5MBLkOnqjeQILmRnwcnOU5LKV2tr5xeLDZ+6K6Z9SR2w082SniA== X-Received: by 2002:a17:907:7b9e:: with SMTP id ne30mr275681ejc.389.1623355534392; Thu, 10 Jun 2021 13:05:34 -0700 (PDT) Received: from localhost.localdomain ([188.24.178.25]) by smtp.gmail.com with ESMTPSA id du7sm1800978edb.1.2021.06.10.13.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 13:05:33 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?Andreas?= =?utf-8?q?_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC Date: Thu, 10 Jun 2021 23:05:24 +0300 Message-Id: <21c1abd19a7089b65a34852ac6513961be88cbe1.1623354574.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org There are a few issues with the setup of the Actions Semi Owl S500 SoC's clock chain involving AHPPREDIV, H and AHB clocks: * AHBPREDIV clock is defined as a muxer only, although it also acts as a divider. * H clock is using a wrong divider register offset * AHB is defined as a multi-rate factor clock, but it is actually just a fixed pass clock. Let's provide the following fixes: * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition. * Use the correct register shift value in the OWL_DIVIDER definition for H clock * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an ungated OWL_COMP_FIXED_FACTOR definition. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Fixed the swapped flags between "ahbprediv_clk" and "ahb_clk" as noticed by Mani Changes in v2: - Reverted the addition of the clock div table for H clock to support the '1' divider (according to the datasheet), even though the vendor implementation marks it as reserved drivers/clk/actions/owl-s500.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 42d6899755e6..cbeb51c804eb 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -153,11 +153,6 @@ static struct clk_factor_table hde_factor_table[] = { { 0, 0, 0 }, }; -static struct clk_factor_table ahb_factor_table[] = { - { 1, 1, 2 }, { 2, 1, 3 }, - { 0, 0, 0 }, -}; - static struct clk_div_table rmii_ref_div_table[] = { { 0, 4 }, { 1, 10 }, { 0, 0 }, @@ -186,7 +181,6 @@ static struct clk_div_table nand_div_table[] = { /* mux clock */ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); -static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT); /* gate clocks */ static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0); @@ -199,16 +193,25 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0); static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); /* divider clocks */ -static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0); +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0); static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); /* factor clocks */ -static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0); static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0); static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); /* composite clocks */ +static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, + OWL_MUX_HW(CMU_BUSCLK1, 8, 3), + { 0 }, + OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL), + CLK_SET_RATE_PARENT); + +static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk", + { 0 }, + 1, 1, 0); + static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VCECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), From patchwork Thu Jun 10 20:05:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 12313863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5B1CC48BD1 for ; Thu, 10 Jun 2021 20:05:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8BBC66141F for ; Thu, 10 Jun 2021 20:05:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230492AbhFJUHs (ORCPT ); Thu, 10 Jun 2021 16:07:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230332AbhFJUHr (ORCPT ); Thu, 10 Jun 2021 16:07:47 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 107F0C0617A6; Thu, 10 Jun 2021 13:05:37 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id g18so32505359edq.8; Thu, 10 Jun 2021 13:05:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vqklbb1b+FGK11o6PjF8j0OzGaPb5SlSdCs8dzovjLM=; b=E1MHE601YYllcozgVxcLv4bUNvFScaukRBWFue1xnQPgNIPmQvXr3+O8abm8FcVoim aOfAoJr1lACcSX4FGTfNT2Z4rMLyTz4TP4NzvkUcc1uJjmDW5IXsPNHC9GAgwsslVkdQ mUft+STrRO/nrdmDTfwAZU0j0zHwd6mP4OXgGveX6gBzDUkHFBQp9Pxn06NbNd0ml/Jj jf8yQ6V2/bqkBU1PMZ/OoxJ/5uzR2+x3mfDuBBTSXL0r/77jFOu/Mqmo5aWWF1p4oC0U XDPDF6luM+S7JWtDBSqEYw+HdCp5h0Renkzq3/Hd/2vcS0InbwSDGvCXd9uo3y6K+1pR aUsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vqklbb1b+FGK11o6PjF8j0OzGaPb5SlSdCs8dzovjLM=; b=Iw7jbYqnUqSNpAn7m6GOFit5v0+Uqi+qoQtnD/fWsw0UPBqHCDlTphCRu61V0nLQbW cSX8MdSLsg2iRaMUjOC15pWABE64Tgz6xiFh4ATmwyeo3jb7U3tfUPO8GjONBrK/Mvq5 rG4eiYJvJ9lDXZFXqqDpYOw/U5QX+f0ZoocHRx+g+VI3zrZ9iibhciGQUqLOKXQkSMtj VT64jCyrUEI1ThHu7UvQ9xQ78FaYpvrjYb8HEx3KiRIFK5xZDWHoqTwP2VwlhUNqtZzx nNfMdd2zF+GkNGPyDlmbbc6M0mBLK4h2SpJ0n1i26HFXaeBiL/kVRjVaYOhRir0kULYL lHUg== X-Gm-Message-State: AOAM533wrGAn6+hVjf5fGqCtB6m+s4VocAz2Eb6l/Wc6XkATETonuG9k Mullb7PI9bfcfkRONVWc7pg= X-Google-Smtp-Source: ABdhPJz4OPleI5+1+Gqt8G9O/F3TBu4ayZ5zXX3Jd24SXMOOajxQzgLiU8bmAmrgyx3ElmbomcgRhg== X-Received: by 2002:a05:6402:1111:: with SMTP id u17mr189797edv.87.1623355535695; Thu, 10 Jun 2021 13:05:35 -0700 (PDT) Received: from localhost.localdomain ([188.24.178.25]) by smtp.gmail.com with ESMTPSA id du7sm1800978edb.1.2021.06.10.13.05.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 13:05:35 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?Andreas?= =?utf-8?q?_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v3 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC Date: Thu, 10 Jun 2021 23:05:25 +0300 Message-Id: <1d0902cf073f76a1a602410061481ccb3fc36a72.1623354574.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the missing NIC and ETHERNET clock bindings constants for Actions Semi Owl S500 SoC. Signed-off-by: Cristian Ciocaltea Acked-by: Rob Herring Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by tag from Mani Changes in v2: - Added Acked-by tag from Rob include/dt-bindings/clock/actions,s500-cmu.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h index a250a52a6192..a237eb26accb 100644 --- a/include/dt-bindings/clock/actions,s500-cmu.h +++ b/include/dt-bindings/clock/actions,s500-cmu.h @@ -74,10 +74,12 @@ #define CLK_RMII_REF 54 #define CLK_GPIO 55 -/* system clock (part 2) */ +/* additional clocks */ #define CLK_APB 56 #define CLK_DMAC 57 +#define CLK_NIC 58 +#define CLK_ETHERNET 59 -#define CLK_NR_CLKS (CLK_DMAC + 1) +#define CLK_NR_CLKS (CLK_ETHERNET + 1) #endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */ From patchwork Thu Jun 10 20:05:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 12313857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64C2EC48BD1 for ; Thu, 10 Jun 2021 20:05:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 49A7261419 for ; Thu, 10 Jun 2021 20:05:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230280AbhFJUHf (ORCPT ); Thu, 10 Jun 2021 16:07:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229941AbhFJUHf (ORCPT ); Thu, 10 Jun 2021 16:07:35 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52D25C0617A8; Thu, 10 Jun 2021 13:05:38 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id u24so34482862edy.11; Thu, 10 Jun 2021 13:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0gUA8fCofTJN4dSFDRWQ0LtpsjbZVq0HGtPwb2y+ZNk=; b=pjUX2sX1hCuxJMXZzLkXI2KXrkiO2we8D5JQvdmkNjLXWO4ewuu6ZxBZ6hxK9yWmca KpMPeB7EI4jD9MHCP7kUDJfbFJEVmImX47nuM30re0gUzQpQkDoqv4xBqkWjQLeaF79j /rJzrECl78m6wl/oAubtrxGtkwZrz9fQ7AC/sgDb3O4DY8j9NCwXlwty8DBaTXV/KC9R AhdOkHfpBD3grkwdLrzZD32012rSppYW6PV5Kjn9EI7gKSzHQ8PohorTqdEdPWddqVoZ /sIrkiPy7Yc5aP8Cb3l+l/aAj5/Ac3PqLvDmAz+u/tBlUVLD2gxGyOAve9NfS3N4TW5K jxBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0gUA8fCofTJN4dSFDRWQ0LtpsjbZVq0HGtPwb2y+ZNk=; b=UemONWq2rpFBfGNGSIEcy9RAIgodYFVumo7KhbnD7LIpu/sO3xHBcC1PiykJxpI81G 7fRBIw8I878Hl6mVLhD/8DMp3wS65Lx6O5BChF0tJHjp9P+YsB0NjPuKS5c2t+ZzdTW7 LzDuEwmS77FuOX6PoNLzTiKoMun3PcM6Gyr2eKgTQYeC/GdqFnqW0RzE2BRHOj5j9jn1 6WYym1VTrGl2jtG+ZFG9gVD5CxnskZaM6f3NmWtNs6AJHukABmZF/ZLwbki+Ii8qltMd CIFxDXK4kayo45F/Csa944rIefD+GE1np0xTYWu/q++oXtayQ9TmhuksqJB0+Xn7yI9W 0rjg== X-Gm-Message-State: AOAM5300OYxAS2WO9HX2Og7mO45n1jgWYLDi99Eue7CKMDrqm0r8iJzj X8lYeIG4Oopd+N1MsxpSvGQ= X-Google-Smtp-Source: ABdhPJwzqCXrn8iL2XWZ/0drEfa0hsMCgS3V0Y3oGOF7Zv/CdbCHIq7Drgnn6v3LAFnvr7ohgr2e8A== X-Received: by 2002:a05:6402:cb4:: with SMTP id cn20mr195651edb.334.1623355536938; Thu, 10 Jun 2021 13:05:36 -0700 (PDT) Received: from localhost.localdomain ([188.24.178.25]) by smtp.gmail.com with ESMTPSA id du7sm1800978edb.1.2021.06.10.13.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 13:05:36 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?Andreas?= =?utf-8?q?_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 6/6] clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC Date: Thu, 10 Jun 2021 23:05:26 +0300 Message-Id: X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add support for the missing NIC and ETHERNET clocks in the Actions Semi Owl S500 SoC clock driver. Additionally, change APB clock parent from AHB to the newly added NIC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v3: - Added Reviewed-by tag from Mani Changes in v2: - Reordered "nic_clk_mux_p" after "ahbprediv_clk_mux_p" to follow the reg field ordering drivers/clk/actions/owl-s500.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index cbeb51c804eb..57d06e183dff 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -113,6 +113,7 @@ static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" }; static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" }; static const char * const pwm_clk_mux_p[] = { "losc", "hosc" }; static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; +static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" }; static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" }; @@ -194,7 +195,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); /* divider clocks */ static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0); -static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); +static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); /* factor clocks */ @@ -202,6 +203,12 @@ static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); /* composite clocks */ +static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p, + OWL_MUX_HW(CMU_BUSCLK1, 4, 3), + { 0 }, + OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL), + 0); + static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, OWL_MUX_HW(CMU_BUSCLK1, 8, 3), { 0 }, @@ -317,6 +324,10 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), 1, 5, 0); +static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk", + OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0), + 1, 20, 0); + static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), @@ -451,6 +462,8 @@ static struct owl_clk_common *s500_clks[] = { &apb_clk.common, &dmac_clk.common, &gpio_clk.common, + &nic_clk.common, + ðernet_clk.common, }; static struct clk_hw_onecell_data s500_hw_clks = { @@ -510,6 +523,8 @@ static struct clk_hw_onecell_data s500_hw_clks = { [CLK_APB] = &apb_clk.common.hw, [CLK_DMAC] = &dmac_clk.common.hw, [CLK_GPIO] = &gpio_clk.common.hw, + [CLK_NIC] = &nic_clk.common.hw, + [CLK_ETHERNET] = ðernet_clk.common.hw, }, .num = CLK_NR_CLKS, };