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Fri, 11 Jun 2021 19:59:45 -0700 Received: from MTKMBS01N1.mediatek.inc (172.21.101.68) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Jun 2021 19:59:43 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 12 Jun 2021 10:59:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 12 Jun 2021 10:59:29 +0800 From: Deren Wu To: Felix Fietkau , Lorenzo Bianconi CC: Sean Wang , Soul Huang , YN Chen , Leon Yen , "Eric-SY Chang" , Deren Wu , KM Lin , Robin Chiu , CH Yeh , Posh Sun , Eric Liang , Stella Chang , , , linux-wireless , linux-mediatek , Deren Wu Subject: [PATCH] mt76: mt7921: introduce PCIe ASPM support (L0s/L1/L1ss) Date: Sat, 12 Jun 2021 10:59:26 +0800 Message-ID: X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210611_195949_827185_76E9BA7E X-CRM114-Status: GOOD ( 10.86 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Deren Wu for better power consumption, default enable PCIe ASPM Tested-by: Leon Yen Signed-off-by: Deren Wu --- .../net/wireless/mediatek/mt76/mt7921/pci.c | 68 ++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c index 13263f50dc00..5358836bb00e 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c +++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c @@ -88,6 +88,72 @@ static void mt7921_irq_tasklet(unsigned long data) napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); } +static void mt7921_pci_config_L1(struct pci_dev *pdev, u8 enable) +{ + u32 reg32; + int pos; + + if (!pdev) + return; + + /* capability check */ + pos = pdev->pcie_cap; + pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); + if (!(reg32 & PCI_EXP_LNKCAP_ASPMS)) { + dev_info(&pdev->dev, "ASPM L1: Invalid cap 0x%X\n", reg32); + return; + } + + /* set config */ + pci_read_config_dword(pdev, pos + PCI_EXP_LNKCTL, ®32); + if (enable) + reg32 |= (PCI_EXP_LNKCTL_ASPMC); + else + reg32 &= ~(PCI_EXP_LNKCTL_ASPMC); + dev_dbg(&pdev->dev, "%s ASPM L1\n", (enable) ? "enable" : "disable"); + + pci_write_config_dword(pdev, pos + PCI_EXP_LNKCTL, reg32); +} + +static void mt7921_pci_config_L1ss(struct pci_dev *pdev, u8 enable) +{ +#define PCIE_L1SS_CAP_CHK \ + (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2) +#define PCIE_L1SS_CTL_CHK \ + (PCI_L1SS_CTL1_ASPM_L1_1 | PCI_L1SS_CTL1_ASPM_L1_2) + + int pos; + u32 reg32; + + if (!pdev) + return; + + /* capability check */ + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); + pci_read_config_dword(pdev, pos + PCI_L1SS_CAP, ®32); + if (!(reg32 & (PCIE_L1SS_CAP_CHK))) { + dev_info(&pdev->dev, "ASPM L1SS: Invalid cap 0x%X\n", reg32); + return; + } + + /* set config */ + pci_read_config_dword(pdev, pos + PCI_L1SS_CTL1, ®32); + if (enable) + reg32 |= (PCIE_L1SS_CTL_CHK); + else + reg32 &= ~(PCIE_L1SS_CTL_CHK); + + dev_dbg(&pdev->dev, "%s ASPM L1SS\n", (enable) ? "enable" : "disable"); + + pci_write_config_dword(pdev, pos + PCI_L1SS_CTL1, reg32); +} + +void mt7921_pci_enable_aspm(struct pci_dev *pdev) +{ + mt7921_pci_config_L1ss(pdev, true); + mt7921_pci_config_L1(pdev, true); +} + static int mt7921_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -131,7 +197,7 @@ static int mt7921_pci_probe(struct pci_dev *pdev, if (ret) goto err_free_pci_vec; - mt76_pci_disable_aspm(pdev); + mt7921_pci_enable_aspm(pdev); mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7921_ops, &drv_ops);