From patchwork Sun Jun 13 15:56:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12317769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC803C48BDF for ; Sun, 13 Jun 2021 15:56:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6EE9961019 for ; Sun, 13 Jun 2021 15:56:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231913AbhFMP63 (ORCPT ); Sun, 13 Jun 2021 11:58:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231844AbhFMP63 (ORCPT ); Sun, 13 Jun 2021 11:58:29 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 175E3C061574 for ; Sun, 13 Jun 2021 08:56:28 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id 3-20020a05600c0243b029019f2f9b2b8aso11342096wmj.2 for ; Sun, 13 Jun 2021 08:56:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WcWXY1H/tcjwWXrjK7sGg/H6izhQyfGF6Ma3AVimpBU=; b=HEbM5nM8IHDEzMdD3sztOA9THxULFR4v8Z3E2Fvii9hlMDTtptfpVaiPLdLYnSvk+0 NTVwVp7GOcNpM8gtJafnfqtSo2gRkzUbCOCXnt1Hyh7joulJKdVs0TBy0NDzVRha3+oH ytSQ0/gvM1ltmbnXirtLVlCkTqxYlHK58VDN79RPpE1rtCeRE2nNBmIFp89xpMw4k2Ej xEeeSONozXVj/bm8pCu0jqEASSM1HsSG5cvz+jmpKiY59koi1j//UB+fE3a3OsUdNQhS DjXE2hwHJFaqvad1GEFWivXu2sIRYVfTq1zj/zfTDUZVS+fixR2x09HT4qJkZDkA3izK 2OYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WcWXY1H/tcjwWXrjK7sGg/H6izhQyfGF6Ma3AVimpBU=; b=P1Y1+HuVBN6IHrUyHmDtU4GpPNT6qVMoM6UmP4WTbuVjZ6p03lsBFIFYctXxzy2bsG PNr7p8/nYZM6pPag/a7arepNmdVhlcBc5fnR4ZuXFqyN8CohMvacDNm9tcPSNixca2ZP yI/sQvQS5xlg+POO5afWH67dLlB/F70wqHXoFHYHZJV60LIV1dV7B5RHukKqbli240Lo Z1w3KgtwaESldTdHADRbA/Vz4hLyUfcXsv3xgyj05+qrm2VlYtl5PpuGk3fhfVTt9M9b SkqOzjVG9wkrM6yt/bQE/OTJsVd7AJ42jIe3JowXsq9Dhjws7wi4CM25sy8a+oI7FLw8 ZL3w== X-Gm-Message-State: AOAM532L32U+SSCM+v/Dw84tcbDmUyV02RbWViR1kSqQiJEpfgWVRvLA ZmggSAgg7tk+yXH60xrd4GU= X-Google-Smtp-Source: ABdhPJzC7esJXQAJvVqwSLn+AHewwNmrMQCmETANKdSzUN9Gdtf2/VJaUyahh1RjHJVC4574vp7ZRw== X-Received: by 2002:a1c:453:: with SMTP id 80mr12034421wme.171.1623599786485; Sun, 13 Jun 2021 08:56:26 -0700 (PDT) Received: from localhost.localdomain (98.red-81-38-58.dynamicip.rima-tde.net. [81.38.58.98]) by smtp.gmail.com with ESMTPSA id g17sm17539746wrh.72.2021.06.13.08.56.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jun 2021 08:56:26 -0700 (PDT) From: Sergio Paracuellos To: linux-staging@lists.linux.dev Cc: gregkh@linuxfoundation.org, neil@brown.name, linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, ilya.lipnitskiy@gmail.com, john@phrozen.org Subject: [PATCH 1/3] MIPS: ralink: Define PCI_IOBASE Date: Sun, 13 Jun 2021 17:56:21 +0200 Message-Id: <20210613155623.17233-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210613155623.17233-1-sergio.paracuellos@gmail.com> References: <20210613155623.17233-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org PCI_IOBASE is used to create VM maps for PCI I/O ports, it is required by generic PCI drivers to make memory mapped I/O range work. Hence define it for ralink architectures to be able to avoid parsing manually IO ranges in PCI generic driver code. Function 'plat_mem_setup' for ralink is using 'set_io_port_base' call using '0xa0000000' as address, so use the same address in the definition to align things. Signed-off-by: Sergio Paracuellos --- arch/mips/include/asm/mach-ralink/spaces.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/mips/include/asm/mach-ralink/spaces.h diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h new file mode 100644 index 000000000000..ec58d4a9ed05 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/spaces.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_RALINK_SPACES_H_ +#define __ASM_MACH_RALINK_SPACES_H_ + +#define PCI_IOBASE _AC(0xa0000000, UL) +#define PCI_IOSIZE SZ_16M +#define IO_SPACE_LIMIT (PCI_IOSIZE - 1) + +#include +#endif From patchwork Sun Jun 13 15:56:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12317771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E2B5C48BDF for ; Sun, 13 Jun 2021 15:56:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7990361245 for ; Sun, 13 Jun 2021 15:56:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231922AbhFMP6o (ORCPT ); Sun, 13 Jun 2021 11:58:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231844AbhFMP6n (ORCPT ); Sun, 13 Jun 2021 11:58:43 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C68B5C061574 for ; Sun, 13 Jun 2021 08:56:28 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id s70-20020a1ca9490000b02901a589651424so8303326wme.0 for ; Sun, 13 Jun 2021 08:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U+7KMa4x9I3RPmCk8B+EWnxSMOxLFlMAChoVtPf3+Qw=; b=sRm83kHP9pj1mh8p6uprSQKuZQ6IIpJJsIzwqx/4odMzL6Wu/nmAdp3Wo0rDx0BoS1 JHba3I5flCsPV8zuUgmX7K2JLppXNEA4tUYKwk22HuaHtMjDEIz0Vk1r/c7UVSCfsyaR 7kwV5kJk9EEbcTWU321+6uORYPzY/D9/rOHZSu5JU1YeXs3m8hIAiJP0TmtLWRPjX+51 im/kshnLGPKDHrlSS6fADgYx2UpmfN8pm9nP4GR6CD9dnDGbjHXjYnqsRCBWIQMPkOsM DUoFyQHWWj1KYkeiva2qpPztAMaqD193akrzzL4nJCTieV03+mSgs8zhBdZR5bxxUA9V xV7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U+7KMa4x9I3RPmCk8B+EWnxSMOxLFlMAChoVtPf3+Qw=; b=iBoFSr8SFg1KVYu4ak+STLn4OjOpigGtnsSmzGculDxc4s6vEiMaUmVHGH+1qwpwWT ICtcHTJtMJUXMzcOLPpKhkJlJMB1AxjqYVOVe7hwMvWXUOxaAo+9OJnTHSOLsWFs1e+V D2UQRTrpJ7E4nRHUTngx8LDwgCBd89Nu5Xo8opmLi82lT1w78XuW3P1j4Gc9tQuPAE9B R3calr1JQRuuE9E8oxvXQEkF0BtwEE6INjroAW3fEfGFl71b4qBcqC9XzyMQJKLun0L3 5aT5BkWtes7e7DAmmnC3sY4EC1IySETO6DglccqKlYGd3FtFLFWJOZUhuyIO1qiptj8J s8gA== X-Gm-Message-State: AOAM531ym1bXA/aDQDgd37N1EEmg4S/ByQoK4IZ9yg8zg6lwYaZhAwFz FfS1kqzW71iBCTU7XGf++qo= X-Google-Smtp-Source: ABdhPJzQDoc9eMI4+h5ulG+lDOYp9zHS4rPC0Q1y6HneU/Rmfd5s6SYJsNeVGLIe5V3qB8L8sP6OAw== X-Received: by 2002:a05:600c:230b:: with SMTP id 11mr12292290wmo.81.1623599787334; Sun, 13 Jun 2021 08:56:27 -0700 (PDT) Received: from localhost.localdomain (98.red-81-38-58.dynamicip.rima-tde.net. [81.38.58.98]) by smtp.gmail.com with ESMTPSA id g17sm17539746wrh.72.2021.06.13.08.56.26 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jun 2021 08:56:27 -0700 (PDT) From: Sergio Paracuellos To: linux-staging@lists.linux.dev Cc: gregkh@linuxfoundation.org, neil@brown.name, linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, ilya.lipnitskiy@gmail.com, john@phrozen.org Subject: [PATCH 2/3] staging: mt7621-pci: remove 'mt7621_pci_parse_request_of_pci_ranges' Date: Sun, 13 Jun 2021 17:56:22 +0200 Message-Id: <20210613155623.17233-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210613155623.17233-1-sergio.paracuellos@gmail.com> References: <20210613155623.17233-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org After 'PCI_IOBASE' is defined for ralink, ranges are properly parsed using pci generic APIS and there is no need to parse anything manually. So function 'mt7621_pci_parse_request_of_pci_ranges' used for this can be enterely removed. Since we have to configure iocu memory regions and pci io windows resources must be retrieved accordly from 'bridge->windows' but there is no need to store anything as driver private data. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 100 +++++++----------------- 1 file changed, 27 insertions(+), 73 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index b0b5700cbfec..691030e1a5ed 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -86,10 +86,7 @@ struct mt7621_pcie_port { /** * struct mt7621_pcie - PCIe host information * @base: IO Mapped Register Base - * @io: IO resource - * @mem: pointer to non-prefetchable memory resource * @dev: Pointer to PCIe device - * @io_map_base: virtual memory base address for io * @ports: pointer to PCIe port information * @resets_inverted: depends on chip revision * reset lines are inverted. @@ -97,9 +94,6 @@ struct mt7621_pcie_port { struct mt7621_pcie { void __iomem *base; struct device *dev; - struct resource io; - struct resource *mem; - unsigned long io_map_base; struct list_head ports; bool resets_inverted; }; @@ -213,75 +207,33 @@ static inline void mt7621_control_deassert(struct mt7621_pcie_port *port) reset_control_assert(port->pcie_rst); } -static void setup_cm_memory_region(struct mt7621_pcie *pcie) +static int setup_cm_memory_region(struct pci_host_bridge *host) { - struct resource *mem_resource = pcie->mem; + struct mt7621_pcie *pcie = pci_host_bridge_priv(host); struct device *dev = pcie->dev; + struct resource_entry *entry; resource_size_t mask; + entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) { + dev_err(dev, "Cannot get memory resource\n"); + return -EINVAL; + } + if (mips_cps_numiocu(0)) { /* * FIXME: hardware doesn't accept mask values with 1s after * 0s (e.g. 0xffef), so it would be great to warn if that's * about to happen */ - mask = ~(mem_resource->end - mem_resource->start); + mask = ~(entry->res->end - entry->res->start); - write_gcr_reg1_base(mem_resource->start); + write_gcr_reg1_base(entry->res->start); write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n", (unsigned long long)read_gcr_reg1_base(), (unsigned long long)read_gcr_reg1_mask()); } -} - -static int mt7621_pci_parse_request_of_pci_ranges(struct pci_host_bridge *host) -{ - struct mt7621_pcie *pcie = pci_host_bridge_priv(host); - struct device *dev = pcie->dev; - struct device_node *node = dev->of_node; - struct of_pci_range_parser parser; - struct resource_entry *entry; - struct of_pci_range range; - LIST_HEAD(res); - - if (of_pci_range_parser_init(&parser, node)) { - dev_err(dev, "missing \"ranges\" property\n"); - return -EINVAL; - } - - /* - * IO_SPACE_LIMIT for MIPS is 0xffff but this platform uses IO at - * upper address 0x001e160000. of_pci_range_to_resource does not work - * well for MIPS platforms that don't define PCI_IOBASE, so set the IO - * resource manually instead. - */ - for_each_of_pci_range(&parser, &range) { - switch (range.flags & IORESOURCE_TYPE_BITS) { - case IORESOURCE_IO: - pcie->io_map_base = - (unsigned long)ioremap(range.cpu_addr, - range.size); - pcie->io.name = node->full_name; - pcie->io.flags = range.flags; - pcie->io.start = range.cpu_addr; - pcie->io.end = range.cpu_addr + range.size - 1; - pcie->io.parent = pcie->io.child = pcie->io.sibling = NULL; - set_io_port_base(pcie->io_map_base); - break; - } - } - - entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); - if (!entry) { - dev_err(dev, "Cannot get memory resource"); - return -EINVAL; - } - - pcie->mem = entry->res; - pci_add_resource(&res, &pcie->io); - pci_add_resource(&res, entry->res); - list_splice_init(&res, &host->windows); return 0; } @@ -510,15 +462,23 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) write_config(pcie, slot, PCIE_FTS_NUM, val); } -static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) +static int mt7621_pcie_enable_ports(struct pci_host_bridge *host) { + struct mt7621_pcie *pcie = pci_host_bridge_priv(host); struct device *dev = pcie->dev; struct mt7621_pcie_port *port; + struct resource_entry *entry; int err; + entry = resource_list_first_type(&host->windows, IORESOURCE_IO); + if (!entry) { + dev_err(dev, "Cannot get io resource\n"); + return -EINVAL; + } + /* Setup MEMWIN and IOWIN */ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); - pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE); + pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE); list_for_each_entry(port, &pcie->ports, list) { if (port->enabled) { @@ -581,25 +541,19 @@ static int mt7621_pci_probe(struct platform_device *pdev) return err; } - err = mt7621_pci_parse_request_of_pci_ranges(bridge); - if (err) { - dev_err(dev, "Error requesting pci resources from ranges"); - goto remove_resets; - } - - /* set resources limits */ - ioport_resource.start = pcie->io.start; - ioport_resource.end = pcie->io.end; - mt7621_pcie_init_ports(pcie); - err = mt7621_pcie_enable_ports(pcie); + err = mt7621_pcie_enable_ports(bridge); if (err) { dev_err(dev, "Error enabling pcie ports\n"); goto remove_resets; } - setup_cm_memory_region(pcie); + err = setup_cm_memory_region(bridge); + if (err) { + dev_err(dev, "Error setting up iocu mem regions\n"); + goto remove_resets; + } return mt7621_pcie_register_host(bridge); From patchwork Sun Jun 13 15:56:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12317775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 101F4C48BDF for ; Sun, 13 Jun 2021 15:57:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D656761285 for ; Sun, 13 Jun 2021 15:57:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231913AbhFMP7p (ORCPT ); Sun, 13 Jun 2021 11:59:45 -0400 Received: from mail-wm1-f49.google.com ([209.85.128.49]:50783 "EHLO mail-wm1-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231844AbhFMP7p (ORCPT ); Sun, 13 Jun 2021 11:59:45 -0400 Received: by mail-wm1-f49.google.com with SMTP id d184so10700350wmd.0 for ; Sun, 13 Jun 2021 08:57:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Eqtg1+fbJlMCohN2MghF9TKMofIxShR1miILFIvbuXo=; b=aqnqVbgEFUWxR+Qy9iGlYx07qrJgGmTJBGXNYQ9iIgruAXAEAkZx1UHaDqBgicpgXb vt2SQ968igKkZpV7Hc1E+A3dAYR80r4Suq9VXb6ujVG4Cr6l4KZooRNMMo6OUx9pz6m2 LyanJ9UOp3ca/ZUhbMPYuvCbbM6BF3FVYv+nzwXBcGCA87Wn+8ocxQKkaDsV1zLET22E StCsuM224y/ul5f6sONBV1Sh2E7UN/jtAgcqgS1X2w0AqwntW0fo4hxz6PjiH5QGfNsC onXpzXvwfhDUrASBT1mERg6PfGLUIJm/ycUMr6fGFppPB11EJ4ydjV3er+5UEl+N6xcV xQjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Eqtg1+fbJlMCohN2MghF9TKMofIxShR1miILFIvbuXo=; b=R5w25qcTOz5CrCfMl9+angMjUUR79cv6MPmJ9yESGIAHMV4mCnLKU7ae0waiPx/rW4 g14Bi+1bgEybyCXX7KzCH3ibEwT/ykBftVMDvgXkkqjhhL6LbXKe/td7zMu6YilQXVmD mpkdWvdCXQOp2xDsHpHAYlPKOyU8CI3tCV6vtg8gP4swJ+KwvVq1mgKXGcmlDqm9bH2M W1Z3woC8eN3dmlvKMdRkZQfIUT5mwYhOGZrPYjLwXQ+OYeJ9YgpzvZXTALZROj+mXVQt 0YnSwPFt1d8TWlS2cJG19IjeljZrPu2WclPAp/L9/tYrHttzbjeQNcA1IJ3qF3ApqePX qO4Q== X-Gm-Message-State: AOAM5304W6WDPMu/5ZG7Gb3QLkDG/4CxzjQTmStouYVv1hYOP17oy+st aP7MN3zhf05v6PH6tD/pfqo= X-Google-Smtp-Source: ABdhPJzn6deyzLma154OGI+jhNI78UihPVmufIOcMJ+81krmmS3QJ7Vy6g6K15b1LShq71g8il7fVA== X-Received: by 2002:a1c:a484:: with SMTP id n126mr28984602wme.34.1623599788241; Sun, 13 Jun 2021 08:56:28 -0700 (PDT) Received: from localhost.localdomain (98.red-81-38-58.dynamicip.rima-tde.net. [81.38.58.98]) by smtp.gmail.com with ESMTPSA id g17sm17539746wrh.72.2021.06.13.08.56.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jun 2021 08:56:27 -0700 (PDT) From: Sergio Paracuellos To: linux-staging@lists.linux.dev Cc: gregkh@linuxfoundation.org, neil@brown.name, linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, ilya.lipnitskiy@gmail.com, john@phrozen.org Subject: [PATCH 3/3] staging: mt7621-dts: fix pci address for PCI memory range Date: Sun, 13 Jun 2021 17:56:23 +0200 Message-Id: <20210613155623.17233-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210613155623.17233-1-sergio.paracuellos@gmail.com> References: <20210613155623.17233-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Driver code call 'devm_of_pci_get_host_bridge_resources' to get resources and properly fill 'bridge->windows' and 'bridge->dma_ranges'. After parsing the ranges and store as resources, at the end it makes a call to pci function 'pci_add_resource_offset' to set the offset for the memory resource. To calculate offset, resource start address subtracts pci address of the range. MT7621 does not need any offset for the memory resource. Moreover, setting an offset got into 'WARN_ON' calls from pci devices driver code. Until now memory range pci_addr was being '0x00000000' and res->start is '0x60000000' but becase pci controller driver was manually setting resources and adding them using pci function 'pci_add_resource' where a zero is passed as offset, things was properly working. Since PCI_IOBASE is defined now for ralink we don't set nothing manually anymore so we have to properly fix PCI address for this range to make things work and the new pci address must be set to '0x60000000'. Doing in this way the subtract result obtain zero as offset and pci device driver code properly works. Fixes: d59578da2bb8 ("staging: mt7621-dts: add dts files") Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index ecfe2f2cf75a..f15ea61851b2 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -489,7 +489,7 @@ pcie: pcie@1e140000 { device_type = "pci"; - ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */ + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ #interrupt-cells = <1>;