From patchwork Mon Jun 14 10:06:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12318477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87DDDC48BE6 for ; Mon, 14 Jun 2021 10:06:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 66C74611BE for ; Mon, 14 Jun 2021 10:06:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232579AbhFNKI1 (ORCPT ); Mon, 14 Jun 2021 06:08:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232691AbhFNKI0 (ORCPT ); Mon, 14 Jun 2021 06:08:26 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 708D6C061766 for ; Mon, 14 Jun 2021 03:06:21 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id n7so7718581wri.3 for ; Mon, 14 Jun 2021 03:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N0fsKa0m+ct2TNQQ9Pb5MMJ8S0hfbem4WCcQmEP55Aw=; b=alZqxe/iNgMwZ4sWImtm00CDmdvzVwc0Fe2Ol7kiL2X2JKrhnquF+MUcRTvC/sjvwW aug8+vpOmTsktZH4AOE0DWwMMAMUsNXAPgxON3hjkOlsFpZyT10qeWvpZOrB79rkC5Tr 7Hx3FekROUivbEnrigJ7s0+7bXFfZsOLlT6c9+Pp9MpNVZV+VHq95YLZM/gAoNlqqHnE LlszW+ORwsdXV6Mhfrcmx+R9OyYXuNHtTQuabohzy9k1epJznKP50fnWPZbssZRA7wyL +7ym7O7R9TDSyVguePFoiw5uziIkNiUIWxOtwgz9WWr8JiSUoXIdB5mkKOtDGCQcaI9j TMdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N0fsKa0m+ct2TNQQ9Pb5MMJ8S0hfbem4WCcQmEP55Aw=; b=Bi01bPEyIQSYgJwX8yVOq8yYCKIAIgbfcUxsj1PPr+J9HfDehd+bvgllzCZgTlMeCB 0+BGzL9YgFt01DptZI7l2yoTq6QgzWrmL9lORCVp/INfO9ksKHuCPapL7BvBgt3PKv8j irf6nC/xqUC6AxIjA8qWN9f2SzEwoBLJNuUiTJf6mjaabqNCU48CAQq7r8YEw/XqcQKk FMPOFZG4Cft0ftc/mhrdxMuG1fvgRDKlY8iyxwLU4X6G+fFgDrbdXmmsfi9/L0hT0Jh5 3EW3MrOn2ihr8+HqH8W1KMZsjjv7j+vcus98VhoroF3ToiLpYoST9wm8NRjIdpIAWtt1 nBsA== X-Gm-Message-State: AOAM533WigvHX/xs6afxp9HgUgmhp7A2ro7m61LpnmWqX7U86G3oQCS/ qkQwPysYbRLB+hmP05eDNOQ= X-Google-Smtp-Source: ABdhPJzF4cE/D7foVs4lkEe8wDLIxb9sDkQiX242rhjvHu3/KfrF25c7Jc6fMYsZzwriWltz1gRwaA== X-Received: by 2002:a5d:4538:: with SMTP id j24mr17707142wra.391.1623665179977; Mon, 14 Jun 2021 03:06:19 -0700 (PDT) Received: from localhost.localdomain (98.red-81-38-58.dynamicip.rima-tde.net. [81.38.58.98]) by smtp.gmail.com with ESMTPSA id k5sm16476566wrv.85.2021.06.14.03.06.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jun 2021 03:06:19 -0700 (PDT) From: Sergio Paracuellos To: linux-staging@lists.linux.dev Cc: gregkh@linuxfoundation.org, neil@brown.name, linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, ilya.lipnitskiy@gmail.com, john@phrozen.org Subject: [PATCH v2 1/3] MIPS: ralink: Define PCI_IOBASE Date: Mon, 14 Jun 2021 12:06:15 +0200 Message-Id: <20210614100617.28753-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210614100617.28753-1-sergio.paracuellos@gmail.com> References: <20210614100617.28753-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org PCI_IOBASE is used to create VM maps for PCI I/O ports, it is required by generic PCI drivers to make memory mapped I/O range work. Hence define it for ralink architectures to be able to avoid parsing manually IO ranges in PCI generic driver code. Function 'plat_mem_setup' for ralink is using 'set_io_port_base' call using '0xa0000000' as address, so use the same address in the definition to align things. Signed-off-by: Sergio Paracuellos Acked-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-ralink/spaces.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/mips/include/asm/mach-ralink/spaces.h diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h new file mode 100644 index 000000000000..87d085c9ad61 --- /dev/null +++ b/arch/mips/include/asm/mach-ralink/spaces.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_RALINK_SPACES_H_ +#define __ASM_MACH_RALINK_SPACES_H_ + +#define PCI_IOBASE _AC(0xa0000000, UL) +#define PCI_IOSIZE SZ_16M +#define IO_SPACE_LIMIT (PCI_IOSIZE - 1) + +#include +#endif From patchwork Mon Jun 14 10:06:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12318479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5728FC2B9F4 for ; Mon, 14 Jun 2021 10:06:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B7C7611BE for ; Mon, 14 Jun 2021 10:06:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232747AbhFNKI3 (ORCPT ); Mon, 14 Jun 2021 06:08:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232698AbhFNKI2 (ORCPT ); Mon, 14 Jun 2021 06:08:28 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE254C061574 for ; Mon, 14 Jun 2021 03:06:25 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id c9so13872865wrt.5 for ; Mon, 14 Jun 2021 03:06:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U+7KMa4x9I3RPmCk8B+EWnxSMOxLFlMAChoVtPf3+Qw=; b=ri7gFhMP/nBzhc/hFq0ftuZCNTZIix/tCuEuVdnuYr8GKDRoOjxKqtvj8k+u5J+oIP Y+0sp5k6yHZwvPHT0OCB504wk8e77SY5HoswYwsTvjAHriY8DCgljE5Yi/UM36sfNtoD h0RzL2u44+7mnWAmae5Ou5ZVvywhUrDlEqlggwcwInXMsdmopeHKQFz2sBma0VFQfoXT QF/M9AnD/Gq4YgnDHkJiTtxROqys3qIG9dHjKEWjrjClCO0n5aGLun8F7t/fGxFdA1gL YfG8+Tn6LKY790iGi6mYICwnVYiosiT0XNNa96sadV9iU6H6pQ9/5SLdIzvUbL32ve8J L3yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U+7KMa4x9I3RPmCk8B+EWnxSMOxLFlMAChoVtPf3+Qw=; b=FabaeMBUhfpZItwB+YIGaGsRKhXD39g6U6jx7oL3zTj/GkqrMxemAeYPBFMm7Xdvtu UT3c5NDg7cUHUPh8oEUPSkN1MLpmrT2HUaGhvIMEztxqJ6Xedfi4j6J2j+iUDJh061xG fmk7co54vcEi7+bcDQcsYmiBp969fUzNfHGMpuvt4lLbAmEaM3NC/IKBeFi4E7BBXCwv zzIfgwG0GEwU5u1Zid49In37we63ueG1W96xSjFZUHj+mBgDlji1HAOWFi7oyLNdSxHi JzwL6tZ10BxBoyKt13CjRi2LPccIx/z1R8QT9mTV1U4R98nzSf5WCllzS6nZDiEJLWLE tldg== X-Gm-Message-State: AOAM5335/jfi4shf8ZVfT906mlUxjogw1GCSE77v637T51bSxY7QxmYT 6cvVKFbKrvJ1lkYBCX/bv2I= X-Google-Smtp-Source: ABdhPJzGDQwVT0svJUq+IYNQz6SmADbXkgPWvW/PKnib42t3b8iw7xJUEdpzQex89k3Qdho4yExDGA== X-Received: by 2002:a5d:6da2:: with SMTP id u2mr17788354wrs.355.1623665180889; Mon, 14 Jun 2021 03:06:20 -0700 (PDT) Received: from localhost.localdomain (98.red-81-38-58.dynamicip.rima-tde.net. [81.38.58.98]) by smtp.gmail.com with ESMTPSA id k5sm16476566wrv.85.2021.06.14.03.06.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jun 2021 03:06:20 -0700 (PDT) From: Sergio Paracuellos To: linux-staging@lists.linux.dev Cc: gregkh@linuxfoundation.org, neil@brown.name, linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, ilya.lipnitskiy@gmail.com, john@phrozen.org Subject: [PATCH v2 2/3] staging: mt7621-pci: remove 'mt7621_pci_parse_request_of_pci_ranges' Date: Mon, 14 Jun 2021 12:06:16 +0200 Message-Id: <20210614100617.28753-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210614100617.28753-1-sergio.paracuellos@gmail.com> References: <20210614100617.28753-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org After 'PCI_IOBASE' is defined for ralink, ranges are properly parsed using pci generic APIS and there is no need to parse anything manually. So function 'mt7621_pci_parse_request_of_pci_ranges' used for this can be enterely removed. Since we have to configure iocu memory regions and pci io windows resources must be retrieved accordly from 'bridge->windows' but there is no need to store anything as driver private data. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 100 +++++++----------------- 1 file changed, 27 insertions(+), 73 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index b0b5700cbfec..691030e1a5ed 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -86,10 +86,7 @@ struct mt7621_pcie_port { /** * struct mt7621_pcie - PCIe host information * @base: IO Mapped Register Base - * @io: IO resource - * @mem: pointer to non-prefetchable memory resource * @dev: Pointer to PCIe device - * @io_map_base: virtual memory base address for io * @ports: pointer to PCIe port information * @resets_inverted: depends on chip revision * reset lines are inverted. @@ -97,9 +94,6 @@ struct mt7621_pcie_port { struct mt7621_pcie { void __iomem *base; struct device *dev; - struct resource io; - struct resource *mem; - unsigned long io_map_base; struct list_head ports; bool resets_inverted; }; @@ -213,75 +207,33 @@ static inline void mt7621_control_deassert(struct mt7621_pcie_port *port) reset_control_assert(port->pcie_rst); } -static void setup_cm_memory_region(struct mt7621_pcie *pcie) +static int setup_cm_memory_region(struct pci_host_bridge *host) { - struct resource *mem_resource = pcie->mem; + struct mt7621_pcie *pcie = pci_host_bridge_priv(host); struct device *dev = pcie->dev; + struct resource_entry *entry; resource_size_t mask; + entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (!entry) { + dev_err(dev, "Cannot get memory resource\n"); + return -EINVAL; + } + if (mips_cps_numiocu(0)) { /* * FIXME: hardware doesn't accept mask values with 1s after * 0s (e.g. 0xffef), so it would be great to warn if that's * about to happen */ - mask = ~(mem_resource->end - mem_resource->start); + mask = ~(entry->res->end - entry->res->start); - write_gcr_reg1_base(mem_resource->start); + write_gcr_reg1_base(entry->res->start); write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n", (unsigned long long)read_gcr_reg1_base(), (unsigned long long)read_gcr_reg1_mask()); } -} - -static int mt7621_pci_parse_request_of_pci_ranges(struct pci_host_bridge *host) -{ - struct mt7621_pcie *pcie = pci_host_bridge_priv(host); - struct device *dev = pcie->dev; - struct device_node *node = dev->of_node; - struct of_pci_range_parser parser; - struct resource_entry *entry; - struct of_pci_range range; - LIST_HEAD(res); - - if (of_pci_range_parser_init(&parser, node)) { - dev_err(dev, "missing \"ranges\" property\n"); - return -EINVAL; - } - - /* - * IO_SPACE_LIMIT for MIPS is 0xffff but this platform uses IO at - * upper address 0x001e160000. of_pci_range_to_resource does not work - * well for MIPS platforms that don't define PCI_IOBASE, so set the IO - * resource manually instead. - */ - for_each_of_pci_range(&parser, &range) { - switch (range.flags & IORESOURCE_TYPE_BITS) { - case IORESOURCE_IO: - pcie->io_map_base = - (unsigned long)ioremap(range.cpu_addr, - range.size); - pcie->io.name = node->full_name; - pcie->io.flags = range.flags; - pcie->io.start = range.cpu_addr; - pcie->io.end = range.cpu_addr + range.size - 1; - pcie->io.parent = pcie->io.child = pcie->io.sibling = NULL; - set_io_port_base(pcie->io_map_base); - break; - } - } - - entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); - if (!entry) { - dev_err(dev, "Cannot get memory resource"); - return -EINVAL; - } - - pcie->mem = entry->res; - pci_add_resource(&res, &pcie->io); - pci_add_resource(&res, entry->res); - list_splice_init(&res, &host->windows); return 0; } @@ -510,15 +462,23 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) write_config(pcie, slot, PCIE_FTS_NUM, val); } -static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) +static int mt7621_pcie_enable_ports(struct pci_host_bridge *host) { + struct mt7621_pcie *pcie = pci_host_bridge_priv(host); struct device *dev = pcie->dev; struct mt7621_pcie_port *port; + struct resource_entry *entry; int err; + entry = resource_list_first_type(&host->windows, IORESOURCE_IO); + if (!entry) { + dev_err(dev, "Cannot get io resource\n"); + return -EINVAL; + } + /* Setup MEMWIN and IOWIN */ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); - pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE); + pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE); list_for_each_entry(port, &pcie->ports, list) { if (port->enabled) { @@ -581,25 +541,19 @@ static int mt7621_pci_probe(struct platform_device *pdev) return err; } - err = mt7621_pci_parse_request_of_pci_ranges(bridge); - if (err) { - dev_err(dev, "Error requesting pci resources from ranges"); - goto remove_resets; - } - - /* set resources limits */ - ioport_resource.start = pcie->io.start; - ioport_resource.end = pcie->io.end; - mt7621_pcie_init_ports(pcie); - err = mt7621_pcie_enable_ports(pcie); + err = mt7621_pcie_enable_ports(bridge); if (err) { dev_err(dev, "Error enabling pcie ports\n"); goto remove_resets; } - setup_cm_memory_region(pcie); + err = setup_cm_memory_region(bridge); + if (err) { + dev_err(dev, "Error setting up iocu mem regions\n"); + goto remove_resets; + } return mt7621_pcie_register_host(bridge); From patchwork Mon Jun 14 10:06:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 12318481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88C2AC2B9F4 for ; Mon, 14 Jun 2021 10:07:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D285611AB for ; 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[81.38.58.98]) by smtp.gmail.com with ESMTPSA id k5sm16476566wrv.85.2021.06.14.03.06.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jun 2021 03:06:21 -0700 (PDT) From: Sergio Paracuellos To: linux-staging@lists.linux.dev Cc: gregkh@linuxfoundation.org, neil@brown.name, linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, ilya.lipnitskiy@gmail.com, john@phrozen.org Subject: [PATCH v2 3/3] staging: mt7621-dts: fix pci address for PCI memory range Date: Mon, 14 Jun 2021 12:06:17 +0200 Message-Id: <20210614100617.28753-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210614100617.28753-1-sergio.paracuellos@gmail.com> References: <20210614100617.28753-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Driver code call 'devm_of_pci_get_host_bridge_resources' to get resources and properly fill 'bridge->windows' and 'bridge->dma_ranges'. After parsing the ranges and store as resources, at the end it makes a call to pci function 'pci_add_resource_offset' to set the offset for the memory resource. To calculate offset, resource start address subtracts pci address of the range. MT7621 does not need any offset for the memory resource. Moreover, setting an offset got into 'WARN_ON' calls from pci devices driver code. Until now memory range pci_addr was being '0x00000000' and res->start is '0x60000000' but becase pci controller driver was manually setting resources and adding them using pci function 'pci_add_resource' where a zero is passed as offset, things was properly working. Since PCI_IOBASE is defined now for ralink we don't set nothing manually anymore so we have to properly fix PCI address for this range to make things work and the new pci address must be set to '0x60000000'. Doing in this way the subtract result obtain zero as offset and pci device driver code properly works. Fixes: d59578da2bb8 ("staging: mt7621-dts: add dts files") Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index ecfe2f2cf75a..f15ea61851b2 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -489,7 +489,7 @@ pcie: pcie@1e140000 { device_type = "pci"; - ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */ + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ #interrupt-cells = <1>;