From patchwork Wed Jun 16 00:20:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Schofield X-Patchwork-Id: 12323431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15796C49361 for ; Wed, 16 Jun 2021 00:24:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F144C613D0 for ; Wed, 16 Jun 2021 00:24:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231703AbhFPA1A (ORCPT ); Tue, 15 Jun 2021 20:27:00 -0400 Received: from mga03.intel.com ([134.134.136.65]:14098 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231617AbhFPA07 (ORCPT ); Tue, 15 Jun 2021 20:26:59 -0400 IronPort-SDR: PHHp/uaotySIAnY/IlzG3oWPpKTdZzc00YSr8NKIWiZr7IijQIYSIyYOXH0T2nndKPjJc0MyFw d2Tde+RVzh9g== X-IronPort-AV: E=McAfee;i="6200,9189,10016"; a="206127848" X-IronPort-AV: E=Sophos;i="5.83,276,1616482800"; d="scan'208";a="206127848" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2021 17:24:53 -0700 IronPort-SDR: ABp0BcE4Y1Oohh52DpbwdVeMQyfffX9TC1jLS2/naX0YKbMcMS4ghMbi9TtbWPWgciDPFZaAdU wGNi3gMj7lOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,276,1616482800"; d="scan'208";a="639822561" Received: from alison-desk.jf.intel.com (HELO alison-desk) ([10.54.74.53]) by fmsmga005.fm.intel.com with ESMTP; 15 Jun 2021 17:24:53 -0700 From: Alison Schofield To: Ben Widawsky , Dan Williams , Ira Weiny , Alison Schofield , Vishal Verma Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Linux ACPI Subject: [PATCH v2 1/2] cxl/acpi: Add the Host Bridge base address to CXL port objects Date: Tue, 15 Jun 2021 17:20:38 -0700 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The base address for the Host Bridge port component registers is located in the CXL Host Bridge Structure (CHBS) of the ACPI CXL Early Discovery Table (CEDT). Retrieve the CHBS for each Host Bridge (ACPI0016 device) and include that base address in the port object. Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Signed-off-by: Alison Schofield --- drivers/cxl/acpi.c | 105 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 99 insertions(+), 6 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index be357eea552c..b6d9cd45428c 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -8,6 +8,61 @@ #include #include "cxl.h" +static struct acpi_table_header *cedt_table; + +static struct acpi_cedt_chbs *cxl_acpi_match_chbs(struct device *dev, u32 uid) +{ + struct acpi_cedt_chbs *chbs, *chbs_match = NULL; + acpi_size len, cur = 0; + void *cedt_base; + int rc = 0; + + len = cedt_table->length - sizeof(*cedt_table); + cedt_base = cedt_table + 1; + + while (cur < len) { + struct acpi_cedt_header *c = cedt_base + cur; + + if (c->type != ACPI_CEDT_TYPE_CHBS) { + cur += c->length; + continue; + } + + chbs = cedt_base + cur; + + if (chbs->header.length < sizeof(*chbs)) { + dev_err(dev, "Invalid CHBS header length: %u\n", + chbs->header.length); + rc = -EINVAL; + break; + } + + if (chbs->uid == uid && !chbs_match) { + chbs_match = chbs; + cur += c->length; + continue; + } + + if (chbs->uid == uid && chbs_match) { + dev_err(dev, "Duplicate CHBS UIDs %u\n", uid); + rc = -EINVAL; + break; + } + cur += c->length; + } + if (!chbs_match) + rc = -EINVAL; + if (rc) + return ERR_PTR(rc); + + return chbs_match; +} + +static resource_size_t get_chbcr(struct acpi_cedt_chbs *chbs) +{ + return IS_ERR(chbs) ? CXL_RESOURCE_NONE : chbs->base; +} + struct cxl_walk_context { struct device *dev; struct pci_bus *root; @@ -50,6 +105,21 @@ static int match_add_root_ports(struct pci_dev *pdev, void *data) return 0; } +static struct cxl_dport *find_dport_by_dev(struct cxl_port *port, struct device *dev) +{ + struct cxl_dport *dport; + + device_lock(&port->dev); + list_for_each_entry(dport, &port->dports, list) + if (dport->dport == dev) { + device_unlock(&port->dev); + return dport; + } + + device_unlock(&port->dev); + return NULL; +} + static struct acpi_device *to_cxl_host_bridge(struct device *dev) { struct acpi_device *adev = to_acpi_device(dev); @@ -71,6 +141,7 @@ static int add_host_bridge_uport(struct device *match, void *arg) struct acpi_pci_root *pci_root; struct cxl_walk_context ctx; struct cxl_decoder *cxld; + struct cxl_dport *dport; struct cxl_port *port; if (!bridge) @@ -80,8 +151,15 @@ static int add_host_bridge_uport(struct device *match, void *arg) if (!pci_root) return -ENXIO; - /* TODO: fold in CEDT.CHBS retrieval */ - port = devm_cxl_add_port(host, match, CXL_RESOURCE_NONE, root_port); + dport = find_dport_by_dev(root_port, match); + if (!dport) { + dev_dbg(host, "host bridge expected and not found\n"); + return -ENODEV; + } + + port = devm_cxl_add_port(host, match, dport->component_reg_phys, + root_port); + if (IS_ERR(port)) return PTR_ERR(port); dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev)); @@ -120,6 +198,7 @@ static int add_host_bridge_dport(struct device *match, void *arg) int rc; acpi_status status; unsigned long long uid; + struct acpi_cedt_chbs *chbs; struct cxl_port *root_port = arg; struct device *host = root_port->dev.parent; struct acpi_device *bridge = to_cxl_host_bridge(match); @@ -135,7 +214,12 @@ static int add_host_bridge_dport(struct device *match, void *arg) return -ENODEV; } - rc = cxl_add_dport(root_port, match, uid, CXL_RESOURCE_NONE); + chbs = cxl_acpi_match_chbs(host, uid); + if (IS_ERR(chbs)) + dev_dbg(host, "No CHBS found for Host Bridge: %s\n", + dev_name(match)); + + rc = cxl_add_dport(root_port, match, uid, get_chbcr(chbs)); if (rc) { dev_err(host, "failed to add downstream port: %s\n", dev_name(match)); @@ -148,6 +232,7 @@ static int add_host_bridge_dport(struct device *match, void *arg) static int cxl_acpi_probe(struct platform_device *pdev) { int rc; + acpi_status status; struct cxl_port *root_port; struct device *host = &pdev->dev; struct acpi_device *adev = ACPI_COMPANION(host); @@ -157,17 +242,25 @@ static int cxl_acpi_probe(struct platform_device *pdev) return PTR_ERR(root_port); dev_dbg(host, "add: %s\n", dev_name(&root_port->dev)); + status = acpi_get_table(ACPI_SIG_CEDT, 0, &cedt_table); + if (ACPI_FAILURE(status)) + return -ENXIO; + rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, add_host_bridge_dport); if (rc) - return rc; + goto out; /* * Root level scanned with host-bridge as dports, now scan host-bridges * for their role as CXL uports to their CXL-capable PCIe Root Ports. */ - return bus_for_each_dev(adev->dev.bus, NULL, root_port, - add_host_bridge_uport); + rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, + add_host_bridge_uport); + +out: + acpi_put_table(cedt_table); + return rc; } static const struct acpi_device_id cxl_acpi_ids[] = { From patchwork Wed Jun 16 00:20:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Schofield X-Patchwork-Id: 12323429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62180C49EA3 for ; Wed, 16 Jun 2021 00:24:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E3E56109E for ; Wed, 16 Jun 2021 00:24:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231760AbhFPA1A (ORCPT ); Tue, 15 Jun 2021 20:27:00 -0400 Received: from mga03.intel.com ([134.134.136.65]:14098 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230265AbhFPA1A (ORCPT ); Tue, 15 Jun 2021 20:27:00 -0400 IronPort-SDR: cKMRZeDd4ytlVBa0Opv7CZifVTPJ3wa2DryC0y4LHSxaEFAm9gUZ39bo7qYqAxw+e8zW05SjUs v5gWKifDDbIw== X-IronPort-AV: E=McAfee;i="6200,9189,10016"; a="206127849" X-IronPort-AV: E=Sophos;i="5.83,276,1616482800"; d="scan'208";a="206127849" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2021 17:24:53 -0700 IronPort-SDR: KovZsLBtH8r7kPsBjZf9/jGCgKTsVj9BdMVKA3AqxT0dY4iJBKtAC8yfmyuxenvm7ccx99I7D2 Vx7ILPfB03RA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,276,1616482800"; d="scan'208";a="639822567" Received: from alison-desk.jf.intel.com (HELO alison-desk) ([10.54.74.53]) by fmsmga005.fm.intel.com with ESMTP; 15 Jun 2021 17:24:53 -0700 From: Alison Schofield To: Ben Widawsky , Dan Williams , Ira Weiny , Alison Schofield , Vishal Verma Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Linux ACPI Subject: [PATCH v2 2/2] cxl/acpi: Use the ACPI CFMWS to create static decoder objects Date: Tue, 15 Jun 2021 17:20:39 -0700 Message-Id: <48f1b59105e46f04b38347fc1555bb5c8d654cff.1623800340.git.alison.schofield@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The ACPI CXL Early Discovery Table (CEDT) includes a list of CXL memory resources in CXL Fixed Memory Window Structures (CFMWS). Retrieve each CFMWS in the CEDT and add a cxl_decoder object to the root port (root0) for each memory resource. Signed-off-by: Alison Schofield Reviewed-by: Jonathan Cameron --- drivers/cxl/acpi.c | 114 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index b6d9cd45428c..e3aa356d4dcd 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -8,8 +8,120 @@ #include #include "cxl.h" +/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ +#define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways) +#define CFMWS_INTERLEAVE_GRANULARITY(x) ((x)->granularity + 8) + static struct acpi_table_header *cedt_table; +static unsigned long cfmws_to_decoder_flags(int restrictions) +{ + unsigned long flags = 0; + + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) + flags |= CXL_DECODER_F_TYPE2; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) + flags |= CXL_DECODER_F_TYPE3; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) + flags |= CXL_DECODER_F_RAM; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) + flags |= CXL_DECODER_F_PMEM; + if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED) + flags |= CXL_DECODER_F_LOCK; + + return flags; +} + +static int cxl_acpi_cfmws_verify(struct device *dev, + struct acpi_cedt_cfmws *cfmws) +{ + int expected_len; + + if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { + dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n"); + return -EINVAL; + } + + if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) { + dev_err(dev, "CFMWS Base HPA not 256MB aligned\n"); + return -EINVAL; + } + + if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) { + dev_err(dev, "CFMWS Window Size not 256MB aligned\n"); + return -EINVAL; + } + + expected_len = struct_size((cfmws), interleave_targets, + CFMWS_INTERLEAVE_WAYS(cfmws)); + + if (expected_len != cfmws->header.length) { + dev_err(dev, "CFMWS interleave ways and targets mismatch\n"); + return -EINVAL; + } + + return 0; +} + +static void cxl_add_cfmws_decoders(struct device *dev, + struct cxl_port *root_port) +{ + struct acpi_cedt_cfmws *cfmws; + struct cxl_decoder *cxld; + acpi_size len, cur = 0; + void *cedt_base; + int rc; + + len = cedt_table->length - sizeof(*cedt_table); + cedt_base = cedt_table + 1; + + while (cur < len) { + struct acpi_cedt_header *c = cedt_base + cur; + + if (c->type != ACPI_CEDT_TYPE_CFMWS) { + cur += c->length; + continue; + } + + cfmws = cedt_base + cur; + + if (cfmws->header.length < sizeof(*cfmws)) { + dev_err(dev, "Invalid CFMWS header length %u\n", + cfmws->header.length); + dev_err(dev, "Failed to add decoders\n"); + return; + } + + rc = cxl_acpi_cfmws_verify(dev, cfmws); + if (rc) { + dev_err(dev, "CFMWS range %#llx-%#llx not registered\n", + cfmws->base_hpa, cfmws->base_hpa + + cfmws->window_size - 1); + cur += c->length; + continue; + } + + cxld = devm_cxl_add_decoder(dev, root_port, + CFMWS_INTERLEAVE_WAYS(cfmws), + cfmws->base_hpa, cfmws->window_size, + CFMWS_INTERLEAVE_WAYS(cfmws), + CFMWS_INTERLEAVE_GRANULARITY(cfmws), + CXL_DECODER_EXPANDER, + cfmws_to_decoder_flags(cfmws->restrictions)); + + if (IS_ERR(cxld)) { + dev_err(dev, "Failed to add decoder for %#llx-%#llx\n", + cfmws->base_hpa, cfmws->base_hpa + + cfmws->window_size - 1); + } else { + dev_dbg(dev, "add: %s range %#llx-%#llx\n", + dev_name(&cxld->dev), cfmws->base_hpa, + cfmws->base_hpa + cfmws->window_size - 1); + } + cur += c->length; + } +} + static struct acpi_cedt_chbs *cxl_acpi_match_chbs(struct device *dev, u32 uid) { struct acpi_cedt_chbs *chbs, *chbs_match = NULL; @@ -251,6 +363,8 @@ static int cxl_acpi_probe(struct platform_device *pdev) if (rc) goto out; + cxl_add_cfmws_decoders(host, root_port); + /* * Root level scanned with host-bridge as dports, now scan host-bridges * for their role as CXL uports to their CXL-capable PCIe Root Ports.