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[2a00:1028:8386:da8a:eacb:c188:78b9:634c]) by smtp.gmail.com with ESMTPSA id k32sm1764304edb.42.2018.11.30.16.02.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 16:02:11 -0800 (PST) From: Andrea Parri To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH] riscv, atomic: Add #define's for the atomic_{cmp, }xchg_*() variants Date: Sat, 1 Dec 2018 01:01:56 +0100 Message-Id: <20181201000156.5366-1-andrea.parri@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181130_160224_935033_CE6AF83B X-CRM114-Status: UNSURE ( 8.59 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrea Parri , Albert Ou , Peter Zijlstra , Boqun Feng , Palmer Dabbelt , Will Deacon MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP If an architecture does not define the atomic_{cmp,}xchg_*() variants, the generic implementation defaults them to the fully-ordered version. riscv's had its own variants since "the beginning", but it never told (#define-d these for) the generic implementation: it is time to do so. Signed-off-by: Andrea Parri Cc: Palmer Dabbelt Cc: Albert Ou Cc: Will Deacon Cc: Peter Zijlstra Cc: Boqun Feng Acked-by: Peter Zijlstra (Intel) --- TBH, the delay was not intentional: I've just become aware of it while working on moving riscv over to queued rwlocks. There's currently one callsite for the non-fully-ordered variants mentioned above for riscv: for atomic_cmpxchg_acquire() in kernel/sched/rt.c:rto_start_trylock(), [before] 51a: 100726af lr.w a3,(a4) 51e: 00069763 bnez a3,52c <.L17> 522: 1af7262f sc.w.rl a2,a5,(a4) 526: fa75 bnez a2,51a <.L1> 528: 0330000f fence rw,rw [after] 51a: 100726af lr.w a3,(a4) 51e: 00069763 bnez a3,52c <.L17> 522: 18f7262f sc.w a2,a5,(a4) 526: fa75 bnez a2,51a <.L1> 528: 0230000f fence r,rw --- arch/riscv/include/asm/atomic.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index c452359c9cb8a..93826771b616a 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -303,6 +303,15 @@ c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ ATOMIC_OPS() +#define atomic_xchg_relaxed atomic_xchg_relaxed +#define atomic_xchg_acquire atomic_xchg_acquire +#define atomic_xchg_release atomic_xchg_release +#define atomic_xchg atomic_xchg +#define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed +#define atomic_cmpxchg_acquire atomic_cmpxchg_acquire +#define atomic_cmpxchg_release atomic_cmpxchg_release +#define atomic_cmpxchg atomic_cmpxchg + #undef ATOMIC_OPS #undef ATOMIC_OP