From patchwork Sat Dec 1 00:52:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10707503 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD73616B1 for ; Sat, 1 Dec 2018 00:54:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D0AF026E76 for ; Sat, 1 Dec 2018 00:54:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C52552F272; Sat, 1 Dec 2018 00:54:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75F4F26E76 for ; Sat, 1 Dec 2018 00:54:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726571AbeLAMEi (ORCPT ); Sat, 1 Dec 2018 07:04:38 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:36533 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726637AbeLAMEh (ORCPT ); Sat, 1 Dec 2018 07:04:37 -0500 Received: by mail-pg1-f195.google.com with SMTP id n2so3212352pgm.3 for ; Fri, 30 Nov 2018 16:53:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Af+pB+6KYWG/war09y7KjqxVZ2laXeJjW1k19D2PuXo=; b=eqiVLNYql5hobYHZOsC+uBixktHTEz5qCejw0Xf2tlizgV4BCc9zn9JeMKl6a7cGZu XahwOB0NUCXyN+2zJtsi5SjvDpPD+nVEw48CI5yGHCac+lDwyq02JewstTYNQP3rtauP yc3CcRruaZfBQ7ukB8R2DbdSqPmMsKzebv3+U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Af+pB+6KYWG/war09y7KjqxVZ2laXeJjW1k19D2PuXo=; b=j/vTG1GNOSuuHoXBwi3LdogAdgWkFHi206fkJ4G6oNVQHC0GvJ7PlQT/f0xK2H4aqQ PRkrU9845owJV02nQwaLH6cWLwtaOAFBQ+f8s6OX7EdM6Ez3/R7faDntqHfVR25rkk2c 2xXsikyWiy8HjfLg8cn17B4Utrgs+p7+UxZnixxcLAntVLQX3LZAKdrUBPs4/FmmpDYg QuUFIrQJgJ1fRbxSmXjBAfnfqyPOSY4D0khdXB0w0Mhzsdn92jsHBP/CNZVITBagd/9o CQPJGj90IES3uUpt3WdraBNR2npKwm5uTc2CzyPIU7rfCFAfkaR62EOwwxBKk9a4RXo8 K/mw== X-Gm-Message-State: AA+aEWb+CHVzW9dV3DmwRDQQAem+Cv6P+ofIEjnhN8xNcJ1G3gTb3cKi l0ukivKvvXiwtc3QwdcMF8Y+7Q== X-Google-Smtp-Source: AFSGD/XqwPiekgMOIJhtR3M4IEWaj3fNMnBTDXwMLxI8TiroG1xCYJ3Pcm2crLJRYrw6ofdoCkmXgA== X-Received: by 2002:a65:41c2:: with SMTP id b2mr6498839pgq.67.1543625605751; Fri, 30 Nov 2018 16:53:25 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:b6af:f85:ed6c:ac6a]) by smtp.gmail.com with ESMTPSA id z8sm16518566pgz.53.2018.11.30.16.53.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 16:53:25 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v3 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs Date: Fri, 30 Nov 2018 16:52:47 -0800 Message-Id: <20181201005254.139908-2-mka@chromium.org> X-Mailer: git-send-email 2.20.0.rc1.387.gf8505762e3-goog In-Reply-To: <20181201005254.139908-1-mka@chromium.org> References: <20181201005254.139908-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson --- Changes in V3: - added note that the ref clock is only required for new DTS files/entries Changes in v2: - add the ref clock for all PHYs, not only the 10nm one - updated commit message --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..9ae9469427207 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: From patchwork Sat Dec 1 00:52:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10707505 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3804617F0 for ; Sat, 1 Dec 2018 00:54:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 27BB026E76 for ; Sat, 1 Dec 2018 00:54:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C2E42F24F; Sat, 1 Dec 2018 00:54:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AB2AF2F24B for ; Sat, 1 Dec 2018 00:54:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726590AbeLAMFZ (ORCPT ); Sat, 1 Dec 2018 07:05:25 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:45339 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726637AbeLAMEi (ORCPT ); Sat, 1 Dec 2018 07:04:38 -0500 Received: by mail-pl1-f196.google.com with SMTP id a14so3576740plm.12 for ; Fri, 30 Nov 2018 16:53:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LI45bFlsD7zVrMZGddVOy1VzB8cFZD00h+Kdx5fCJbc=; b=FlXqIosx3pr6oWnUp5bveL5TXIetbdq47hmrILLuoI+4QMMbiUclRT/HVolYM3MMkP +FZC4TnTpDVpOBikmZaQ0NgJjjEfF8V7vXI0HkGzb4+Sbz4xieQF8uPbiO/V8pm4qaGT uV9VedCPw1fRQagZzSzAubwenbPhKyZDb+BtM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LI45bFlsD7zVrMZGddVOy1VzB8cFZD00h+Kdx5fCJbc=; b=ACt9Jmh8ZuYNVWYjvM93HRtqxmJgIOhoGbtl4MLzfVcOZOb6rWwoPjt5FdmjkWF8ll Wh3yhg3bWlevh/SQOjK6Qak5AdrCNUOL2VsoR33KfEIOEAHGZVlF1JRlOUnHT/btvUQM wNEgx636/j81v4UNorbecezN9gMoGW4QPeQ7eQZ2hwz4jC6NnO9VlzlmXXXI8TJWzQxy 0/Z8hzZCQPsF1rn2dBGiXv8ehnvYNDstVrggzHuBakC0geHnX0B7UGhSM6qj5YBIAtTp HL9xGOGROcTknihi6RzLoc397f/PwLTEafMTVuzCs3wHpzOqOUnHcvnDPMhRxGh4+4Rs l7yQ== X-Gm-Message-State: AA+aEWYm5ghTAYwqJogq6H2HB1wHZIMKuxQlVASHHgkLiYJpqWyeUNLk Np5PtPs9cVZxWG0YQ/ONtCQoVA== X-Google-Smtp-Source: AFSGD/VinoBrgeOVmxagIOQrCeQQ6pc5cJSTqRrEsx7rUxpce3XePKXfjHEwZTqXAfvpdy/AL5oKYA== X-Received: by 2002:a17:902:7b91:: with SMTP id w17mr7718839pll.111.1543625606947; Fri, 30 Nov 2018 16:53:26 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:b6af:f85:ed6c:ac6a]) by smtp.gmail.com with ESMTPSA id z8sm16518566pgz.53.2018.11.30.16.53.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 16:53:26 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v3 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT Date: Fri, 30 Nov 2018 16:52:48 -0800 Message-Id: <20181201005254.139908-3-mka@chromium.org> X-Mailer: git-send-email 2.20.0.rc1.387.gf8505762e3-goog In-Reply-To: <20181201005254.139908-1-mka@chromium.org> References: <20181201005254.139908-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Use default values if the ref clock is not specified. Signed-off-by: Matthias Kaehlcke --- Changes in v3: - use default name and rate if the ref clock is not specified in the DT - store vco_ref_clk_name instead of vco_ref_clk - fixed check for EPROBE_DEFER - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE Changes in v2: - patch added to the series --- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c index 49008451085b8..3af678d3317f6 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c @@ -47,9 +47,9 @@ #define NUM_PROVIDED_CLKS 2 -#define VCO_REF_CLK_RATE 27000000 -#define VCO_MIN_RATE 600000000 -#define VCO_MAX_RATE 1200000000 +#define VCO_REF_CLK_DEFAULT_RATE 27000000 +#define VCO_MIN_RATE 600000000 +#define VCO_MAX_RATE 1200000000 #define DSI_BYTE_PLL_CLK 0 #define DSI_PIXEL_PLL_CLK 1 @@ -75,6 +75,8 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio; + const char *vco_ref_clk_name; + /* custom byte clock divider */ struct clk_bytediv *bytediv; @@ -125,7 +127,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, DBG("rate=%lu, parent's=%lu", rate, parent_rate); temp = rate / 10; - val = VCO_REF_CLK_RATE / 10; + if (parent_rate) + val = parent_rate / 10; + else + val = VCO_REF_CLK_DEFAULT_RATE / 10; fb_divider = (temp * VCO_PREF_DIV_RATIO) / val; fb_divider = fb_divider / 2 - 1; pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, @@ -410,7 +415,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) { char *clk_name, *parent_name, *vco_name; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "pxo" }, + .parent_names = &pll_28nm->vco_ref_clk_name, .num_parents = 1, .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_28nm_vco, @@ -494,6 +499,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, { struct dsi_pll_28nm *pll_28nm; struct msm_dsi_pll *pll; + struct clk *vco_ref_clk; int ret; if (!pdev) @@ -506,6 +512,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, pll_28nm->pdev = pdev; pll_28nm->id = id + 1; + vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (!IS_ERR(vco_ref_clk)) { + pll_28nm->vco_ref_clk_name = __clk_get_name(vco_ref_clk); + } else { + ret = PTR_ERR(vco_ref_clk); + if (ret == -EPROBE_DEFER) + return ERR_PTR(ret); + + dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n"); + pll_28nm->vco_ref_clk_name = "pxo"; + } + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__); From patchwork Sat Dec 1 00:52:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10707501 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D888D14DB for ; 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Fri, 30 Nov 2018 16:53:28 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:b6af:f85:ed6c:ac6a]) by smtp.gmail.com with ESMTPSA id z8sm16518566pgz.53.2018.11.30.16.53.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 16:53:27 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v3 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT Date: Fri, 30 Nov 2018 16:52:49 -0800 Message-Id: <20181201005254.139908-4-mka@chromium.org> X-Mailer: git-send-email 2.20.0.rc1.387.gf8505762e3-goog In-Reply-To: <20181201005254.139908-1-mka@chromium.org> References: <20181201005254.139908-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate. Use default values if the ref clock is not specified. Signed-off-by: Matthias Kaehlcke --- Changes in v3: - use default name and rate if the ref clock is not specified in the DT - store vco_ref_clk_name instead of vco_ref_clk - dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to unsigned long - fixed check for EPROBE_DEFER - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE Changes in v2: - patch added to the series --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 35 ++++++++++++++++------ 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c index 26e3a01a99c2b..4a84c69ca0b2b 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c @@ -40,7 +40,7 @@ #define NUM_PROVIDED_CLKS 2 -#define VCO_REF_CLK_RATE 19200000 +#define VCO_REF_CLK_DEFAULT_RATE 19200000 #define VCO_MIN_RATE 350000000 #define VCO_MAX_RATE 750000000 @@ -81,6 +81,7 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio; + const char *vco_ref_clk_name; int vco_delay; /* private clocks: */ @@ -139,6 +140,8 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); struct device *dev = &pll_28nm->pdev->dev; void __iomem *base = pll_28nm->mmio; + unsigned long ref_clk_rate = parent_rate ? + parent_rate : VCO_REF_CLK_DEFAULT_RATE; unsigned long div_fbx1000, gen_vco_clk; u32 refclk_cfg, frac_n_mode, frac_n_value; u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; @@ -166,17 +169,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); - rem = rate % VCO_REF_CLK_RATE; + rem = rate % ref_clk_rate; if (rem) { refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; frac_n_mode = 1; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); + div_fbx1000 = rate / (ref_clk_rate / 500); + gen_vco_clk = div_fbx1000 * (ref_clk_rate / 500); } else { refclk_cfg = 0x0; frac_n_mode = 0; - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); + div_fbx1000 = rate / (ref_clk_rate / 1000); + gen_vco_clk = div_fbx1000 * (ref_clk_rate / 1000); } DBG("refclk_cfg = %d", refclk_cfg); @@ -265,7 +268,8 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, void __iomem *base = pll_28nm->mmio; u32 sdm0, doubler, sdm_byp_div; u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3; - u32 ref_clk = VCO_REF_CLK_RATE; + u32 ref_clk = parent_rate ? + parent_rate : VCO_REF_CLK_DEFAULT_RATE; unsigned long vco_rate; VERB("parent_rate=%lu", parent_rate); @@ -273,7 +277,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, /* Check to see if the ref clk doubler is enabled */ doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR; - ref_clk += (doubler * VCO_REF_CLK_RATE); + ref_clk += (doubler * ref_clk); /* see if it is integer mode or sdm mode */ sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); @@ -518,7 +522,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) { char clk_name[32], parent1[32], parent2[32], vco_name[32]; struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &pll_28nm->vco_ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -593,6 +597,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, { struct dsi_pll_28nm *pll_28nm; struct msm_dsi_pll *pll; + struct clk *vco_ref_clk; int ret; if (!pdev) @@ -605,6 +610,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev, pll_28nm->pdev = pdev; pll_28nm->id = id; + vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (!IS_ERR(vco_ref_clk)) { + pll_28nm->vco_ref_clk_name = __clk_get_name(vco_ref_clk); + } else { + ret = PTR_ERR(vco_ref_clk); + if (ret == -EPROBE_DEFER) + ERR_PTR(ret); + + dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n"); + pll_28nm->vco_ref_clk_name = "xo"; + } + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__); From patchwork Sat Dec 1 00:52:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10707499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C4EF16B1 for ; Sat, 1 Dec 2018 00:54:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D6C126E76 for ; Sat, 1 Dec 2018 00:54:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 40F462F24F; Sat, 1 Dec 2018 00:54:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CFE7C26E76 for ; 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Note: This change could break old out-of-tree DTS files that use the 14nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson --- Changes in v3: - fixed check for EPROBE_DEFER - added note to commit message about breaking old DTS files - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c index 71fe60e5f01f1..032bf3e8614bd 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c @@ -40,7 +40,6 @@ #define NUM_PROVIDED_CLKS 2 -#define VCO_REF_CLK_RATE 19200000 #define VCO_MIN_RATE 1300000000UL #define VCO_MAX_RATE 2600000000UL @@ -139,6 +138,7 @@ struct dsi_pll_14nm { /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; + struct clk *vco_ref_clk; u64 vco_current_rate; u64 vco_ref_clk_rate; @@ -591,7 +591,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, parent_rate); pll_14nm->vco_current_rate = rate; - pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; + pll_14nm->vco_ref_clk_rate = parent_rate; dsi_pll_14nm_input_init(pll_14nm); @@ -950,8 +950,9 @@ static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) { char clk_name[32], parent[32], vco_name[32]; + const char *ref_clk_name = __clk_get_name(pll_14nm->vco_ref_clk); struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -1065,6 +1066,15 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) pll_14nm->id = id; pll_14nm_list[id] = pll_14nm; + pll_14nm->vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(pll_14nm->vco_ref_clk)) { + ret = PTR_ERR(pll_14nm->vco_ref_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n", + ret); + return ERR_PTR(ret); + } + pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) { dev_err(&pdev->dev, "failed to map CMN PHY base\n"); From patchwork Sat Dec 1 00:52:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10707497 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3449816B1 for ; Sat, 1 Dec 2018 00:53:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 21B732F24B for ; Sat, 1 Dec 2018 00:53:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0F97726E76; Sat, 1 Dec 2018 00:53:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6F2326E76 for ; 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Note: This change could break old out-of-tree DTS files that use the 10nm PHY Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson --- Changes in v3: - fixed check for EPROBE_DEFER - added note to commit message about breaking old DTS files - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - remove anonymous array in clk_init_data assignment - log error code if devm_clk_get() fails - don't log devm_clk_get() failures for -EPROBE_DEFER - updated commit message --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 4c03f0b7343ed..2d23372acd20d 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -91,6 +91,7 @@ struct dsi_pll_10nm { void __iomem *phy_cmn_mmio; void __iomem *mmio; + struct clk *vco_ref_clk; u64 vco_ref_clk_rate; u64 vco_current_rate; @@ -629,8 +630,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) { char clk_name[32], parent[32], vco_name[32]; char parent2[32], parent3[32], parent4[32]; + const char *ref_clk_name = __clk_get_name(pll_10nm->vco_ref_clk); struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "xo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .name = vco_name, .flags = CLK_IGNORE_UNUSED, @@ -786,6 +788,15 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) pll_10nm->id = id; pll_10nm_list[id] = pll_10nm; + pll_10nm->vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(pll_10nm->vco_ref_clk)) { + ret = PTR_ERR(pll_10nm->vco_ref_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n", + ret); + return ERR_PTR(ret); + } + pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) { dev_err(&pdev->dev, "failed to map CMN PHY base\n"); From patchwork Sat Dec 1 00:52:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10707479 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B966417F0 for ; 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Fri, 30 Nov 2018 16:53:31 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:b6af:f85:ed6c:ac6a]) by smtp.gmail.com with ESMTPSA id z8sm16518566pgz.53.2018.11.30.16.53.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 16:53:30 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v3 6/8] arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY Date: Fri, 30 Nov 2018 16:52:52 -0800 Message-Id: <20181201005254.139908-7-mka@chromium.org> X-Mailer: git-send-email 2.20.0.rc1.387.gf8505762e3-goog In-Reply-To: <20181201005254.139908-1-mka@chromium.org> References: <20181201005254.139908-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a12..89f30f34ff896 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -959,8 +959,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&gcc GCC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "ref"; }; }; From patchwork Sat Dec 1 00:52:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10707481 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A857614DB for ; Sat, 1 Dec 2018 00:53:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B8482D4A4 for ; Sat, 1 Dec 2018 00:53:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F5802F272; Sat, 1 Dec 2018 00:53:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 336E82D4A4 for ; Sat, 1 Dec 2018 00:53:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726915AbeLAMEo (ORCPT ); Sat, 1 Dec 2018 07:04:44 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:39027 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726904AbeLAMEo (ORCPT ); Sat, 1 Dec 2018 07:04:44 -0500 Received: by mail-pf1-f195.google.com with SMTP id c72so3602538pfc.6 for ; Fri, 30 Nov 2018 16:53:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qaxLMCAB1G+6SIVdyeMOaOPPp9x4osIUQ9Kn7JRFmZI=; b=Q/xcXPh7HtVRsRfF60tUsgTlaB/NySnb/oSio3et9JwmfMahaIpV2jefGW4OYfP036 3Rmwj86AzagNMiC/P80DZnqYqtGEfKv5wWiijF5qIVeSVrZxMxfnaOa8OvMeJe18X+Gj gUW67Pddg+j4nEAMtGuOw277s6CLJHVaPvCc0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qaxLMCAB1G+6SIVdyeMOaOPPp9x4osIUQ9Kn7JRFmZI=; b=I/ELkrMH/WNlh6tCEyo6p+/Y5iZGISD0gjY1k3NkIDoHgLxmEhEwFwvTwNgpzGwzLm hM9lcePd3+jcyGzx0sk7nEhcwa9YJFtWeROvXJUU43OW7Z+7bK/NDG6YsV9Bq1NVWsX5 DGKF4ckuzRYkW9kLj9yO9r3vuJnsn1ABOrrgt2SxpWcPtZdH8JGjWLS20/JTIxI06q33 R5r6xPv9OwfnHQaqnhbZJt0uNhhTSca4UWtHX4fcKwNvpQfBZjBCR969iLqEHjQ7dFzF kWUxg2PXfk/bbMjkYsjLaH262DGJ+lDrUaFkbtltzBwO+cbFNVgGg/IYU8FGcZy15MIq pyOA== X-Gm-Message-State: AA+aEWZM1FNcVVKMgDVeOVnVyajAJNGlU0W64Y0IvBXTt80oNP8a+Wkm rDh3rt9NvYsIMeoqBdXq0ZG3nQ== X-Google-Smtp-Source: AFSGD/WiRSrQAqNF1UVr1P9XO3Qvv1iYVKYO7OPUUV20XeY34PK1I1nwuDc7XzDytoRb1vc+KJT96w== X-Received: by 2002:a63:4d:: with SMTP id 74mr6717605pga.248.1543625612386; Fri, 30 Nov 2018 16:53:32 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:b6af:f85:ed6c:ac6a]) by smtp.gmail.com with ESMTPSA id z8sm16518566pgz.53.2018.11.30.16.53.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 16:53:31 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v3 7/8] arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs Date: Fri, 30 Nov 2018 16:52:53 -0800 Message-Id: <20181201005254.139908-8-mka@chromium.org> X-Mailer: git-send-email 2.20.0.rc1.387.gf8505762e3-goog In-Reply-To: <20181201005254.139908-1-mka@chromium.org> References: <20181201005254.139908-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 10nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file" (https://patchwork.kernel.org/patch/10666253/) Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5728b4cfae269..cdb5a9bb23e69 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1372,8 +1372,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; }; dsi1: dsi@ae96000 { @@ -1434,8 +1435,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; }; }; From patchwork Sat Dec 1 00:52:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 10707483 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EDFDB17F0 for ; Sat, 1 Dec 2018 00:53:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1CE52F24F for ; Sat, 1 Dec 2018 00:53:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D5BAE2F272; Sat, 1 Dec 2018 00:53:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8BCA12F24B for ; Sat, 1 Dec 2018 00:53:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726920AbeLAMEp (ORCPT ); Sat, 1 Dec 2018 07:04:45 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:34138 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726918AbeLAMEp (ORCPT ); Sat, 1 Dec 2018 07:04:45 -0500 Received: by mail-pf1-f195.google.com with SMTP id h3so3614036pfg.1 for ; Fri, 30 Nov 2018 16:53:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HOtbCRNtEJv+CkEKZnSbEou+cNOE2l3Xvsy9ozDZFL0=; b=DJcxkDczA+pUB2+99vUBdnlYP/xoaCz9WwzaK7Yuy6mosbjalaRQnnPytfBPMbWPpT OkinmFXlGPn6lgRBg1K7LRA+kax5xuOFzGJOUYWMhHd+dOcdmmspBeMucHjfbvs7RuFR zd2hXXRVezh+0fz4S/E3TJpkSrMjQBSdTB6uA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HOtbCRNtEJv+CkEKZnSbEou+cNOE2l3Xvsy9ozDZFL0=; b=sN6mY57WeG13PEjYTnxjIHv2a9uqYQ1a2WPX377zRVteA3wzR2jBbRj0CbO1g4BnM3 q3vVwQpGFemRSIJB78FTtw5foMbPQs6bdPqYfdaSBeQjZc++FAXuE/wuqczk/H/w81Fu DYt0QdNnsLBxYdGAZMqNe/8gcYUgbFjxaOlY3ZpG1iaccskANyZJEkB6SOIn/kOg3Tsd FZXJMzCPzO0TicgL3TW7fCB05DDEgBE2YU0Ylyk3jO+CO1GQkgRFzbejm2TMWEY73SPr 8pyK6rdhLO9MA6R6AmOFUxHIsu0vDmeZr786pK4soAMhztbpVTU241JKGpYWD6aeCwUr 8oHw== X-Gm-Message-State: AA+aEWbfwTbvYyiVSCxR4llaPyMloPxrYKp1UvewHEj4c7nsaCnhQgCN pcJljBRFmk9WEMRiFppwHjplHA== X-Google-Smtp-Source: AFSGD/UFcEBtIhMQVEC6k2F+FwHoRgAzwLXNBFWplJNxIbq25v5VlOXRsnFzybqcAcAol+yhzauyeA== X-Received: by 2002:a62:9419:: with SMTP id m25mr8035769pfe.147.1543625613340; Fri, 30 Nov 2018 16:53:33 -0800 (PST) Received: from mka.mtv.corp.google.com ([2620:15c:202:1:b6af:f85:ed6c:ac6a]) by smtp.gmail.com with ESMTPSA id z8sm16518566pgz.53.2018.11.30.16.53.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 16:53:32 -0800 (PST) From: Matthias Kaehlcke To: Rob Clark , David Airlie , Rob Herring , Mark Rutland , Andy Gross , David Brown Cc: Archit Taneja , Sean Paul , Rajesh Yadav , Douglas Anderson , Stephen Boyd , Jeykumar Sankaran , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Kaehlcke Subject: [PATCH v3 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY Date: Fri, 30 Nov 2018 16:52:54 -0800 Message-Id: <20181201005254.139908-9-mka@chromium.org> X-Mailer: git-send-email 2.20.0.rc1.387.gf8505762e3-goog In-Reply-To: <20181201005254.139908-1-mka@chromium.org> References: <20181201005254.139908-1-mka@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- Changes in v3: - patch added to the series --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf4276101..d337ae9326cd8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1338,8 +1338,9 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk"; - clocks = <&mmcc DSI_M_AHB_CLK>; + clock-names = "iface_clk", "ref"; + clocks = <&mmcc DSI_M_AHB_CLK>, + <&xo_board>; };