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Thu, 17 Jun 2021 20:31:24 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Jun 2021 20:31:13 +0000 Received: from amhetre.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Jun 2021 20:31:10 +0000 From: Ashish Mhetre To: , , , CC: , , Subject: [Patch V2 1/2] iommu: Fix race condition during default domain allocation Date: Fri, 18 Jun 2021 02:00:36 +0530 Message-ID: <1623961837-12540-2-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1623961837-12540-1-git-send-email-amhetre@nvidia.com> References: <1623961837-12540-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9ff37436-257d-49c3-2613-08d931cee099 X-MS-TrafficTypeDiagnostic: DM6PR12MB3001: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1775; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 20:31:24.8144 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ff37436-257d-49c3-2613-08d931cee099 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3001 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210617_133127_907560_97DC69D0 X-CRM114-Status: GOOD ( 11.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Domain is getting created more than once during asynchronous multiple display heads(devices) probe. All the display heads share same SID and are expected to be in same domain. As iommu_alloc_default_domain() call is not protected, it ends up in creating two domains for two display devices which should ideally be in same domain. iommu_alloc_default_domain() checks whether domain is already allocated for given iommu group, but due to this race the check condition is failing and two different domains are getting created. This is leading to context faults when one device is accessing the IOVA mapped by other device. Fix this by protecting iommu_alloc_default_domain() call with group->mutex. With this fix serialization will happen only for the devices sharing same group. Also, only first device in group will hold the mutex till group is created and for rest of the devices it will just check for existing domain and then release the mutex. Signed-off-by: Ashish Mhetre --- Changes since V1: - Update the commit message per Will's suggestion drivers/iommu/iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 808ab70..2700500 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -273,7 +273,9 @@ int iommu_probe_device(struct device *dev) * support default domains, so the return value is not yet * checked. */ + mutex_lock(&group->mutex); iommu_alloc_default_domain(group, dev); + mutex_unlock(&group->mutex); if (group->default_domain) { ret = __iommu_attach_device(group->default_domain, dev); From patchwork Thu Jun 17 20:30:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashish Mhetre X-Patchwork-Id: 12329481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AAAAC2B9F4 for ; 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Thu, 17 Jun 2021 20:31:24 +0000 From: Ashish Mhetre To: , , , CC: , , Subject: [Patch V2 2/2] iommu/arm-smmu: Fix race condition during iommu_group creation Date: Fri, 18 Jun 2021 02:00:37 +0530 Message-ID: <1623961837-12540-3-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1623961837-12540-1-git-send-email-amhetre@nvidia.com> References: <1623961837-12540-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2564e868-5114-4be5-fcbb-08d931cee23f X-MS-TrafficTypeDiagnostic: DM6PR12MB3881: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:773; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eSDQWY2pwKSVr8P6Gz8zZLxlmBKp/OtLZGoHwEybFTdjMikMD60gAIuc/+nNivMDCbgn47i6edl3wTSOJcZlBAnHaFR3ede/jd+gPl8xF/dWxwArRY1uiRbMqzaByIjowpxE83q8lDdKd4TyPA0D4VeSSgKiKdxd/sqecIU3XRmiVY0AnQ0zM+zvohSgfUpgzqs0q7SvwZ6mSsqvCvbmUHS1ObMTLkXEJu48mRXcNzZtx/Y9ljowF9HNki2RKj3ZqD9h/TpNxzstDRN9pngpPcdvMpsRY9jwJTcxmBXKJ3zWFa63DJahfucxIIrEoZZSHjH4R9AZ9G28tHMTsOW8ax0LcHalTloXL2jTMrSnXkArxAohtjerj4iuNp/8iUUAKBueyffAY3/0uh/NOB41gvOEAeww0WGkpFY/Gjutj5VUgiiHALqyoT9S+N7BEGzXwWfnf9fgBlVP2zdMB4niUKBh2pF4Qw7pfIu2aALRxmKochkYLsUzWCJxO+Nf4zrv1puNXvlW9SNd7htRk2LpaRnNNOJPSzPrclE7bYN2utIhWt/E69ejNf+O5b6DuA25q4sB66yTPl6OgXZdUTpT/V9cjEM+AP8MX1tqsCnRbIu6tSCIzDKmT4JbW9WdgKrpbmfeq2g6SbVnbmWZtxKkPQ== X-Forefront-Antispam-Report: CIP:216.228.112.36; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid05.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(376002)(136003)(39860400002)(346002)(36840700001)(46966006)(7696005)(70586007)(70206006)(7636003)(6666004)(26005)(47076005)(478600001)(36860700001)(356005)(54906003)(5660300002)(8676002)(86362001)(82310400003)(4326008)(2906002)(36756003)(82740400003)(186003)(36906005)(110136005)(83380400001)(316002)(2616005)(6636002)(426003)(336012)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 20:31:27.6755 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2564e868-5114-4be5-fcbb-08d931cee23f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT062.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3881 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210617_133130_695902_A81B7E4E X-CRM114-Status: GOOD ( 12.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Krishna Reddy iommu_group is getting created more than once during asynchronous multiple display heads(devices) probe on Tegra194 SoC. All the display heads share same SID and are expected to be in same iommu_group. As arm_smmu_device_group() is not protecting group creation across devices, it is leading to multiple groups creation across devices with same SID and subsequent IOMMU faults. During race, the iommu_probe_device() call for two display devices is ending up in arm_smmu_device_group() twice and hence two groups are getting created. Ideally after group creation for first display device, same group should be used by second display device. This race is leading to context faults when one display device is accessing IOVA from other display device which shouldn't be the case for devices sharing same SID. Fix this by protecting group creation with smmu->stream_map_mutex. Signed-off-by: Krishna Reddy --- Changes since V1: - Update the commit message per Will's suggestion drivers/iommu/arm/arm-smmu/arm-smmu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 6f72c4d..21af179 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1458,6 +1458,7 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) struct iommu_group *group = NULL; int i, idx; + mutex_lock(&smmu->stream_map_mutex); for_each_cfg_sme(cfg, fwspec, i, idx) { if (group && smmu->s2crs[idx].group && group != smmu->s2crs[idx].group) @@ -1466,8 +1467,10 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) group = smmu->s2crs[idx].group; } - if (group) + if (group) { + mutex_unlock(&smmu->stream_map_mutex); return iommu_group_ref_get(group); + } if (dev_is_pci(dev)) group = pci_device_group(dev); @@ -1481,6 +1484,7 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) for_each_cfg_sme(cfg, fwspec, i, idx) smmu->s2crs[idx].group = group; + mutex_unlock(&smmu->stream_map_mutex); return group; }