From patchwork Fri Jun 18 09:58:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12330833 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3778C48BE8 for ; Fri, 18 Jun 2021 09:58:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CD78360C3E for ; Fri, 18 Jun 2021 09:58:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233139AbhFRKAo (ORCPT ); Fri, 18 Jun 2021 06:00:44 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:34971 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232690AbhFRKAm (ORCPT ); Fri, 18 Jun 2021 06:00:42 -0400 X-IronPort-AV: E=Sophos;i="5.83,283,1616425200"; d="scan'208";a="84769008" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 18 Jun 2021 18:58:30 +0900 Received: from localhost.localdomain (unknown [10.226.93.115]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0ED49401BC11; Fri, 18 Jun 2021 18:58:28 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Lad Prabhakar , devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: clk: r9a07g044-cpg: Update clock definitions Date: Fri, 18 Jun 2021 10:58:17 +0100 Message-Id: <20210618095823.19885-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> References: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Update clock definitions as per the RZG2L_clock_list(Rev.02) manual. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- include/dt-bindings/clock/r9a07g044-cpg.h | 153 ++++++++++++++-------- 1 file changed, 100 insertions(+), 53 deletions(-) diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h index 1d8986563fc5..7e0127646973 100644 --- a/include/dt-bindings/clock/r9a07g044-cpg.h +++ b/include/dt-bindings/clock/r9a07g044-cpg.h @@ -32,58 +32,105 @@ #define R9A07G044_OSCCLK 21 /* R9A07G044 Module Clocks */ -#define R9A07G044_CLK_GIC600 0 -#define R9A07G044_CLK_IA55 1 -#define R9A07G044_CLK_SYC 2 -#define R9A07G044_CLK_DMAC 3 -#define R9A07G044_CLK_SYSC 4 -#define R9A07G044_CLK_MTU 5 -#define R9A07G044_CLK_GPT 6 -#define R9A07G044_CLK_ETH0 7 -#define R9A07G044_CLK_ETH1 8 -#define R9A07G044_CLK_I2C0 9 -#define R9A07G044_CLK_I2C1 10 -#define R9A07G044_CLK_I2C2 11 -#define R9A07G044_CLK_I2C3 12 -#define R9A07G044_CLK_SCIF0 13 -#define R9A07G044_CLK_SCIF1 14 -#define R9A07G044_CLK_SCIF2 15 -#define R9A07G044_CLK_SCIF3 16 -#define R9A07G044_CLK_SCIF4 17 -#define R9A07G044_CLK_SCI0 18 -#define R9A07G044_CLK_SCI1 19 -#define R9A07G044_CLK_GPIO 20 -#define R9A07G044_CLK_SDHI0 21 -#define R9A07G044_CLK_SDHI1 22 -#define R9A07G044_CLK_USB0 23 -#define R9A07G044_CLK_USB1 24 -#define R9A07G044_CLK_CANFD 25 -#define R9A07G044_CLK_SSI0 26 -#define R9A07G044_CLK_SSI1 27 -#define R9A07G044_CLK_SSI2 28 -#define R9A07G044_CLK_SSI3 29 -#define R9A07G044_CLK_MHU 30 -#define R9A07G044_CLK_OSTM0 31 -#define R9A07G044_CLK_OSTM1 32 -#define R9A07G044_CLK_OSTM2 33 -#define R9A07G044_CLK_WDT0 34 -#define R9A07G044_CLK_WDT1 35 -#define R9A07G044_CLK_WDT2 36 -#define R9A07G044_CLK_WDT_PON 37 -#define R9A07G044_CLK_GPU 38 -#define R9A07G044_CLK_ISU 39 -#define R9A07G044_CLK_H264 40 -#define R9A07G044_CLK_CRU 41 -#define R9A07G044_CLK_MIPI_DSI 42 -#define R9A07G044_CLK_LCDC 43 -#define R9A07G044_CLK_SRC 44 -#define R9A07G044_CLK_RSPI0 45 -#define R9A07G044_CLK_RSPI1 46 -#define R9A07G044_CLK_RSPI2 47 -#define R9A07G044_CLK_ADC 48 -#define R9A07G044_CLK_TSU_PCLK 49 -#define R9A07G044_CLK_SPI 50 -#define R9A07G044_CLK_MIPI_DSI_V 51 -#define R9A07G044_CLK_MIPI_DSI_PIN 52 +#define R9A07G044_CA55_SCLK 0 +#define R9A07G044_CA55_PCLK 1 +#define R9A07G044_CA55_ATCLK 2 +#define R9A07G044_CA55_GICCLK 3 +#define R9A07G044_CA55_PERICLK 4 +#define R9A07G044_CA55_ACLK 5 +#define R9A07G044_CA55_TSCLK 6 +#define R9A07G044_GIC600_GICCLK 7 +#define R9A07G044_IA55_CLK 8 +#define R9A07G044_IA55_PCLK 9 +#define R9A07G044_MHU_PCLK 10 +#define R9A07G044_SYC_CNT_CLK 11 +#define R9A07G044_DMAC_ACLK 12 +#define R9A07G044_DMAC_PCLK 13 +#define R9A07G044_OSTM0_PCLK 14 +#define R9A07G044_OSTM1_PCLK 15 +#define R9A07G044_OSTM2_PCLK 16 +#define R9A07G044_MTU_X_MCK_MTU3 17 +#define R9A07G044_POE3_CLKM_POE 18 +#define R9A07G044_GPT_PCLK 19 +#define R9A07G044_POEG_A_CLKP 20 +#define R9A07G044_POEG_B_CLKP 21 +#define R9A07G044_POEG_C_CLKP 22 +#define R9A07G044_POEG_D_CLKP 23 +#define R9A07G044_WDT0_PCLK 24 +#define R9A07G044_WDT0_CLK 25 +#define R9A07G044_WDT1_PCLK 26 +#define R9A07G044_WDT1_CLK 27 +#define R9A07G044_WDT2_PCLK 28 +#define R9A07G044_WDT2_CLK 29 +#define R9A07G044_SPI_CLK2 30 +#define R9A07G044_SPI_CLK 31 +#define R9A07G044_SDHI0_IMCLK 32 +#define R9A07G044_SDHI0_IMCLK2 33 +#define R9A07G044_SDHI0_CLK_HS 34 +#define R9A07G044_SDHI0_ACLK 35 +#define R9A07G044_SDHI1_IMCLK 36 +#define R9A07G044_SDHI1_IMCLK2 37 +#define R9A07G044_SDHI1_CLK_HS 38 +#define R9A07G044_SDHI1_ACLK 39 +#define R9A07G044_GPU_CLK 40 +#define R9A07G044_GPU_AXI_CLK 41 +#define R9A07G044_GPU_ACE_CLK 42 +#define R9A07G044_ISU_ACLK 43 +#define R9A07G044_ISU_PCLK 44 +#define R9A07G044_H264_CLK_A 45 +#define R9A07G044_H264_CLK_P 46 +#define R9A07G044_CRU_SYSCLK 47 +#define R9A07G044_CRU_VCLK 48 +#define R9A07G044_CRU_PCLK 49 +#define R9A07G044_CRU_ACLK 50 +#define R9A07G044_MIPI_DSI_PLLCLK 51 +#define R9A07G044_MIPI_DSI_SYSCLK 52 +#define R9A07G044_MIPI_DSI_ACLK 53 +#define R9A07G044_MIPI_DSI_PCLK 54 +#define R9A07G044_MIPI_DSI_VCLK 55 +#define R9A07G044_MIPI_DSI_LPCLK 56 +#define R9A07G044_LCDC_CLK_A 57 +#define R9A07G044_LCDC_CLK_P 58 +#define R9A07G044_LCDC_CLK_D 59 +#define R9A07G044_SSI0_PCLK2 60 +#define R9A07G044_SSI0_PCLK_SFR 61 +#define R9A07G044_SSI1_PCLK2 62 +#define R9A07G044_SSI1_PCLK_SFR 63 +#define R9A07G044_SSI2_PCLK2 64 +#define R9A07G044_SSI2_PCLK_SFR 65 +#define R9A07G044_SSI3_PCLK2 66 +#define R9A07G044_SSI3_PCLK_SFR 67 +#define R9A07G044_SRC_CLKP 68 +#define R9A07G044_USB_U2H0_HCLK 69 +#define R9A07G044_USB_U2H1_HCLK 70 +#define R9A07G044_USB_U2P_EXR_CPUCLK 71 +#define R9A07G044_USB_PCLK 72 +#define R9A07G044_USB_SCLK 73 +#define R9A07G044_ETH0_CLK_AXI 74 +#define R9A07G044_ETH0_CLK_CHI 75 +#define R9A07G044_ETH0_REFCLK 76 +#define R9A07G044_ETH1_CLK_AXI 77 +#define R9A07G044_ETH1_CLK_CHI 78 +#define R9A07G044_ETH1_REFCLK 79 +#define R9A07G044_I2C0_PCLK 80 +#define R9A07G044_I2C1_PCLK 81 +#define R9A07G044_I2C2_PCLK 82 +#define R9A07G044_I2C3_PCLK 83 +#define R9A07G044_SCIF0_CLK_PCK 84 +#define R9A07G044_SCIF1_CLK_PCK 85 +#define R9A07G044_SCIF2_CLK_PCK 86 +#define R9A07G044_SCIF3_CLK_PCK 87 +#define R9A07G044_SCIF4_CLK_PCK 88 +#define R9A07G044_SCI0_CLKP 89 +#define R9A07G044_SCI1_CLKP 90 +#define R9A07G044_IRDA_CLKP 91 +#define R9A07G044_RSPI0_CLKB 92 +#define R9A07G044_RSPI1_CLKB 93 +#define R9A07G044_RSPI2_CLKB 94 +#define R9A07G044_CANFD_PCLK 95 +#define R9A07G044_GPIO_HCLK 96 +#define R9A07G044_ADC_ADCLK 97 +#define R9A07G044_ADC_PCLK 98 +#define R9A07G044_TSU_PCLK 99 #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ From patchwork Fri Jun 18 09:58:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12330835 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23504C49EA5 for ; Fri, 18 Jun 2021 09:58:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B18C60C3E for ; Fri, 18 Jun 2021 09:58:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233150AbhFRKAp (ORCPT ); Fri, 18 Jun 2021 06:00:45 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:11947 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233098AbhFRKAn (ORCPT ); Fri, 18 Jun 2021 06:00:43 -0400 X-IronPort-AV: E=Sophos;i="5.83,283,1616425200"; d="scan'208";a="84769017" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 18 Jun 2021 18:58:33 +0900 Received: from localhost.localdomain (unknown [10.226.93.115]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 681F8401BC11; Fri, 18 Jun 2021 18:58:31 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 2/7] drivers: clk: renesas: renesas-rzg2l-cpg: Add multi clock PM support Date: Fri, 18 Jun 2021 10:58:18 +0100 Message-Id: <20210618095823.19885-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> References: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add multi clock PM support for cpg driver. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/renesas-rzg2l-cpg.c | 51 ++++++++++++++----------- 1 file changed, 29 insertions(+), 22 deletions(-) diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.c b/drivers/clk/renesas/renesas-rzg2l-cpg.c index ef308cb2368f..f32a270319e5 100644 --- a/drivers/clk/renesas/renesas-rzg2l-cpg.c +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c @@ -594,42 +594,49 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device { struct device_node *np = dev->of_node; struct of_phandle_args clkspec; + bool once = true; struct clk *clk; int error; int i = 0; while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec)) { - if (rzg2l_cpg_is_pm_clk(&clkspec)) - goto found; - - of_node_put(clkspec.np); + if (rzg2l_cpg_is_pm_clk(&clkspec)) { + if (once) { + once = false; + error = pm_clk_create(dev); + if (error) { + of_node_put(clkspec.np); + goto err; + } + } + clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); + if (IS_ERR(clk)) { + error = PTR_ERR(clk); + goto fail_destroy; + } + + error = pm_clk_add_clk(dev, clk); + if (error) { + dev_err(dev, "pm_clk_add_clk failed %d\n", + error); + goto fail_put; + } + } else { + of_node_put(clkspec.np); + } i++; } return 0; -found: - clk = of_clk_get_from_provider(&clkspec); - of_node_put(clkspec.np); - - if (IS_ERR(clk)) - return PTR_ERR(clk); - - error = pm_clk_create(dev); - if (error) - goto fail_put; - - error = pm_clk_add_clk(dev, clk); - if (error) - goto fail_destroy; - - return 0; +fail_put: + clk_put(clk); fail_destroy: pm_clk_destroy(dev); -fail_put: - clk_put(clk); +err: return error; } From patchwork Fri Jun 18 09:58:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12330837 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4013FC49EAB for ; Fri, 18 Jun 2021 09:58:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2561F613D6 for ; Fri, 18 Jun 2021 09:58:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233217AbhFRKAr (ORCPT ); Fri, 18 Jun 2021 06:00:47 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:12869 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233167AbhFRKAp (ORCPT ); Fri, 18 Jun 2021 06:00:45 -0400 X-IronPort-AV: E=Sophos;i="5.83,283,1616425200"; d="scan'208";a="84638752" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 18 Jun 2021 18:58:35 +0900 Received: from localhost.localdomain (unknown [10.226.93.115]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D80FC4018222; Fri, 18 Jun 2021 18:58:33 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 3/7] drivers: clk: renesas: r9a07g044-cpg: Update {GIC,IA55,SCIF} clock entries Date: Fri, 18 Jun 2021 10:58:19 +0100 Message-Id: <20210618095823.19885-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> References: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Update {GIC,IA55,SCIF} clock entries to CPG driver to match with RZ/G2L clock list hardware manual(Rev0.2). Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- drivers/clk/renesas/r9a07g044-cpg.c | 37 +++++++++++++++++-------- drivers/clk/renesas/renesas-rzg2l-cpg.h | 1 + 2 files changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 50b5269586a4..5c215b6c06e0 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -32,6 +32,7 @@ enum clk_ids { CLK_PLL3_DIV2, CLK_PLL3_DIV4, CLK_PLL3_DIV8, + CLK_PLL3_DIV16, CLK_PLL4, CLK_PLL5, CLK_PLL5_DIV2, @@ -42,6 +43,14 @@ enum clk_ids { }; /* Divider tables */ +static const struct clk_div_table dtable_3a[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {4, 32}, +}; + static const struct clk_div_table dtable_3b[] = { {0, 1}, {1, 2}, @@ -68,6 +77,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8), + DEF_FIXED(".pll3_div16", CLK_PLL3_DIV16, CLK_PLL3, 1, 16), /* Core output clk */ DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), @@ -76,37 +86,42 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8, DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV16, + DIVPL3A, dtable_3a, CLK_DIVIDER_HIWORD_MASK), }; static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { - DEF_MOD("gic", R9A07G044_CLK_GIC600, + DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, 0x514, BIT(0), (BIT(0) | BIT(1))), - DEF_MOD("ia55", R9A07G044_CLK_IA55, + DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, + R9A07G044_CLK_P2, + 0x518, BIT(0), BIT(0)), + DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, - 0x518, (BIT(0) | BIT(1)), BIT(0)), - DEF_MOD("scif0", R9A07G044_CLK_SCIF0, + 0x518, BIT(1), BIT(0)), + DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, 0x584, BIT(0), BIT(0)), - DEF_MOD("scif1", R9A07G044_CLK_SCIF1, + DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, 0x584, BIT(1), BIT(1)), - DEF_MOD("scif2", R9A07G044_CLK_SCIF2, + DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, 0x584, BIT(2), BIT(2)), - DEF_MOD("scif3", R9A07G044_CLK_SCIF3, + DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, 0x584, BIT(3), BIT(3)), - DEF_MOD("scif4", R9A07G044_CLK_SCIF4, + DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, 0x584, BIT(4), BIT(4)), - DEF_MOD("sci0", R9A07G044_CLK_SCI0, + DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, 0x588, BIT(0), BIT(0)), }; static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { - MOD_CLK_BASE + R9A07G044_CLK_GIC600, + MOD_CLK_BASE + R9A07G044_GIC600_GICCLK, }; const struct rzg2l_cpg_info r9a07g044_cpg_info = { @@ -123,5 +138,5 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { /* Module Clocks */ .mod_clks = r9a07g044_mod_clks, .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks), - .num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1, + .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, }; diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.h b/drivers/clk/renesas/renesas-rzg2l-cpg.h index 3948bdd8afc9..a6a3bade1985 100644 --- a/drivers/clk/renesas/renesas-rzg2l-cpg.h +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h @@ -21,6 +21,7 @@ #define DDIV_PACK(offset, bitpos, size) \ (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) +#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) /** From patchwork Fri Jun 18 09:58:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12330839 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A847C48BDF for ; Fri, 18 Jun 2021 09:58:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1468861369 for ; Fri, 18 Jun 2021 09:58:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233193AbhFRKAu (ORCPT ); Fri, 18 Jun 2021 06:00:50 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:32511 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233187AbhFRKAr (ORCPT ); Fri, 18 Jun 2021 06:00:47 -0400 X-IronPort-AV: E=Sophos;i="5.83,283,1616425200"; d="scan'208";a="84638764" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 18 Jun 2021 18:58:38 +0900 Received: from localhost.localdomain (unknown [10.226.93.115]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 5CB9C401BEE1; Fri, 18 Jun 2021 18:58:36 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Lad Prabhakar , devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 4/7] arm64: dts: renesas: r9a07g044: Update SCIF0 clock Date: Fri, 18 Jun 2021 10:58:20 +0100 Message-Id: <20210618095823.19885-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> References: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Update SCIF0 clock index in SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 476ee9a69065..544f040a4e1d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -82,10 +82,10 @@ ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>; + clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; clock-names = "fck"; power-domains = <&cpg>; - resets = <&cpg R9A07G044_CLK_SCIF0>; + resets = <&cpg R9A07G044_SCIF0_CLK_PCK>; status = "disabled"; }; From patchwork Fri Jun 18 09:58:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12330841 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 855A3C49EA2 for ; Fri, 18 Jun 2021 09:58:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FCC7613CB for ; Fri, 18 Jun 2021 09:58:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233242AbhFRKAv (ORCPT ); Fri, 18 Jun 2021 06:00:51 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:12869 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233219AbhFRKAu (ORCPT ); Fri, 18 Jun 2021 06:00:50 -0400 X-IronPort-AV: E=Sophos;i="5.83,283,1616425200"; d="scan'208";a="84638769" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 18 Jun 2021 18:58:40 +0900 Received: from localhost.localdomain (unknown [10.226.93.115]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D2459401A453; Fri, 18 Jun 2021 18:58:38 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 5/7] drivers: clk: renesas: r9a07g044-cpg: Add I2C Clocks Date: Fri, 18 Jun 2021 10:58:21 +0100 Message-Id: <20210618095823.19885-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> References: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add I2C{0,1,2.3} clock entries. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- drivers/clk/renesas/r9a07g044-cpg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 5c215b6c06e0..c7be8ede494d 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -100,6 +100,18 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, 0x518, BIT(1), BIT(0)), + DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, + R9A07G044_CLK_P0, + 0x580, BIT(0), BIT(0)), + DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, + R9A07G044_CLK_P0, + 0x580, BIT(1), BIT(1)), + DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, + R9A07G044_CLK_P0, + 0x580, BIT(2), BIT(2)), + DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, + R9A07G044_CLK_P0, + 0x580, BIT(3), BIT(3)), DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, 0x584, BIT(0), BIT(0)), From patchwork Fri Jun 18 09:58:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12330843 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D428C49361 for ; Fri, 18 Jun 2021 09:58:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C1BF613CB for ; Fri, 18 Jun 2021 09:58:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233184AbhFRKAx (ORCPT ); Fri, 18 Jun 2021 06:00:53 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:33508 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232796AbhFRKAx (ORCPT ); Fri, 18 Jun 2021 06:00:53 -0400 X-IronPort-AV: E=Sophos;i="5.83,283,1616425200"; d="scan'208";a="84638776" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 18 Jun 2021 18:58:43 +0900 Received: from localhost.localdomain (unknown [10.226.93.115]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4E09A401BC16; Fri, 18 Jun 2021 18:58:41 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 6/7] drivers: clk: renesas: r9a07g044-cpg: Add DMAC clocks Date: Fri, 18 Jun 2021 10:58:22 +0100 Message-Id: <20210618095823.19885-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> References: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add DMAC clock entry in CPG driver. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- drivers/clk/renesas/r9a07g044-cpg.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index c7be8ede494d..bdede1d28086 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -37,6 +37,7 @@ enum clk_ids { CLK_PLL5, CLK_PLL5_DIV2, CLK_PLL6, + CLK_P1_DIV2, /* Module Clocks */ MOD_CLK_BASE, @@ -86,6 +87,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8, DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV16, DIVPL3A, dtable_3a, CLK_DIVIDER_HIWORD_MASK), }; @@ -100,6 +102,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, 0x518, BIT(1), BIT(0)), + DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, + R9A07G044_CLK_P1, + 0x52c, BIT(0), BIT(0)), + DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, + CLK_P1_DIV2, + 0x52c, BIT(1), BIT(1)), DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, 0x580, BIT(0), BIT(0)), From patchwork Fri Jun 18 09:58:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12330845 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC3CAC49EA3 for ; Fri, 18 Jun 2021 09:58:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9774860C3E for ; Fri, 18 Jun 2021 09:58:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233278AbhFRKA4 (ORCPT ); Fri, 18 Jun 2021 06:00:56 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:33508 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233213AbhFRKAz (ORCPT ); Fri, 18 Jun 2021 06:00:55 -0400 X-IronPort-AV: E=Sophos;i="5.83,283,1616425200"; d="scan'208";a="84638784" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 18 Jun 2021 18:58:45 +0900 Received: from localhost.localdomain (unknown [10.226.93.115]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id BAA74401A453; Fri, 18 Jun 2021 18:58:43 +0900 (JST) From: Biju Das To: Rob Herring Cc: Biju Das , Lad Prabhakar , devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: renesas: r9a07g044: Add I2C nodes Date: Fri, 18 Jun 2021 10:58:23 +0100 Message-Id: <20210618095823.19885-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> References: <20210618095823.19885-1-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add I2C{0,1,2,3} nodes to RZ/G2 (R9A07G044) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 544f040a4e1d..b573ce88f4da 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -89,6 +89,86 @@ status = "disabled"; }; + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; + reg = <0 0x10058000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G044_I2C0_PCLK>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; + reg = <0 0x10058400 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G044_I2C1_PCLK>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G044_I2C2_PCLK>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c3: i2c@10058c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; + reg = <0 0x10058c00 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G044_I2C3_PCLK>; + power-domains = <&cpg>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>;