From patchwork Mon Jun 21 07:06:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Hundeb=C3=B8ll?= X-Patchwork-Id: 12333901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA25DC49EA2 for ; Mon, 21 Jun 2021 07:06:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D6F8661156 for ; Mon, 21 Jun 2021 07:06:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230311AbhFUHIz (ORCPT ); Mon, 21 Jun 2021 03:08:55 -0400 Received: from first.geanix.com ([116.203.34.67]:54084 "EHLO first.geanix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229583AbhFUHIq (ORCPT ); Mon, 21 Jun 2021 03:08:46 -0400 Received: from 185.17.218.86 (unknown [185.17.218.86]) by first.geanix.com (Postfix) with ESMTPSA id 178754C3BB8; Mon, 21 Jun 2021 07:06:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=silicom.dk; s=first; t=1624259190; bh=e3h4F5C3FTTVvZujv41AeP7Sff71JQ2Cctc9Xe9XIFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=K+fM+uVUJKzZqm93n6/x114b/dsA0eaUMioKpKEdZvL0JHN4fMDBi3REyC5Zq7GqZ v4GylqkFXGTsKjVPImUInd66OLG2qbTp80wOIdTtp/FwMi+IMktUkLfcoy2ZIgumN4 0pwlvxxhYnDUTeOARSOwDpeKzB1AwDtVHA2M5Oh94MR6yUPNFY8YXoGbctKqLWviHz JWNZtEiyBKhIYW8EPXQc/Tdn7inaHWkjeXY4usy9k4LwOd2IkBPjrmnn6taf86kp3a A/w/AQsb3fVLb+uDJ4Mech467WmpGANOU+JeCoGbudw6oUyF3tsLkc9/WAlZDGfS/J tcwOpTRQg85mQ== From: =?utf-8?q?Martin_Hundeb=C3=B8ll?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , Jean Delvare , Guenter Roeck , Lee Jones , Mark Brown Cc: =?utf-8?q?Martin_Hundeb=C3=B8ll?= , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org, =?utf-8?q?Martin_Hu?= =?utf-8?q?ndeb=C3=B8ll?= Subject: [PATCH 1/4] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards Date: Mon, 21 Jun 2021 09:06:18 +0200 Message-Id: <20210621070621.431482-2-mhu@silicom.dk> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210621070621.431482-1-mhu@silicom.dk> References: <20210621070621.431482-1-mhu@silicom.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This adds the approved PCI Express Device IDs for the Silicom PAC N5010 and N5011 cards. Signed-off-by: Martin Hundebøll Acked-by: Wu Hao --- drivers/fpga/dfl-pci.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index b44523ea8c91..4d68719e608f 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -74,6 +74,9 @@ static void cci_pci_free_irq(struct pci_dev *pcidev) #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4 #define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30 #define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B +#define PCIE_DEVICE_ID_SILICOM_PAC_N5010 0x1000 +#define PCIE_DEVICE_ID_SILICOM_PAC_N5011 0x1001 + /* VF Device */ #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1 @@ -90,6 +93,8 @@ static struct pci_device_id cci_pcie_id_tbl[] = { {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),}, {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),}, {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),}, + {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),}, + {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),}, {0,} }; MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl); From patchwork Mon Jun 21 07:06:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Hundeb=C3=B8ll?= X-Patchwork-Id: 12333897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5469C49EA7 for ; Mon, 21 Jun 2021 07:06:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9C512611C0 for ; Mon, 21 Jun 2021 07:06:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230161AbhFUHIw (ORCPT ); Mon, 21 Jun 2021 03:08:52 -0400 Received: from first.geanix.com ([116.203.34.67]:54102 "EHLO first.geanix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229804AbhFUHIs (ORCPT ); Mon, 21 Jun 2021 03:08:48 -0400 Received: from 185.17.218.86 (unknown [185.17.218.86]) by first.geanix.com (Postfix) with ESMTPSA id DD7B34C3BB7; Mon, 21 Jun 2021 07:06:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=silicom.dk; s=first; t=1624259192; bh=EvJBXmKpD9XzIULYTA8pUFWOTf4A6/iiDUj0U5hdSvc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=a4r9ikf51N/FMGhXyLfg7J0FfBqo+3CMlW6iDiIN/fAshKci3ArsTgT9y/Qd3PXm7 V/dfn6TTtmDz2B3k/hgvHtPuzD+Df6JyDuYZ521ki/QlGLzKaovoSK47Bd+NNIjqtr G3/bKFlmtA4izfChXzQjAxKIlOs8tmP7GK1EWifItkLrXs4y7VaAcH+wwSpKQo4nT/ DPWx7yI6UdMX0dkILu/M0tfMXJNrvQJxIaLcoKoDYUbs1rdfkiDRTghHzNObOiKJZr ua7416nnJYNCQ6aUI21EbUmdJr1T7SaqWlwfVNMIfW9QhXvrYr8YfDeS7FEoAlc+zk 1mBerE5LRxKwg== From: =?utf-8?q?Martin_Hundeb=C3=B8ll?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , Jean Delvare , Guenter Roeck , Lee Jones , Mark Brown Cc: =?utf-8?q?Martin_Hundeb=C3=B8ll?= , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org, Debarati Biswas , Russ Weight , =?utf-8?q?Martin_Hundeb=C3=B8ll?= Subject: [PATCH 2/4] fpga: dfl: Move DFH header register macros to linux/dfl.h Date: Mon, 21 Jun 2021 09:06:19 +0200 Message-Id: <20210621070621.431482-3-mhu@silicom.dk> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210621070621.431482-1-mhu@silicom.dk> References: <20210621070621.431482-1-mhu@silicom.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Debarati Biswas Device Feature List (DFL) drivers may be defined in subdirectories other than drivers/fpga, and each DFL driver should have access to the Device Feature Header (DFH) register, which contains revision and type information. This change moves the macros specific to the DFH register from drivers/fpga/dfl.h to include/linux/dfl.h. Signed-off-by: Debarati Biswas Signed-off-by: Russ Weight Signed-off-by: Martin Hundebøll Reported-by: kernel test robot --- drivers/fpga/dfl.h | 48 +---------------------------------------- include/linux/dfl.h | 52 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 47 deletions(-) diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 2b82c96ba56c..6ed0353e9a99 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -53,32 +54,6 @@ #define PORT_FEATURE_ID_UINT 0x12 #define PORT_FEATURE_ID_STP 0x13 -/* - * Device Feature Header Register Set - * - * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. - * For AFUs, they have DFH + GUID as common header registers. - * For private features, they only have DFH register as common header. - */ -#define DFH 0x0 -#define GUID_L 0x8 -#define GUID_H 0x10 -#define NEXT_AFU 0x18 - -#define DFH_SIZE 0x8 - -/* Device Feature Header Register Bitfield */ -#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ -#define DFH_ID_FIU_FME 0 -#define DFH_ID_FIU_PORT 1 -#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ -#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ -#define DFH_EOL BIT_ULL(40) /* End of list */ -#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ -#define DFH_TYPE_AFU 1 -#define DFH_TYPE_PRIVATE 3 -#define DFH_TYPE_FIU 4 - /* Next AFU Register Bitfield */ #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ @@ -403,27 +378,6 @@ struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata) return pdata->dev->dev.parent->parent; } -static inline bool dfl_feature_is_fme(void __iomem *base) -{ - u64 v = readq(base + DFH); - - return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && - (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME); -} - -static inline bool dfl_feature_is_port(void __iomem *base) -{ - u64 v = readq(base + DFH); - - return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && - (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT); -} - -static inline u8 dfl_feature_revision(void __iomem *base) -{ - return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH)); -} - /** * struct dfl_fpga_enum_info - DFL FPGA enumeration information * diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 6cc10982351a..1cd86b2e7cb1 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -8,7 +8,9 @@ #ifndef __LINUX_DFL_H #define __LINUX_DFL_H +#include #include +#include #include /** @@ -83,4 +85,54 @@ void dfl_driver_unregister(struct dfl_driver *dfl_drv); module_driver(__dfl_driver, dfl_driver_register, \ dfl_driver_unregister) +/* + * Device Feature Header Register Set + * + * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. + * For AFUs, they have DFH + GUID as common header registers. + * For private features, they only have DFH register as common header. + */ +#define DFH 0x0 +#define GUID_L 0x8 +#define GUID_H 0x10 +#define NEXT_AFU 0x18 + +#define DFH_SIZE 0x8 + +/* Device Feature Header Register Bitfield */ +#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ +#define DFH_ID_FIU_FME 0 +#define DFH_ID_FIU_PORT 1 +#define DFH_REVISION GENMASK_ULL(15, 12) +#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ +#define DFH_EOL BIT_ULL(40) /* End of list */ +#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ +#define DFH_TYPE_AFU 1 +#define DFH_TYPE_PRIVATE 3 +#define DFH_TYPE_FIU 4 + +/* Function to read from DFH and check if the Feature type is FME */ +static inline bool dfl_feature_is_fme(void __iomem *base) +{ + u64 v = readq(base + DFH); + + return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && + (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME); +} + +/* Function to read from DFH and check if the Feature type is port*/ +static inline bool dfl_feature_is_port(void __iomem *base) +{ + u64 v = readq(base + DFH); + + return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && + (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT); +} + +/* Function to read feature revision from DFH */ +static inline u8 dfl_feature_revision(void __iomem *base) +{ + return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH)); +} + #endif /* __LINUX_DFL_H */ From patchwork Mon Jun 21 07:06:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Hundeb=C3=B8ll?= X-Patchwork-Id: 12333899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F898C49EAF for ; Mon, 21 Jun 2021 07:06:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47AEC611C1 for ; Mon, 21 Jun 2021 07:06:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230306AbhFUHIy (ORCPT ); Mon, 21 Jun 2021 03:08:54 -0400 Received: from first.geanix.com ([116.203.34.67]:54118 "EHLO first.geanix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230170AbhFUHIt (ORCPT ); Mon, 21 Jun 2021 03:08:49 -0400 Received: from 185.17.218.86 (unknown [185.17.218.86]) by first.geanix.com (Postfix) with ESMTPSA id AAC414C3BBA; Mon, 21 Jun 2021 07:06:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=silicom.dk; s=first; t=1624259193; bh=FQ6OmgXuxLP0LFgo3KI2yKErrT4d+o1nxrmrp3bEEeo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=biRmxCoeMc1eeHhzn66fWqS0A12JgTku2fYxF3bgQQIRzqoLFUSYIqsWG0Kx5fP5x FkcojwIlBNEaMBpqsiyObxZalGB0RuF5EUpUlcrUewIC5B8Ynu0NQO7uVNWT75mN6V ilVLQu1z3gesU7I4gXA6G+FM8oyzz1gi634dBv/+W969vn0PZH/MYV2be6jJJSdBjr OWorwkB/TJJ1ESJxiK/GR1TgowlbzY7JfEDpdlwoapD9LTMxggvC8le0xtxGYzwRVS g2GODuB8S0EeY61Hrda6yt9ZDvvZMHnv4+7P100+X3pkEJ0voYaY0VpQIcyuD00v0g vnGlL8xJXbfWg== From: =?utf-8?q?Martin_Hundeb=C3=B8ll?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , Jean Delvare , Guenter Roeck , Lee Jones , Mark Brown Cc: =?utf-8?q?Martin_Hundeb=C3=B8ll?= , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org, =?utf-8?q?Martin_Hu?= =?utf-8?q?ndeb=C3=B8ll?= Subject: [PATCH 3/4] spi: spi-altera-dfl: support n5010 feature revision Date: Mon, 21 Jun 2021 09:06:20 +0200 Message-Id: <20210621070621.431482-4-mhu@silicom.dk> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210621070621.431482-1-mhu@silicom.dk> References: <20210621070621.431482-1-mhu@silicom.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org The Max10 BMC on the Silicom n5010 PAC is slightly different than the existing BMC's, so use a dedicated feature revision detect it. Signed-off-by: Martin Hundebøll --- drivers/spi/spi-altera-dfl.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c index 3e32e4fe5895..d4908db39d87 100644 --- a/drivers/spi/spi-altera-dfl.c +++ b/drivers/spi/spi-altera-dfl.c @@ -111,6 +111,13 @@ static struct spi_board_info m10_bmc_info = { .chip_select = 0, }; +static struct spi_board_info m10_n5010_bmc_info = { + .modalias = "m10-n5010", + .max_speed_hz = 12500000, + .bus_num = 0, + .chip_select = 0, +}; + static void config_spi_master(void __iomem *base, struct spi_master *master) { u64 v; @@ -130,6 +137,7 @@ static void config_spi_master(void __iomem *base, struct spi_master *master) static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) { + struct spi_board_info *board_info = &m10_bmc_info; struct device *dev = &dfl_dev->dev; struct spi_master *master; struct altera_spi *hw; @@ -172,9 +180,12 @@ static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) goto exit; } - if (!spi_new_device(master, &m10_bmc_info)) { + if (dfl_feature_revision(base) == FME_FEATURE_REV_MAX10_SPI_N5010) + board_info = &m10_n5010_bmc_info; + + if (!spi_new_device(master, board_info)) { dev_err(dev, "%s failed to create SPI device: %s\n", - __func__, m10_bmc_info.modalias); + __func__, board_info->modalias); } return 0; From patchwork Mon Jun 21 07:06:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Hundeb=C3=B8ll?= X-Patchwork-Id: 12333903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1590C49EA5 for ; Mon, 21 Jun 2021 07:06:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF3E461205 for ; Mon, 21 Jun 2021 07:06:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230379AbhFUHJA (ORCPT ); Mon, 21 Jun 2021 03:09:00 -0400 Received: from first.geanix.com ([116.203.34.67]:54126 "EHLO first.geanix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230215AbhFUHIw (ORCPT ); Mon, 21 Jun 2021 03:08:52 -0400 Received: from 185.17.218.86 (unknown [185.17.218.86]) by first.geanix.com (Postfix) with ESMTPSA id 76C904C3BBC; Mon, 21 Jun 2021 07:06:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=silicom.dk; s=first; t=1624259195; bh=1YwLc2H2BckkRj4vXarfWOOaU87sQ2pkK5QQqGvScrs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ljBIetRDvDNk1Wi57+NSQK2gErXzawHV/SpY31t300IVoZP58COWVdymENVN5Duvk LR2HJaPm6Me5lTjgShpi9xsz0GbjabCcGZsXUkRZGYOkLxNiBg4ccBRInpkXN5+dcE TIP6Mn2wisOAZtKZBqIrx6Ly7uQoU/lKzMOumYQAiS47IHO6GUv9XIvtC0xuyX8f6P CzvSW7+ePHI2GfLln/pumcqNc50v+xmJliTPi/YFiEo80+EcIJhcGRXPcgqYO8Y1CN RMEJgBcSI8UrwBPjDiCO8OFcx8KLBNeMDmnTYztgO2VT3ZfcBvrSZ5BwQh5A7o8TTZ URNdd7I8Noezg== From: =?utf-8?q?Martin_Hundeb=C3=B8ll?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , Jean Delvare , Guenter Roeck , Lee Jones , Mark Brown Cc: =?utf-8?q?Martin_Hundeb=C3=B8ll?= , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org, =?utf-8?q?Martin_Hu?= =?utf-8?q?ndeb=C3=B8ll?= Subject: [PATCH 4/4] hwmon: intel-m10-bmc: add sensor support for Silicom N5010 card Date: Mon, 21 Jun 2021 09:06:21 +0200 Message-Id: <20210621070621.431482-5-mhu@silicom.dk> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210621070621.431482-1-mhu@silicom.dk> References: <20210621070621.431482-1-mhu@silicom.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org The Silicom N5010 PAC is similar to Intel N3000 and D5005. Enable monitoring of its sensors like it is done for the two Intel cards. Signed-off-by: Martin Hundebøll --- drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++ drivers/mfd/intel-m10-bmc.c | 12 ++- 2 files changed, 127 insertions(+), 1 deletion(-) diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c index bd7ed2ed3a1e..7a08e4c44a4b 100644 --- a/drivers/hwmon/intel-m10-bmc-hwmon.c +++ b/drivers/hwmon/intel-m10-bmc-hwmon.c @@ -228,6 +228,118 @@ static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = { .hinfo = d5005bmc_hinfo, }; +static const struct m10bmc_sdata n5010bmc_temp_tbl[] = { + { 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" }, + { 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" }, + { 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" }, + { 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" }, + { 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" }, + { 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" }, + { 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" }, + { 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" }, + { 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" }, + { 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" }, + { 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" }, + { 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" }, + { 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" }, + { 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" }, + { 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" }, + { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" }, + { 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" }, +}; + +static const struct m10bmc_sdata n5010bmc_in_tbl[] = { + { 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" }, + { 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" }, + { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" }, + { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" }, + { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" }, + { 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" }, + { 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" }, + { 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" }, + { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" }, + { 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" }, + { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" }, + { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" }, + { 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" }, +}; + +static const struct m10bmc_sdata n5010bmc_curr_tbl[] = { + { 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" }, + { 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" }, + { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" }, + { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" }, + { 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" }, + { 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" }, + { 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" }, + { 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" }, + { 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" }, + { 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" }, + { 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" }, + { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" }, + { 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" }, +}; + +static const struct hwmon_channel_info *n5010bmc_hinfo[] = { + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL), + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL), + HWMON_CHANNEL_INFO(curr, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL), + NULL +}; + +static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = { + .tables = { + [hwmon_temp] = n5010bmc_temp_tbl, + [hwmon_in] = n5010bmc_in_tbl, + [hwmon_curr] = n5010bmc_curr_tbl, + }, + + .hinfo = n5010bmc_hinfo, +}; + static umode_t m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr, int channel) @@ -438,6 +550,10 @@ static const struct platform_device_id intel_m10bmc_hwmon_ids[] = { .name = "d5005bmc-hwmon", .driver_data = (unsigned long)&d5005bmc_hwmon_bdata, }, + { + .name = "n5010bmc-hwmon", + .driver_data = (unsigned long)&n5010bmc_hwmon_bdata, + }, { } }; diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c index 1a9bfb7f48cd..8db3bcf5fccc 100644 --- a/drivers/mfd/intel-m10-bmc.c +++ b/drivers/mfd/intel-m10-bmc.c @@ -15,7 +15,8 @@ enum m10bmc_type { M10_N3000, - M10_D5005 + M10_D5005, + M10_N5010, }; static struct mfd_cell m10bmc_d5005_subdevs[] = { @@ -28,6 +29,10 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = { { .name = "n3000bmc-secure" }, }; +static struct mfd_cell m10bmc_n5010_subdevs[] = { + { .name = "n5010bmc-hwmon" }, +}; + static const struct regmap_range m10bmc_regmap_range[] = { regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER), regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END), @@ -192,6 +197,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi) cells = m10bmc_d5005_subdevs; n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs); break; + case M10_N5010: + cells = m10bmc_n5010_subdevs; + n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs); + break; default: return -ENODEV; } @@ -207,6 +216,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi) static const struct spi_device_id m10bmc_spi_id[] = { { "m10-n3000", M10_N3000 }, { "m10-d5005", M10_D5005 }, + { "m10-n5010", M10_N5010 }, { } }; MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);