From patchwork Thu Jun 24 12:02:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 12342047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64BBEC48BDF for ; Thu, 24 Jun 2021 12:06:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 30013613DC for ; Thu, 24 Jun 2021 12:06:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 30013613DC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:44634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwO7i-0003uh-Ah for qemu-devel@archiver.kernel.org; Thu, 24 Jun 2021 08:06:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3w-0003YP-4f for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:28 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:53591) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3t-0003oZ-Ip for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1624536145; x=1656072145; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ITFr8OeVAPrRxzJtiBdw3XbLzbr/OQpRi3PhUKINCQY=; b=fZLIsI9NEGTDNfBHdXNDa3ekvevG37yiS0TazZMZ9p3fMWSINZJDOvz/ 7kkrczHnFVhUKXjnymtVFBMF6RPHRRtTYTIdsGyFXfHWITEb5MV/9/cgL MyBlbWiZBnZG0Anx1CY4Euq//OrQGjVRhzJsTUW0sRb2kvdThOdAY6Pxp JHEUl61SlyJ3+HAr544KkWf1+5xXi7vXWuCLU84arCnD+4cEZOK+egNSm mnqrZhp/K1/ARcsTshbVL7TSdxnBGWJgwQfrLgwWrV6NCe6fRLJG1iDZY PkuuN6kUx/YU/SHFAbvlKPKeNSmnf81dlKvotn2TTqcTUE0JRSAeLMTpk w==; IronPort-SDR: H2CYvhD/q6780uLun62Kh+Bl5biaLmxdrq/9KfTOEMILSBj4MBBTLj3Jt6vbKtASiZ1R96SwGo yZyR7Dd1s6/D1ZDHPmHJ3EV1d1QOp6YbKYuI4CBqTl/gFLSsgDW33ycX0xD9En+THls6vXUMXC vainkrP9jsubscbRlnol13CQ41D0c6GvBSd+R37CHIYX5blkY703ZH+B0iBK4aIyB3Mq98+Qi5 ywgryEvKR6Y52L0E1KwD1h/x8P3jzzXCUrTMpe07DwSog0Q93aQyDfjn0vNfnXSVlSnfY1a24V nos= X-IronPort-AV: E=Sophos;i="5.83,296,1616428800"; d="scan'208";a="173360799" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Jun 2021 20:02:15 +0800 IronPort-SDR: bDkw4B/eTM68nR1ORJKqnby0ACLHx9gR/45tqW0ufi5XsnpQX60z7T3XP+xRf2HSS9br8YfhUe 628NFF6bE+W0xvaMB34Y/0fSs2IFFJT/LHFujj0TUM0uzWqTgI0BX+HZMJ9jsiqiUVL/1S+Yer a4MVfCCO3hKMjziZCPENHDSrm/8DYOMSElrETlux84E0pZ9wnhvEmEr4LJJxA+pv80mV0xKty0 W2NUvvlX6oLteucT/Tjg3/rm2yhKbo7yjkyKDmqDILjZ26uUUpaxraOarN7P5Zkj1gFmvtknsJ UAV5ncj8k+Crf/JaadJ+tGtL Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2021 04:39:30 -0700 IronPort-SDR: 2D0Bdf+WD0fnIVqiudrwadVCyiGXtJl7ihAiq1wGXC2rhTSPga3h1Gl+61fTdkumxthYknb4uJ 2fzZECaPt8Oh8YaQR7fRsQhCxjSxUnacjNgtT2DgfoGwBo7kS9AF2oJ9577jXEBLbWKe2PcFGw VLb/YjnKEY4pqZqmdgbjCCPGR+rX+3baoNGz9hpO/DceZAHhqbCSJTKFN5xkemcr4uB7jwLBIc fdJeLRBX/VQaGYFFvgEcg/ggfzBw0IldryHbbihRBLMYfRpOPONQIGvZm/YGiDO0lRDs1e8Vxh xd4= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip02.wdc.com with ESMTP; 24 Jun 2021 05:02:15 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 1/7] target/riscv: Use target_ulong for the DisasContext misa Date: Thu, 24 Jun 2021 05:02:05 -0700 Message-Id: <20210624120211.85499-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com> References: <20210624120211.85499-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=802348aeb=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The is_32bit() check in translate.c expects a 64-bit guest to have a 64-bit misa value otherwise the macro check won't work. This patches fixes that and fixes a Coverity issue at the same time. Fixes: CID 1453107 Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: c00176c7518c2a7b4de3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com --- target/riscv/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c6e8739614..62a7d7e4c7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -47,7 +47,7 @@ typedef struct DisasContext { bool virt_enabled; uint32_t opcode; uint32_t mstatus_fs; - uint32_t misa; + target_ulong misa; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for From patchwork Thu Jun 24 12:02:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 12342043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58901C48BDF for ; Thu, 24 Jun 2021 12:03:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B2A0613DC for ; Thu, 24 Jun 2021 12:03:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0B2A0613DC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:36494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwO5D-0006Fu-3f for qemu-devel@archiver.kernel.org; Thu, 24 Jun 2021 08:03:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3w-0003ZX-GN for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:28 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:53600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3u-0003qt-4r for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1624536146; x=1656072146; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o1fMzRHfUIya9XuwqHf51o/1khK1Dly0k/KbCVjHkIk=; b=mYysrgb5c45R6HpuTLlpdZhVwZO37YoUd5z1r2Ps7i2bIHuqn0+ygP6f H6ep0TDe+YTzMseag4vv1pvPy0RF5WB1BHeXcToJK9ZidMFewAuY0vPWG f8jnKQwJ7Op85rLBqDv8vOJuDVq56g/lZZApLsELA4fqX81IQoSS1hiZh NePlGhNOTTfjEPDNAbWXxTT8Y0mYDrS/HLkKngJaW58cM1PN1iflQDU4t ++acmrfsFLJq6L4LRCXj1+RrjDCKUStCexlj56eRBhZI/aw+faELUJvHs qqjDNjiyg5ZAWhgd5+fBWpiN04hc5WMP22NM2RFL/dsVumXMYuVhqGXO0 Q==; IronPort-SDR: eAOzwPQzyeYGvd6kab8uafqXxDUduMvveE5V85kd1TxrXTxHoca5jmGZo/HiM+iylwwuPJxbot 2CFIryZ1ub8zoKbzM7kFPjeSlA6KrsBZiuB8GvFwcxgaph5cRvRSPbvKVVauXHvFfykvrT9dIj 5VYE/n08NiQQQocSKMk/GPoc83mtDi8thCQJYLLH9IwqV0qo5rglwyT50CNGRQbtNvXcDdz4dM fWRclb5CynTcWj+nph0jxGicahFtaEjVMd+6Wmukqjprsxl4TkoZXu6+8HTFv6hegbt106EbJd PnI= X-IronPort-AV: E=Sophos;i="5.83,296,1616428800"; d="scan'208";a="173360800" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Jun 2021 20:02:15 +0800 IronPort-SDR: U4VSL8BKP2uIQYiDasokOqoI5Z7E4de4L5hBufs9VqtPJ+HijQFVF7NfuM/mNYmHvbIqqMUcER ma4N01hERcdJBbmdAaJpvcTQhrmXRK5q2vCK3FE+u3lrPed2eP0SV6PEcnLuXIq77GMKizfFV1 qqPGDTGYnBEiZ5w98pIJ7xtxF9jd3Yhe1DSs6QpCHVj102LJsaxdTb+GyavpF+31ub97Sl6gYG WN2/D/mSLrLhC00uqEaayDr75zoRzbmfhai9a/3iJ9e51K+BloshouqxmehQ1iGpzptMyGaWrR v+khSyGzQMNL/WL2NlbUHQtQ Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2021 04:39:30 -0700 IronPort-SDR: fBoln/6UP9RyZ5JcqlD8tE/+vEBXAzw66SGhsr8WrCmPogohmrkezG8Zm3QI93VxIhj7WxRUdv MHmzSTrguQysoEsNkSDVQLgfDT3QRPuWSNQAUegL6SQZxPX349x/WZ9U2qrtODxx9y2cvdw7II QjuwGAkP+62R+80Q/dkmuiYLk+v2PcWDl/oeKfdkPolsEtxIif9MSuosA4WdLneb5ZfHRI5Ci8 QerWTCr4zpA0QstINlt6neTLavcYXOuA1hFUxYMqGcK6Sya2PiFclZnj89KyxPjzaW9BSl58fT KvY= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip02.wdc.com with ESMTP; 24 Jun 2021 05:02:15 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation Date: Thu, 24 Jun 2021 05:02:06 -0700 Message-Id: <20210624120211.85499-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com> References: <20210624120211.85499-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=802348aeb=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xuzhou Cheng , Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Since commit 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations") the CSR predicate() function was changed to return RISCV_EXCP_NONE instead of 0 for a valid CSR, but it forgot to update the dynamic CSR XML generation codes in gdbstub. Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations") Reported-by: Xuzhou Cheng Signed-off-by: Bin Meng Tested-by: Xuzhou Cheng Reviewed-by: Alistair Francis Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- target/riscv/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ca78682cf4..a7a9c0b1fe 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -170,7 +170,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) for (i = 0; i < CSR_TABLE_SIZE; i++) { predicate = csr_ops[i].predicate; - if (predicate && !predicate(env, i)) { + if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) { if (csr_ops[i].name) { g_string_append_printf(s, " X-Patchwork-Id: 12342049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C270C49EA5 for ; Thu, 24 Jun 2021 12:06:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 458AC613DA for ; Thu, 24 Jun 2021 12:06:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 458AC613DA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:44594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwO7i-0003tS-E9 for qemu-devel@archiver.kernel.org; Thu, 24 Jun 2021 08:06:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54454) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3y-0003f2-U2 for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:31 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:53591) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3w-0003oZ-FK for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1624536148; x=1656072148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8K8GtISv5QuI3fx9PL6mn3y9ZOkm6y/jwxGKQP8i/Ks=; b=GRWNOpVrzo/oUUvjbD7Uz7gUAOBIpsKQeWCQMK7L9otk56TnczlRrqn1 TJhYknK14UhRdRWCbNWHLt0pwE2qIDZY4tc2TbsGcqPZNP5K74SP+GyUk XfXV50LLFT453glbznEIt8+9lkYByYtKgqfaKEF+Cn++Otn647PSPTidi tMGj3CgpsYNOasjczNEvNX/DoZs5rixEJtfMS04si7m8dk1Fjf9pzkHG+ PdUd0AjT6yZhSa+6rcFC8+EmS2GMnRzZGgckoifwIM2h62LgtFkwSpWfo r/cOd5KFGreZkZTf7nJhRI5lNeVe0Kw0cwS8AMSkNEHrpfu63WS22vZp0 A==; IronPort-SDR: V7GGmRP3oFD6nkDLRYH99bzs0iK0wHQlp081TYMXFiYepFirly3ncuv9QwpT1E7b16avO17qAw EU8/aUuHk5g0DteF+9v2HJ2bNJFFJWtI3wgZIDtiugTyIM7mr4Fm3xfs0fhhQlVoLelEBlQ1Px RDP8lr5k1mTsI1or8R+UkOzYs1DHiSEd7u9q7f7ITKlFBdPjTO17fsJFEDTKhSgZSukVVloqGe w30f6Dy2Zl3PxATamvRa7Vti3+Nve41nKaXwbYaNZimKBvtXjCW42jTyQNhx/x77F0H0HC1Lh3 29U= X-IronPort-AV: E=Sophos;i="5.83,296,1616428800"; d="scan'208";a="173360801" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Jun 2021 20:02:15 +0800 IronPort-SDR: Jb4BhOvFNLGTgbN0z1XzkDVerVhQhVGVkFG2W3bRzz0OenNS7nY0TPOUdpt1v3NI/TEeJTL+Gw 3ReM0z3w6X+mc4Bo3Ku5ivFwNQ5+rNJFYf30PTN2rGz0d55FPMVtNy/MtDIL3Kze+wV/cw2XHV PR8rO8nEvVgXuAWAiiVNIlE4iVAPgOR+Ac+sAoFTbXxcJV5KfrohKVYT5obu6j8U4dZHiIi2QQ Knh2hefOVcKzIs6AzoTEM74oKrRxIZQd5ZidgPOpD3Yft3dYPCTU0HMsmX/oc3MSRE2ITOcxt4 ZSPzqTbUiQqyWoia1aqGJh3F Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2021 04:39:31 -0700 IronPort-SDR: RTvru4PtCZ0G7zN/yNbJViUdsJOXiPjVTUKOUSNX7E4PEbkjydyCd5dDLcW8TZSCleVw7PUmsP YWQJ2q7pGh9dDgeUUKzkgX87iygqA+owekXOUlp5G/sUwEanPt3hHdvL8Zxy2G2O5QF2msoPUk dKinStAaQzlnDgbR/aDYB5ZihK973FXUxn/OTN8KLO0DBszHHBkCC0GXHXnWl4e5UYnDVQWk75 jSi9ikmjDjlvXH+yT/C3vlOrR5HZCKItUcGkeX660cAzkYnzCokqY2R8OlMY1DtPjoRh1df6/Y q54= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip02.wdc.com with ESMTP; 24 Jun 2021 05:02:16 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 3/7] hw/char: Consistent function names for sifive_uart Date: Thu, 24 Jun 2021 05:02:07 -0700 Message-Id: <20210624120211.85499-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com> References: <20210624120211.85499-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=802348aeb=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis , =?utf-8?q?Lukas_J=C3=BCnger?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Lukas Jünger This cleans up function names in the SiFive UART model. Signed-off-by: Lukas Jünger Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20210616092326.59639-2-lukas.juenger@greensocs.com Signed-off-by: Alistair Francis --- hw/char/sifive_uart.c | 46 ++++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index fe12666789..5df8212961 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -31,7 +31,7 @@ */ /* Returns the state of the IP (interrupt pending) register */ -static uint64_t uart_ip(SiFiveUARTState *s) +static uint64_t sifive_uart_ip(SiFiveUARTState *s) { uint64_t ret = 0; @@ -48,7 +48,7 @@ static uint64_t uart_ip(SiFiveUARTState *s) return ret; } -static void update_irq(SiFiveUARTState *s) +static void sifive_uart_update_irq(SiFiveUARTState *s) { int cond = 0; if ((s->ie & SIFIVE_UART_IE_TXWM) || @@ -63,7 +63,7 @@ static void update_irq(SiFiveUARTState *s) } static uint64_t -uart_read(void *opaque, hwaddr addr, unsigned int size) +sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) { SiFiveUARTState *s = opaque; unsigned char r; @@ -74,7 +74,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); s->rx_fifo_len--; qemu_chr_fe_accept_input(&s->chr); - update_irq(s); + sifive_uart_update_irq(s); return r; } return 0x80000000; @@ -84,7 +84,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) case SIFIVE_UART_IE: return s->ie; case SIFIVE_UART_IP: - return uart_ip(s); + return sifive_uart_ip(s); case SIFIVE_UART_TXCTRL: return s->txctrl; case SIFIVE_UART_RXCTRL: @@ -99,8 +99,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) } static void -uart_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) +sifive_uart_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) { SiFiveUARTState *s = opaque; uint32_t value = val64; @@ -109,11 +109,11 @@ uart_write(void *opaque, hwaddr addr, switch (addr) { case SIFIVE_UART_TXFIFO: qemu_chr_fe_write(&s->chr, &ch, 1); - update_irq(s); + sifive_uart_update_irq(s); return; case SIFIVE_UART_IE: s->ie = val64; - update_irq(s); + sifive_uart_update_irq(s); return; case SIFIVE_UART_TXCTRL: s->txctrl = val64; @@ -129,9 +129,9 @@ uart_write(void *opaque, hwaddr addr, __func__, (int)addr, (int)value); } -static const MemoryRegionOps uart_ops = { - .read = uart_read, - .write = uart_write, +static const MemoryRegionOps sifive_uart_ops = { + .read = sifive_uart_read, + .write = sifive_uart_write, .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 4, @@ -139,7 +139,7 @@ static const MemoryRegionOps uart_ops = { } }; -static void uart_rx(void *opaque, const uint8_t *buf, int size) +static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size) { SiFiveUARTState *s = opaque; @@ -150,26 +150,27 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size) } s->rx_fifo[s->rx_fifo_len++] = *buf; - update_irq(s); + sifive_uart_update_irq(s); } -static int uart_can_rx(void *opaque) +static int sifive_uart_can_rx(void *opaque) { SiFiveUARTState *s = opaque; return s->rx_fifo_len < sizeof(s->rx_fifo); } -static void uart_event(void *opaque, QEMUChrEvent event) +static void sifive_uart_event(void *opaque, QEMUChrEvent event) { } -static int uart_be_change(void *opaque) +static int sifive_uart_be_change(void *opaque) { SiFiveUARTState *s = opaque; - qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, - uart_be_change, s, NULL, true); + qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, + sifive_uart_event, sifive_uart_be_change, s, + NULL, true); return 0; } @@ -183,9 +184,10 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState)); s->irq = irq; qemu_chr_fe_init(&s->chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, - uart_be_change, s, NULL, true); - memory_region_init_io(&s->mmio, NULL, &uart_ops, s, + qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, + sifive_uart_event, sifive_uart_be_change, s, + NULL, true); + memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s, TYPE_SIFIVE_UART, SIFIVE_UART_MAX); memory_region_add_subregion(address_space, base, &s->mmio); return s; From patchwork Thu Jun 24 12:02:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 12342045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BDC8C49EA5 for ; Thu, 24 Jun 2021 12:03:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B556613DC for ; Thu, 24 Jun 2021 12:03:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9B556613DC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:36782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwO5G-0006TK-Qs for qemu-devel@archiver.kernel.org; Thu, 24 Jun 2021 08:03:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3z-0003f8-0G for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:31 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:53600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3w-0003qt-QO for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1624536149; x=1656072149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wTSMQcxrzoNLuvbpTokHxXESlCREDyWr7/06oIRidGM=; b=U5R1O6h/DKtzPnFOZkXGuwM38OLFStl7OrcKMZEcVZRzF8fCL6JLbt6s cJtB/2r9z80sVg4W+FHA3kYtQCtXJ5or2I9mee1tKB9LhaqyxWq7UdPBt 4wuUJgbjguMwf7uSJwjRykQpHCjyGhqUfKJFdsg8jhH1H+4OpRQvwp6CZ hyLluqWcXbUpn0DLXmmmcp77wR0MF30+0Cx503YuQG/qaqGW3YQIR0Cp3 gOWw/t0Q45PAxBIiFtiF2p3vxyKBsqTZYDxxWTssd6xfQ74Rq7bAGIU4Z F14LXz/aAEJcq9PT1QnDqFgUYd24r4HQUWWjiXaGflZ/PTEWgIweq3KeZ g==; IronPort-SDR: nnJ3utGx4CcGUx0Qeky2NrIqGiZfZVNF9S5vt35Q6lnZoih9koSvQO3pqjW/zJnQrBgX/VHcd8 FSZwGTCC+SGZYPypMqRDaR8K+EmfNHU0T67NKw+VqVg5+08HS66yhchcN+I0VzZRG/XEQr0x/O e80lpU+UZeF5WERiG+4hxUo3aym9yMfoohrkognadg7TY3ADOpS9ViAr68Pfe17FS6zF7dgM/v DYJJC3Ss9CE3nekXe+SaZgW32tx5vjNcCMzC/bBy3rd127gjHe7izJnUxzJhnhpfQFXj9t9mAW cRE= X-IronPort-AV: E=Sophos;i="5.83,296,1616428800"; d="scan'208";a="173360802" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Jun 2021 20:02:15 +0800 IronPort-SDR: HFSQEv3ohOPjw+kq1O4IwM6GY5PZcPOU6H7D6kenRq6Hl2/uX5GBkxc7yj8IYXZGNB0ffcX907 +HsWih5pdf9jXJyugEwoc9xFW+nNQVUKcMBWnca+7nWWTs71/1bfwgp3FiU+UXbAGR2K0NmlnS UUhuV0ZUmd6CGYBXR39GEjYhdeDRuEQgtTbreEZTPvEsV9bEJIBRchOL/GEYYoE7mzQCxVJgDG +miHa2pUHbu7QXi8lXksHfZ0Z+/YsxhaJLlk9Q7r0Kq27yKJ/Aum5aN1uDlMh4yjeU7Moj9KPn 5/+JZcLAzCHN0D2lEpEtGcX0 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2021 04:39:31 -0700 IronPort-SDR: yYwIZJUQ7eZ8VXTBFSnOK1NuXSVYUWyVRmO7nWCfhvpkpXX422Nqemh+BCkE/GkbfMDiwNWRgm PQCxqnnm+WrzkvdKZiNYrEUDTT3nikFi+XNrSs7dz75nbjbJXlw6t/SHZZsBpf/o7qplgYmrwS 3e5ErQl9UHMu3woI8w2lwFYsXlQrI1VqIkrbkekJRnBy25l72Aq5Xdn28zXQUV06KxGRY8Rl4h K183e9V7QsmqNWWcK2n6JWfu2JbL5jU0+u4eqWDmILkqNFr7ysdBtruPS1+ABRxNuJozF63YNW mKM= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip02.wdc.com with ESMTP; 24 Jun 2021 05:02:16 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 4/7] hw/char: QOMify sifive_uart Date: Thu, 24 Jun 2021 05:02:08 -0700 Message-Id: <20210624120211.85499-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com> References: <20210624120211.85499-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=802348aeb=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis , =?utf-8?q?Lukas_J=C3=BCnger?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Lukas Jünger This QOMifies the SiFive UART model. Migration and reset have been implemented. Signed-off-by: Lukas Jünger Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210616092326.59639-3-lukas.juenger@greensocs.com Signed-off-by: Alistair Francis --- include/hw/char/sifive_uart.h | 11 ++-- hw/char/sifive_uart.c | 114 +++++++++++++++++++++++++++++++--- 2 files changed, 109 insertions(+), 16 deletions(-) diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h index 3e962be659..7f6c79f8bd 100644 --- a/include/hw/char/sifive_uart.h +++ b/include/hw/char/sifive_uart.h @@ -21,6 +21,7 @@ #define HW_SIFIVE_UART_H #include "chardev/char-fe.h" +#include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qom/object.h" @@ -49,12 +50,10 @@ enum { #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) +#define SIFIVE_UART_RX_FIFO_SIZE 8 #define TYPE_SIFIVE_UART "riscv.sifive.uart" - -typedef struct SiFiveUARTState SiFiveUARTState; -DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART, - TYPE_SIFIVE_UART) +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART) struct SiFiveUARTState { /*< private >*/ @@ -64,8 +63,8 @@ struct SiFiveUARTState { qemu_irq irq; MemoryRegion mmio; CharBackend chr; - uint8_t rx_fifo[8]; - unsigned int rx_fifo_len; + uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; + uint8_t rx_fifo_len; uint32_t ie; uint32_t ip; uint32_t txctrl; diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index 5df8212961..278e21c434 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -19,10 +19,12 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/log.h" +#include "migration/vmstate.h" #include "chardev/char.h" #include "chardev/char-fe.h" #include "hw/irq.h" #include "hw/char/sifive_uart.h" +#include "hw/qdev-properties-system.h" /* * Not yet implemented: @@ -175,20 +177,112 @@ static int sifive_uart_be_change(void *opaque) return 0; } +static Property sifive_uart_properties[] = { + DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_uart_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + SiFiveUARTState *s = SIFIVE_UART(obj); + + memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s, + TYPE_SIFIVE_UART, SIFIVE_UART_MAX); + sysbus_init_mmio(sbd, &s->mmio); + sysbus_init_irq(sbd, &s->irq); +} + +static void sifive_uart_realize(DeviceState *dev, Error **errp) +{ + SiFiveUARTState *s = SIFIVE_UART(dev); + + qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, + sifive_uart_event, sifive_uart_be_change, s, + NULL, true); + +} + +static void sifive_uart_reset_enter(Object *obj, ResetType type) +{ + SiFiveUARTState *s = SIFIVE_UART(obj); + s->ie = 0; + s->ip = 0; + s->txctrl = 0; + s->rxctrl = 0; + s->div = 0; + s->rx_fifo_len = 0; +} + +static void sifive_uart_reset_hold(Object *obj) +{ + SiFiveUARTState *s = SIFIVE_UART(obj); + qemu_irq_lower(s->irq); +} + +static const VMStateDescription vmstate_sifive_uart = { + .name = TYPE_SIFIVE_UART, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState, + SIFIVE_UART_RX_FIFO_SIZE), + VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState), + VMSTATE_UINT32(ie, SiFiveUARTState), + VMSTATE_UINT32(ip, SiFiveUARTState), + VMSTATE_UINT32(txctrl, SiFiveUARTState), + VMSTATE_UINT32(rxctrl, SiFiveUARTState), + VMSTATE_UINT32(div, SiFiveUARTState), + VMSTATE_END_OF_LIST() + }, +}; + + +static void sifive_uart_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); + + dc->realize = sifive_uart_realize; + dc->vmsd = &vmstate_sifive_uart; + rc->phases.enter = sifive_uart_reset_enter; + rc->phases.hold = sifive_uart_reset_hold; + device_class_set_props(dc, sifive_uart_properties); +} + +static const TypeInfo sifive_uart_info = { + .name = TYPE_SIFIVE_UART, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveUARTState), + .instance_init = sifive_uart_init, + .class_init = sifive_uart_class_init, +}; + +static void sifive_uart_register_types(void) +{ + type_register_static(&sifive_uart_info); +} + +type_init(sifive_uart_register_types) + /* * Create UART device. */ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, Chardev *chr, qemu_irq irq) { - SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState)); - s->irq = irq; - qemu_chr_fe_init(&s->chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, - sifive_uart_event, sifive_uart_be_change, s, - NULL, true); - memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s, - TYPE_SIFIVE_UART, SIFIVE_UART_MAX); - memory_region_add_subregion(address_space, base, &s->mmio); - return s; + DeviceState *dev; + SysBusDevice *s; + SiFiveUARTState *r; + + dev = qdev_new("riscv.sifive.uart"); + s = SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", chr); + sysbus_realize_and_unref(s, &error_fatal); + memory_region_add_subregion(address_space, base, + sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, irq); + + r = SIFIVE_UART(dev); + return r; } From patchwork Thu Jun 24 12:02:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 12342051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 851DBC48BDF for ; Thu, 24 Jun 2021 12:06:31 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0649E613DC for ; Thu, 24 Jun 2021 12:06:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0649E613DC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:45310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwO7q-0004Xi-4V for qemu-devel@archiver.kernel.org; Thu, 24 Jun 2021 08:06:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO40-0003jR-A4 for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:32 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:53602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3x-0003ro-0K for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:32 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1624536149; x=1656072149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3qkqOh9xUfVzpHWka6NyGJ5iqiTacl9dGnX54ZY7ZzY=; b=eNtS+h+5QzoWtpKEQYNvSNMfu/iUxptU6c5mSuTknDYZyJ3i+zOzNzXf SXHpGR0twaqk737FV9koWmzdmS3zHLjs9/Ng58iQyQMfJU5UVyVqe2odT NcE0D3W6S1wGZaOWN9pYlr1Ekotev8mGezaaxo6XOIODBBu2Z3HZ5ek4U +3+s/AeqZsEoxdNY/IKGjRzEcP2z5wtiwl2KelS3c0F6KlbA4h49udZoW 2CgDlNySftWYQFbuiWg3WdiS+S1+/uZqitAQYnShXleu7dGV+QhNQ/en1 6o4elHRPJ0B6nmj79dWBqOiAafE+6Qldvz61+Ty1a1AicmVF0AV88F29Z Q==; IronPort-SDR: pprYtaOQUlgnnAMgtq66wIb6qZt1O5o2vAFxwc7JzT5KsO9Lj1RjxnejsjaVD1YthNc4D2c0oB IPzS8LSsZiJSpH0H55U7dlpp+Kd5QT4oLLthjaw7fm6WEkznyEUh8gh72MA67XNhE/LkkSs2LG +0B5gj/Sm3M59YAJ5tKFCGliSti/+O0nXf0hlM4FM/aiN129jv0RMgCGzqUAgBgpgclwDVlQyC R68CP7QhKDj93o7iHVDHzTeh+gF+oQ2ecgAUclpwzPFrmvRbYDgKOPwy0M43S+dwwihSBIDvKm ksY= X-IronPort-AV: E=Sophos;i="5.83,296,1616428800"; d="scan'208";a="173360803" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Jun 2021 20:02:16 +0800 IronPort-SDR: NIh8hmIsRDtweyseeKvOrSdOdl/m7XFToeOQxssVru5jZdvGru8HmXkCjCzYygN3yn95F+wH2X YSZuk50TF/cgMQP39UFcjs+p39Td+EyiP3xzxPyErXR+qxuqJJnpIhMbk/y8Ypy+KlAd6SYy/b jTT2jedl5+Xg4ULTH2UR8fmj8pJ97HAhJQPI8rtqcmbbG2krcvxvG+YlvkGZH7hf3XlXBRj5Na ryFbHTa//jgKrpUBD+FiGix5A+tgwlURnD92settKxN9uicnIMMLfvyu3rcRW/ChC9hNy11RUi PXtfUNsT+ZUxsTvThyDmO6b1 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2021 04:39:31 -0700 IronPort-SDR: 5p7BpJ6t4uEpMNeHnXg7SEAXFEcG646vR8ObNYQsOYHMOKLbwsQuzfjeMqyo+EhuTuWObfBVRZ EKJCvPkLzrVYgzLsDBp066caMP3Ssa5RKYHubQl1h6UfKx1XX8ve/DnHHYHnlbOOr88TNmHbNv GjcG93RbLkkjrt/QodbUb8U1yalTOSZkRJGC6ZMTk5LMqTgWpVpH7Td5AasqPJeJ+c+GVZoNzl dAJz+q5Gp3tuVd2eWU/qSGFsRbzx0HzS0DPGvtJyk96azFiclVJjLyADWRHUMogZR1r7VA9+Ri XLA= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip02.wdc.com with ESMTP; 24 Jun 2021 05:02:16 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 5/7] hw/char/ibex_uart: Make the register layout private Date: Thu, 24 Jun 2021 05:02:09 -0700 Message-Id: <20210624120211.85499-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com> References: <20210624120211.85499-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=802348aeb=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We don't need to expose the register layout in the public header, so don't. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: c437f570b2b30ab4170387a3ba2fad7d116a4986.1624001156.git.alistair.francis@wdc.com --- include/hw/char/ibex_uart.h | 37 ------------------------------------- hw/char/ibex_uart.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h index 546f958eb8..a39985516a 100644 --- a/include/hw/char/ibex_uart.h +++ b/include/hw/char/ibex_uart.h @@ -31,43 +31,6 @@ #include "qemu/timer.h" #include "qom/object.h" -REG32(INTR_STATE, 0x00) - FIELD(INTR_STATE, TX_WATERMARK, 0, 1) - FIELD(INTR_STATE, RX_WATERMARK, 1, 1) - FIELD(INTR_STATE, TX_EMPTY, 2, 1) - FIELD(INTR_STATE, RX_OVERFLOW, 3, 1) -REG32(INTR_ENABLE, 0x04) -REG32(INTR_TEST, 0x08) -REG32(CTRL, 0x0C) - FIELD(CTRL, TX_ENABLE, 0, 1) - FIELD(CTRL, RX_ENABLE, 1, 1) - FIELD(CTRL, NF, 2, 1) - FIELD(CTRL, SLPBK, 4, 1) - FIELD(CTRL, LLPBK, 5, 1) - FIELD(CTRL, PARITY_EN, 6, 1) - FIELD(CTRL, PARITY_ODD, 7, 1) - FIELD(CTRL, RXBLVL, 8, 2) - FIELD(CTRL, NCO, 16, 16) -REG32(STATUS, 0x10) - FIELD(STATUS, TXFULL, 0, 1) - FIELD(STATUS, RXFULL, 1, 1) - FIELD(STATUS, TXEMPTY, 2, 1) - FIELD(STATUS, RXIDLE, 4, 1) - FIELD(STATUS, RXEMPTY, 5, 1) -REG32(RDATA, 0x14) -REG32(WDATA, 0x18) -REG32(FIFO_CTRL, 0x1c) - FIELD(FIFO_CTRL, RXRST, 0, 1) - FIELD(FIFO_CTRL, TXRST, 1, 1) - FIELD(FIFO_CTRL, RXILVL, 2, 3) - FIELD(FIFO_CTRL, TXILVL, 5, 2) -REG32(FIFO_STATUS, 0x20) - FIELD(FIFO_STATUS, TXLVL, 0, 5) - FIELD(FIFO_STATUS, RXLVL, 16, 5) -REG32(OVRD, 0x24) -REG32(VAL, 0x28) -REG32(TIMEOUT_CTRL, 0x2c) - #define IBEX_UART_TX_FIFO_SIZE 16 #define IBEX_UART_CLOCK 50000000 /* 50MHz clock */ diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index 73b8f2e45b..fe4b6c3c9e 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -35,6 +35,43 @@ #include "qemu/log.h" #include "qemu/module.h" +REG32(INTR_STATE, 0x00) + FIELD(INTR_STATE, TX_WATERMARK, 0, 1) + FIELD(INTR_STATE, RX_WATERMARK, 1, 1) + FIELD(INTR_STATE, TX_EMPTY, 2, 1) + FIELD(INTR_STATE, RX_OVERFLOW, 3, 1) +REG32(INTR_ENABLE, 0x04) +REG32(INTR_TEST, 0x08) +REG32(CTRL, 0x0C) + FIELD(CTRL, TX_ENABLE, 0, 1) + FIELD(CTRL, RX_ENABLE, 1, 1) + FIELD(CTRL, NF, 2, 1) + FIELD(CTRL, SLPBK, 4, 1) + FIELD(CTRL, LLPBK, 5, 1) + FIELD(CTRL, PARITY_EN, 6, 1) + FIELD(CTRL, PARITY_ODD, 7, 1) + FIELD(CTRL, RXBLVL, 8, 2) + FIELD(CTRL, NCO, 16, 16) +REG32(STATUS, 0x10) + FIELD(STATUS, TXFULL, 0, 1) + FIELD(STATUS, RXFULL, 1, 1) + FIELD(STATUS, TXEMPTY, 2, 1) + FIELD(STATUS, RXIDLE, 4, 1) + FIELD(STATUS, RXEMPTY, 5, 1) +REG32(RDATA, 0x14) +REG32(WDATA, 0x18) +REG32(FIFO_CTRL, 0x1c) + FIELD(FIFO_CTRL, RXRST, 0, 1) + FIELD(FIFO_CTRL, TXRST, 1, 1) + FIELD(FIFO_CTRL, RXILVL, 2, 3) + FIELD(FIFO_CTRL, TXILVL, 5, 2) +REG32(FIFO_STATUS, 0x20) + FIELD(FIFO_STATUS, TXLVL, 0, 5) + FIELD(FIFO_STATUS, RXLVL, 16, 5) +REG32(OVRD, 0x24) +REG32(VAL, 0x28) +REG32(TIMEOUT_CTRL, 0x2c) + static void ibex_uart_update_irqs(IbexUartState *s) { if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) { From patchwork Thu Jun 24 12:02:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 12342071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BF37C48BDF for ; Thu, 24 Jun 2021 12:07:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A22D5613E3 for ; Thu, 24 Jun 2021 12:07:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A22D5613E3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:51412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwO98-0000Ob-SD for qemu-devel@archiver.kernel.org; Thu, 24 Jun 2021 08:07:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54530) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO42-0003rp-Q1 for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:34 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:53591) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3z-0003oZ-8S for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:34 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1624536151; x=1656072151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UjNVnjyRwVJUGdZmb3EJguPKjWkN014+XOi7BQD72eA=; b=L5ewjwQK6nEf0/c9Fe99ASS7vqv+Ef7KgaON61hqN0K8MEwA5NjXnBf6 l9cp6chq4NHOgRWMX4Lm55yCrpYGHpQrDRVu8VU4Ni20O38jY8gqMs5/s B1/5ObCkS0Vo2L9zblPXVi7b/67uuRU+KlRIpuG9gqz9IhYTar8cX4F4u YKVli/WzPmkUHm5AYpsrEUy5z2r6MUX0b3PQtg11RDWBSyasYNE+7VC69 LEy4Vp5mx8fa9psa39FOoIs7G3kpHqzSAZtfO5bFozuSyZK5NO45wGuk/ 5fB7nxMFqZqg70cy7BYRa3HPUoIGpRhzyrBo86N7PjXFdIzgkwz/AO3cu A==; IronPort-SDR: 3wkdzTfJe/WTV2tQNKaCQ4bPkHJ/fbl4cQ372i78aAOsOA57vBG2q1iivo/bp9WOMA1kUapsdI sEjvASfahi+anxWvhkH87e/Sz5PEXjvXrlW5vPrU14SwbvFJd/2XJsnttNqM5HEdgUqT3XUde+ VH2ZEM6HcjfT5cJkXHxKUhqhrO2fWX+Z3wv+aWcZKwjl4o2ZKewU8q7Q8PEGUaK7Wg/2X5qg83 ilEg5pj7544f15b1ryRXaD934XGzoZogQZZrBr9+5+tpJcZbxvm1ZFWJBa9wzNKcV40WW1dJCB vng= X-IronPort-AV: E=Sophos;i="5.83,296,1616428800"; d="scan'208";a="173360804" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 24 Jun 2021 20:02:16 +0800 IronPort-SDR: zAx/j2obBLaQ3Vyb/RdAmX2cdZnAAjKGqfUzIN7Q7d/GbYmRPR5Zldb5AIqrDf/DYmG+p36xdh FGOGYLOvR0OtzGZllaqMqy9rNl1l7QcXfIojP8VGfhv9qHGdbNtbw9vZFAb4iFe9X6+33Q2392 iQaxrgh8FNRzDHfy1+Ko5sy8Po5hpZuq9scG2UPFzPKYJ4PwH8P0rTrsjePE4X//45H4WBqdwg XwRtcW9cLVAeXYfvaeo7S5SRZAhYM5wg5/y8zM54kIux0zfFf9HxwW8jpfbsjDDU/EkUnwUXoL D4xqAWRhgG44YwcOUr94BdGv Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2021 04:39:31 -0700 IronPort-SDR: 1tpswv8ppyrGhPQe2mn8UApj/GHKQoeyfZ+GRqVFaeFBCRLFy5irrVVQ6weiDLQ8YEHI26mmyy +sAKOvVP4EOkLtGrFHuEl+2y4/PKLzPJur3CfCMG08XPzoQjVMUVk49tg0nrlEo5QZvL1SmGSa qX02KJojx1awdpP2VC6u/yJOVLlEOC2cgyWAPuAJ+WOCmnWJ6+ehHStaKEZI9guAdcxKeTCUqD 9FBGDIW8ilQg40fR1SwaZDVURuy/VAyZQYp7eTGYzQS4xDy4NrJbfVSHhMlXPLF4JFaUrCTZN+ TfQ= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip02.wdc.com with ESMTP; 24 Jun 2021 05:02:16 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 6/7] hw/timer: Initial commit of Ibex Timer Date: Thu, 24 Jun 2021 05:02:10 -0700 Message-Id: <20210624120211.85499-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com> References: <20210624120211.85499-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=802348aeb=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add support for the Ibex timer. This is used with the RISC-V mtime/mtimecmp similar to the SiFive CLINT. We currently don't support changing the prescale or the timervalue. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 716fdea2244515ce86a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com --- include/hw/timer/ibex_timer.h | 52 ++++++ hw/timer/ibex_timer.c | 305 ++++++++++++++++++++++++++++++++++ MAINTAINERS | 6 +- hw/timer/meson.build | 1 + 4 files changed, 360 insertions(+), 4 deletions(-) create mode 100644 include/hw/timer/ibex_timer.h create mode 100644 hw/timer/ibex_timer.c diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h new file mode 100644 index 0000000000..6a43537003 --- /dev/null +++ b/include/hw/timer/ibex_timer.h @@ -0,0 +1,52 @@ +/* + * QEMU lowRISC Ibex Timer device + * + * Copyright (c) 2021 Western Digital + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_IBEX_TIMER_H +#define HW_IBEX_TIMER_H + +#include "hw/sysbus.h" + +#define TYPE_IBEX_TIMER "ibex-timer" +OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER) + +struct IbexTimerState { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t timer_ctrl; + uint32_t timer_cfg0; + uint32_t timer_compare_lower0; + uint32_t timer_compare_upper0; + uint32_t timer_intr_enable; + uint32_t timer_intr_state; + uint32_t timer_intr_test; + + uint32_t timebase_freq; + + qemu_irq irq; +}; +#endif /* HW_IBEX_TIMER_H */ diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c new file mode 100644 index 0000000000..5befb53506 --- /dev/null +++ b/hw/timer/ibex_timer.c @@ -0,0 +1,305 @@ +/* + * QEMU lowRISC Ibex Timer device + * + * Copyright (c) 2021 Western Digital + * + * For details check the documentation here: + * https://docs.opentitan.org/hw/ip/rv_timer/doc/ + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "hw/timer/ibex_timer.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "target/riscv/cpu.h" +#include "migration/vmstate.h" + +REG32(CTRL, 0x00) + FIELD(CTRL, ACTIVE, 0, 1) +REG32(CFG0, 0x100) + FIELD(CFG0, PRESCALE, 0, 12) + FIELD(CFG0, STEP, 16, 8) +REG32(LOWER0, 0x104) +REG32(UPPER0, 0x108) +REG32(COMPARE_LOWER0, 0x10C) +REG32(COMPARE_UPPER0, 0x110) +REG32(INTR_ENABLE, 0x114) + FIELD(INTR_ENABLE, IE_0, 0, 1) +REG32(INTR_STATE, 0x118) + FIELD(INTR_STATE, IS_0, 0, 1) +REG32(INTR_TEST, 0x11C) + FIELD(INTR_TEST, T_0, 0, 1) + +static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) +{ + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + timebase_freq, NANOSECONDS_PER_SECOND); +} + +static void ibex_timer_update_irqs(IbexTimerState *s) +{ + CPUState *cs = qemu_get_cpu(0); + RISCVCPU *cpu = RISCV_CPU(cs); + uint64_t value = s->timer_compare_lower0 | + ((uint64_t)s->timer_compare_upper0 << 32); + uint64_t next, diff; + uint64_t now = cpu_riscv_read_rtc(s->timebase_freq); + + if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) { + /* Timer isn't active */ + return; + } + + /* Update the CPUs mtimecmp */ + cpu->env.timecmp = value; + + if (cpu->env.timecmp <= now) { + /* + * If the mtimecmp was in the past raise the interrupt now. + */ + riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); + if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { + s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; + qemu_set_irq(s->irq, true); + } + return; + } + + /* Setup a timer to trigger the interrupt in the future */ + riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0)); + qemu_set_irq(s->irq, false); + + diff = cpu->env.timecmp - now; + next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + muldiv64(diff, + NANOSECONDS_PER_SECOND, + s->timebase_freq); + + if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { + /* We overflowed the timer, just set it as large as we can */ + timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF); + } else { + timer_mod(cpu->env.timer, next); + } +} + +static void ibex_timer_cb(void *opaque) +{ + IbexTimerState *s = opaque; + CPUState *cs = qemu_get_cpu(0); + RISCVCPU *cpu = RISCV_CPU(cs); + + riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); + if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { + s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; + qemu_set_irq(s->irq, true); + } +} + +static void ibex_timer_reset(DeviceState *dev) +{ + IbexTimerState *s = IBEX_TIMER(dev); + + CPUState *cpu = qemu_get_cpu(0); + CPURISCVState *env = cpu->env_ptr; + env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + &ibex_timer_cb, s); + env->timecmp = 0; + + s->timer_ctrl = 0x00000000; + s->timer_cfg0 = 0x00010000; + s->timer_compare_lower0 = 0xFFFFFFFF; + s->timer_compare_upper0 = 0xFFFFFFFF; + s->timer_intr_enable = 0x00000000; + s->timer_intr_state = 0x00000000; + s->timer_intr_test = 0x00000000; + + ibex_timer_update_irqs(s); +} + +static uint64_t ibex_timer_read(void *opaque, hwaddr addr, + unsigned int size) +{ + IbexTimerState *s = opaque; + uint64_t now = cpu_riscv_read_rtc(s->timebase_freq); + uint64_t retvalue = 0; + + switch (addr >> 2) { + case R_CTRL: + retvalue = s->timer_ctrl; + break; + case R_CFG0: + retvalue = s->timer_cfg0; + break; + case R_LOWER0: + retvalue = now; + break; + case R_UPPER0: + retvalue = now >> 32; + break; + case R_COMPARE_LOWER0: + retvalue = s->timer_compare_lower0; + break; + case R_COMPARE_UPPER0: + retvalue = s->timer_compare_upper0; + break; + case R_INTR_ENABLE: + retvalue = s->timer_intr_enable; + break; + case R_INTR_STATE: + retvalue = s->timer_intr_state; + break; + case R_INTR_TEST: + retvalue = s->timer_intr_test; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + return 0; + } + + return retvalue; +} + +static void ibex_timer_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + IbexTimerState *s = opaque; + uint32_t val = val64; + + switch (addr >> 2) { + case R_CTRL: + s->timer_ctrl = val; + break; + case R_CFG0: + qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported"); + s->timer_cfg0 = val; + break; + case R_LOWER0: + qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); + break; + case R_UPPER0: + qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); + break; + case R_COMPARE_LOWER0: + s->timer_compare_lower0 = val; + ibex_timer_update_irqs(s); + break; + case R_COMPARE_UPPER0: + s->timer_compare_upper0 = val; + ibex_timer_update_irqs(s); + break; + case R_INTR_ENABLE: + s->timer_intr_enable = val; + break; + case R_INTR_STATE: + /* Write 1 to clear */ + s->timer_intr_state &= ~val; + break; + case R_INTR_TEST: + s->timer_intr_test = val; + if (s->timer_intr_enable & + s->timer_intr_test & + R_INTR_ENABLE_IE_0_MASK) { + s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; + qemu_set_irq(s->irq, true); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static const MemoryRegionOps ibex_timer_ops = { + .read = ibex_timer_read, + .write = ibex_timer_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, +}; + +static int ibex_timer_post_load(void *opaque, int version_id) +{ + IbexTimerState *s = opaque; + + ibex_timer_update_irqs(s); + return 0; +} + +static const VMStateDescription vmstate_ibex_timer = { + .name = TYPE_IBEX_TIMER, + .version_id = 1, + .minimum_version_id = 1, + .post_load = ibex_timer_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT32(timer_ctrl, IbexTimerState), + VMSTATE_UINT32(timer_cfg0, IbexTimerState), + VMSTATE_UINT32(timer_compare_lower0, IbexTimerState), + VMSTATE_UINT32(timer_compare_upper0, IbexTimerState), + VMSTATE_UINT32(timer_intr_enable, IbexTimerState), + VMSTATE_UINT32(timer_intr_state, IbexTimerState), + VMSTATE_UINT32(timer_intr_test, IbexTimerState), + VMSTATE_END_OF_LIST() + } +}; + +static Property ibex_timer_properties[] = { + DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ibex_timer_init(Object *obj) +{ + IbexTimerState *s = IBEX_TIMER(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s, + TYPE_IBEX_TIMER, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void ibex_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = ibex_timer_reset; + dc->vmsd = &vmstate_ibex_timer; + device_class_set_props(dc, ibex_timer_properties); +} + +static const TypeInfo ibex_timer_info = { + .name = TYPE_IBEX_TIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(IbexTimerState), + .instance_init = ibex_timer_init, + .class_init = ibex_timer_class_init, +}; + +static void ibex_timer_register_types(void) +{ + type_register_static(&ibex_timer_info); +} + +type_init(ibex_timer_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 1a041eaf86..77e4570ea0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1364,11 +1364,9 @@ M: Alistair Francis L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/opentitan.c -F: hw/char/ibex_uart.c -F: hw/intc/ibex_plic.c +F: hw/*/ibex_*.c F: include/hw/riscv/opentitan.h -F: include/hw/char/ibex_uart.h -F: include/hw/intc/ibex_plic.h +F: include/hw/*/ibex_*.h Microchip PolarFire SoC Icicle Kit M: Bin Meng diff --git a/hw/timer/meson.build b/hw/timer/meson.build index 157f540ecd..1aa3cd2284 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -33,5 +33,6 @@ softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c')) softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c')) +specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c')) specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c')) From patchwork Thu Jun 24 12:02:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 12342041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7AE3C49EA5 for ; Thu, 24 Jun 2021 12:03:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2AFC9613DA for ; Thu, 24 Jun 2021 12:03:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2AFC9613DA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:36246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwO5A-000662-BG for qemu-devel@archiver.kernel.org; Thu, 24 Jun 2021 08:03:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54388) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3s-0003VY-Cj for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:25 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:41532) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwO3o-0003pC-3t for qemu-devel@nongnu.org; Thu, 24 Jun 2021 08:02:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1624536140; x=1656072140; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8IPZknxPiBDzoNTxSv+VKq5QZC8E+IqWFDKTchLkUtU=; b=TKqzO73NkVwZzA9BhG/w+KkbuxdKGf9AnDRh4+2svbi1HSphoe7LFVxU 1oIjMKQerGCX1UTR/iDn/rIEvicv2h2FZQ5NlXkmMTz5zSIPziDd8FIZY sYuoBdSBgCB6/vj4zmS30jGbWMCUYPjCpKTQyacxjaV0t0lFvstgZaFG1 q5BvVMZlDHARpYX5K4KBhcTDFo97Id7LetuFXPdBnmhFXZVzQto3B8aO+ ytJrlR1aviJ35pYZSROncUE/2l4X9fzva5pnXaJJTHtJKp/o2ky+b2AN0 WA4KHT8kKPIZroGHAiO1aYQFLVA4BNVIpCWClgeQoUvUQUz2l+cw6sZHv Q==; IronPort-SDR: 5Z2Q8UtUxGq0G8Husp/8nwGPt7zqsk51k7wIKXBgA70kFTDfgqpRPgoxX6HesWFcqeMzQSgiBB 8zlWWeMfrsq7LCYRlk8g2L7TQvqkl1sHzrKHfpzV9zALCWQA9Cibob9fjnHyYq+5OvryEDQJGs 6zyTh2UwYA9Ue5rkskyCUFVVqDxqOUK0sxtqrDFYf2bwh29yFAiGkaopGpMHHNHKJzkgoEr/IP lVzwrITdxToVTdBiAXo9GyPoBgnctd0TnjntQOQAAAOsFZQqIxzjLNbKKcq3kE+OaXDAucwRcg EKA= X-IronPort-AV: E=Sophos;i="5.83,296,1616428800"; d="scan'208";a="284269191" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 24 Jun 2021 20:02:15 +0800 IronPort-SDR: 3uDTDCMFegpo+mtHRECaPsb3lReIGPWGUBuLLs+DBnBhmVovYY+EDnKnyGGCHQMivtL91IG1Eq /CXAhVSfdfRbRLZntecPiqVWnHxRNF1DaJCRs5MgYrwqTf7Zrri5dTgrZpw4N1ynWUJWjBJ8dG xOgmN0VB9KcnU1Gq6XnyGRO0bIc7odq8Vo1QDMGNeIlBiCOm7+DNiFzlbXrgFazeoGqS2cACzJ nCLMOmoy3iyYI7BrAm9HUD8MX1jJBiJ6lX3PtOl9gNfKC5sNKUT+koD3hPpRWf/iPPckEecut9 L2Wi+qN02S7T7olQvU5IDnxC Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2021 04:40:50 -0700 IronPort-SDR: goeMpz0zUBJ8YeLo6lIYJW3GOklly4nRtgi/U8wgQ+dcCjq8IeAjKN1hB0ewfWfaLYtlJuBw9T vfx6qNgANzGq7DTM7e0duPKu0qmlPERMhfBdH0tGQUvg/Qiy8tzTL4e9STf632JtasaOaZNcYR L13UBOH80nGFTh5XLpqhU5459B+12B5K6D4s393Flc3BWL2JboXXLFZhtLEsY5W7vIFR0p1kjf muYxAJmTAVIWq3cw2aM5m8ZhNOl/MceD/pjHaGGB9u01V/W+vjqiI6l+2j0bx0E8EjARjimQFT QPs= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip02.wdc.com with ESMTP; 24 Jun 2021 05:02:16 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Date: Thu, 24 Jun 2021 05:02:11 -0700 Message-Id: <20210624120211.85499-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com> References: <20210624120211.85499-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=802348aeb=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Connect the Ibex timer to the OpenTitan machine. The timer can trigger the RISC-V MIE interrupt as well as a custom device interrupt. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com --- include/hw/riscv/opentitan.h | 5 ++++- hw/riscv/opentitan.c | 14 +++++++++++--- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index aab9bc9245..86cceef698 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -22,6 +22,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/intc/ibex_plic.h" #include "hw/char/ibex_uart.h" +#include "hw/timer/ibex_timer.h" #include "qom/object.h" #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" @@ -35,6 +36,7 @@ struct LowRISCIbexSoCState { RISCVHartArrayState cpus; IbexPlicState plic; IbexUartState uart; + IbexTimerState timer; MemoryRegion flash_mem; MemoryRegion rom; @@ -57,7 +59,7 @@ enum { IBEX_DEV_SPI, IBEX_DEV_I2C, IBEX_DEV_PATTGEN, - IBEX_DEV_RV_TIMER, + IBEX_DEV_TIMER, IBEX_DEV_SENSOR_CTRL, IBEX_DEV_OTP_CTRL, IBEX_DEV_PWRMGR, @@ -82,6 +84,7 @@ enum { }; enum { + IBEX_TIMER_TIMEREXPIRED0_0 = 125, IBEX_UART0_RX_PARITY_ERR_IRQ = 8, IBEX_UART0_RX_TIMEOUT_IRQ = 7, IBEX_UART0_RX_BREAK_ERR_IRQ = 6, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 7545dcda9c..c5a7e3bacb 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -36,7 +36,7 @@ static const MemMapEntry ibex_memmap[] = { [IBEX_DEV_SPI] = { 0x40050000, 0x1000 }, [IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, - [IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 }, + [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 }, [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 }, [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, @@ -106,6 +106,8 @@ static void lowrisc_ibex_soc_init(Object *obj) object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC); object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); + + object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); } static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) @@ -159,6 +161,14 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 3, qdev_get_gpio_in(DEVICE(&s->plic), IBEX_UART0_RX_OVERFLOW_IRQ)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), + 0, qdev_get_gpio_in(DEVICE(&s->plic), + IBEX_TIMER_TIMEREXPIRED0_0)); + create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); create_unimplemented_device("riscv.lowrisc.ibex.spi", @@ -167,8 +177,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); create_unimplemented_device("riscv.lowrisc.ibex.pattgen", memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); - create_unimplemented_device("riscv.lowrisc.ibex.rv_timer", - memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size); create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",