From patchwork Thu Jun 24 18:41:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12342875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5F8EC49EA5 for ; Thu, 24 Jun 2021 18:41:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9E87B613FD for ; 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Thu, 24 Jun 2021 13:41:17 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 24 Jun 2021 13:41:16 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Thu, 24 Jun 2021 13:41:16 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 15OIf9Hw041395; Thu, 24 Jun 2021 13:41:14 -0500 From: Pratyush Yadav To: Vinod Koul CC: Nikhil Devshatwar , Tomi Valkeinen , Laurent Pinchart , Paul Kocialkowski , Vignesh Raghavendra , Pratyush Yadav , Kishon Vijay Abraham I , , Subject: [PATCH v3 1/7] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes Date: Fri, 25 Jun 2021 00:11:02 +0530 Message-ID: <20210624184108.21312-2-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624184108.21312-1-p.yadav@ti.com> References: <20210624184108.21312-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210624_114127_591555_1B75A9F1 X-CRM114-Status: GOOD ( 10.23 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Paul Kocialkowski As some D-PHY controllers support both Rx and Tx mode, we need a way for users to explicitly request one or the other. For instance, Rx mode can be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI. Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY. The default (zero value) is kept to Tx so only the rkisp1 driver, which uses D-PHY in Rx mode, needs to be adapted. Signed-off-by: Paul Kocialkowski Signed-off-by: Pratyush Yadav --- (no changes since v1) include/linux/phy/phy-mipi-dphy.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h index a877ffee845d..0f57ef46a8b5 100644 --- a/include/linux/phy/phy-mipi-dphy.h +++ b/include/linux/phy/phy-mipi-dphy.h @@ -6,6 +6,19 @@ #ifndef __PHY_MIPI_DPHY_H_ #define __PHY_MIPI_DPHY_H_ +/** + * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode + * + * A MIPI D-PHY can be used to transmit or receive data. + * Since some controllers can support both, the direction to enable is specified + * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode. + */ + +enum phy_mipi_dphy_submode { + PHY_MIPI_DPHY_SUBMODE_TX = 0, + PHY_MIPI_DPHY_SUBMODE_RX, +}; + /** * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set * From patchwork Thu Jun 24 18:41:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12342877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17CDBC49EA7 for ; Thu, 24 Jun 2021 18:41:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C9053613FE for ; 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Thu, 24 Jun 2021 13:41:20 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 24 Jun 2021 13:41:20 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Thu, 24 Jun 2021 13:41:20 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 15OIf9Hx041395; Thu, 24 Jun 2021 13:41:17 -0500 From: Pratyush Yadav To: Vinod Koul CC: Nikhil Devshatwar , Tomi Valkeinen , Laurent Pinchart , Paul Kocialkowski , Vignesh Raghavendra , Pratyush Yadav , Chunfeng Yun , Kishon Vijay Abraham I , Peter Chen , , Subject: [PATCH v3 2/7] phy: cdns-dphy: Prepare for Rx support Date: Fri, 25 Jun 2021 00:11:03 +0530 Message-ID: <20210624184108.21312-3-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624184108.21312-1-p.yadav@ti.com> References: <20210624184108.21312-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210624_114127_636881_593BF0F8 X-CRM114-Status: GOOD ( 19.21 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The Rx programming sequence differs from the Tx programming sequence. Currently only Tx mode is supported. Move all the Tx related parts into a set of Tx-specific hooks that are then called by the main PHY framework hooks. This way when Rx support is added all that is needed to be done is to plug in the Rx hooks. The clocks "psm" and "pll_ref" are not used by the Rx path so make them optional in the probe and then check if they exist in the power_on() hook. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/phy/cadence/cdns-dphy.c | 140 ++++++++++++++++++++++++-------- 1 file changed, 104 insertions(+), 36 deletions(-) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index ba042e39cfaf..8656f2102a91 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -75,6 +75,11 @@ struct cdns_dphy; struct cdns_dphy_ops { int (*probe)(struct cdns_dphy *dphy); void (*remove)(struct cdns_dphy *dphy); + int (*power_on)(struct cdns_dphy *dphy); + int (*power_off)(struct cdns_dphy *dphy); + int (*validate)(struct cdns_dphy *dphy, enum phy_mode mode, int submode, + union phy_configure_opts *opts); + int (*configure)(struct cdns_dphy *dphy, union phy_configure_opts *opts); void (*set_psm_div)(struct cdns_dphy *dphy, u8 div); void (*set_clk_lane_cfg)(struct cdns_dphy *dphy, enum cdns_dphy_clk_lane_cfg cfg); @@ -86,12 +91,18 @@ struct cdns_dphy_ops { struct cdns_dphy { struct cdns_dphy_cfg cfg; void __iomem *regs; + struct device *dev; struct clk *psm_clk; struct clk *pll_ref_clk; const struct cdns_dphy_ops *ops; struct phy *phy; }; +struct cdns_dphy_driver_data { + const struct cdns_dphy_ops *tx; + const struct cdns_dphy_ops *rx; +}; + static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, struct cdns_dphy_cfg *cfg, struct phy_configure_opts_mipi_dphy *opts, @@ -199,20 +210,9 @@ static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div) dphy->regs + DPHY_PSM_CFG); } -/* - * This is the reference implementation of DPHY hooks. Specific integration of - * this IP may have to re-implement some of them depending on how they decided - * to wire things in the SoC. - */ -static const struct cdns_dphy_ops ref_dphy_ops = { - .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns, - .set_pll_cfg = cdns_dphy_ref_set_pll_cfg, - .set_psm_div = cdns_dphy_ref_set_psm_div, -}; - -static int cdns_dphy_config_from_opts(struct phy *phy, - struct phy_configure_opts_mipi_dphy *opts, - struct cdns_dphy_cfg *cfg) +static int cdns_dphy_tx_config_from_opts(struct phy *phy, + struct phy_configure_opts_mipi_dphy *opts, + struct cdns_dphy_cfg *cfg) { struct cdns_dphy *dphy = phy_get_drvdata(phy); unsigned int dsi_hfp_ext = 0; @@ -232,24 +232,13 @@ static int cdns_dphy_config_from_opts(struct phy *phy, return 0; } -static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, - union phy_configure_opts *opts) +static int cdns_dphy_tx_configure(struct cdns_dphy *dphy, + union phy_configure_opts *opts) { struct cdns_dphy_cfg cfg = { 0 }; - - if (mode != PHY_MODE_MIPI_DPHY) - return -EINVAL; - - return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); -} - -static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) -{ - struct cdns_dphy *dphy = phy_get_drvdata(phy); - struct cdns_dphy_cfg cfg = { 0 }; int ret; - ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); + ret = cdns_dphy_tx_config_from_opts(dphy->phy, &opts->mipi_dphy, &cfg); if (ret) return ret; @@ -279,9 +268,21 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) return 0; } -static int cdns_dphy_power_on(struct phy *phy) +static int cdns_dphy_tx_validate(struct cdns_dphy *dphy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) { - struct cdns_dphy *dphy = phy_get_drvdata(phy); + struct cdns_dphy_cfg cfg = { 0 }; + + if (submode != PHY_MIPI_DPHY_SUBMODE_TX) + return -EINVAL; + + return cdns_dphy_tx_config_from_opts(dphy->phy, &opts->mipi_dphy, &cfg); +} + +static int cdns_dphy_tx_power_on(struct cdns_dphy *dphy) +{ + if (!dphy->psm_clk || !dphy->pll_ref_clk) + return -EINVAL; clk_prepare_enable(dphy->psm_clk); clk_prepare_enable(dphy->pll_ref_clk); @@ -293,16 +294,77 @@ static int cdns_dphy_power_on(struct phy *phy) return 0; } -static int cdns_dphy_power_off(struct phy *phy) +static int cdns_dphy_tx_power_off(struct cdns_dphy *dphy) { - struct cdns_dphy *dphy = phy_get_drvdata(phy); - clk_disable_unprepare(dphy->pll_ref_clk); clk_disable_unprepare(dphy->psm_clk); return 0; } +static const struct cdns_dphy_ops tx_ref_dphy_ops = { + .power_on = cdns_dphy_tx_power_on, + .power_off = cdns_dphy_tx_power_off, + .validate = cdns_dphy_tx_validate, + .configure = cdns_dphy_tx_configure, + .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns, + .set_pll_cfg = cdns_dphy_ref_set_pll_cfg, + .set_psm_div = cdns_dphy_ref_set_psm_div, +}; + +/* + * This is the reference implementation of DPHY hooks. Specific integration of + * this IP may have to re-implement some of them depending on how they decided + * to wire things in the SoC. + */ +static const struct cdns_dphy_driver_data ref_dphy_ops = { + .tx = &tx_ref_dphy_ops, +}; + +static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, + union phy_configure_opts *opts) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + if (dphy->ops->validate) + return dphy->ops->validate(dphy, mode, submode, opts); + + return 0; +} + +static int cdns_dphy_power_on(struct phy *phy) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->power_on) + return dphy->ops->power_on(dphy); + + return 0; +} + +static int cdns_dphy_power_off(struct phy *phy) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->power_off) + return dphy->ops->power_off(dphy); + + return 0; +} + +static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->configure) + return dphy->ops->configure(dphy, opts); + + return 0; +} + static const struct phy_ops cdns_dphy_ops = { .configure = cdns_dphy_configure, .validate = cdns_dphy_validate, @@ -314,14 +376,20 @@ static int cdns_dphy_probe(struct platform_device *pdev) { struct phy_provider *phy_provider; struct cdns_dphy *dphy; + const struct cdns_dphy_driver_data *ddata; int ret; dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); if (!dphy) return -ENOMEM; dev_set_drvdata(&pdev->dev, dphy); + dphy->dev = &pdev->dev; - dphy->ops = of_device_get_match_data(&pdev->dev); + ddata = of_device_get_match_data(&pdev->dev); + if (!ddata) + return -EINVAL; + + dphy->ops = ddata->tx; if (!dphy->ops) return -EINVAL; @@ -329,11 +397,11 @@ static int cdns_dphy_probe(struct platform_device *pdev) if (IS_ERR(dphy->regs)) return PTR_ERR(dphy->regs); - dphy->psm_clk = devm_clk_get(&pdev->dev, "psm"); + dphy->psm_clk = devm_clk_get_optional(dphy->dev, "psm"); if (IS_ERR(dphy->psm_clk)) return PTR_ERR(dphy->psm_clk); - dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref"); + dphy->pll_ref_clk = devm_clk_get_optional(dphy->dev, "pll_ref"); if (IS_ERR(dphy->pll_ref_clk)) return PTR_ERR(dphy->pll_ref_clk); From patchwork Thu Jun 24 18:41:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12342881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DED5C49EA5 for ; Thu, 24 Jun 2021 18:41:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 30AC8613FD for ; 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Thu, 24 Jun 2021 13:41:24 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 24 Jun 2021 13:41:24 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Thu, 24 Jun 2021 13:41:23 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 15OIf9I0041395; Thu, 24 Jun 2021 13:41:21 -0500 From: Pratyush Yadav To: Vinod Koul CC: Nikhil Devshatwar , Tomi Valkeinen , Laurent Pinchart , Paul Kocialkowski , Vignesh Raghavendra , Pratyush Yadav , Chunfeng Yun , Kishon Vijay Abraham I , Peter Chen , , Subject: [PATCH v3 3/7] phy: cdns-dphy: Allow setting mode Date: Fri, 25 Jun 2021 00:11:04 +0530 Message-ID: <20210624184108.21312-4-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624184108.21312-1-p.yadav@ti.com> References: <20210624184108.21312-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210624_114129_569929_84928E1E X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Allow callers to set the PHY mode. The main mode should always be PHY_MODE_MIPI_DPHY but the submode can either be PHY_MIPI_DPHY_SUBMODE_RX or PHY_MIPI_DPHY_SUBMODE_TX. Update the ops based on the requested submode. Signed-off-by: Pratyush Yadav --- (no changes since v1) drivers/phy/cadence/cdns-dphy.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index 8656f2102a91..7d5f7b333893 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -365,11 +365,41 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) return 0; } +static int cdns_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + const struct cdns_dphy_driver_data *ddata; + + ddata = of_device_get_match_data(dphy->dev); + if (!ddata) + return -EINVAL; + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + if (submode == PHY_MIPI_DPHY_SUBMODE_TX) { + if (!ddata->tx) + return -EOPNOTSUPP; + + dphy->ops = ddata->tx; + } else if (submode == PHY_MIPI_DPHY_SUBMODE_RX) { + if (!ddata->rx) + return -EOPNOTSUPP; + + dphy->ops = ddata->rx; + } else { + return -EOPNOTSUPP; + } + + return 0; +} + static const struct phy_ops cdns_dphy_ops = { .configure = cdns_dphy_configure, .validate = cdns_dphy_validate, .power_on = cdns_dphy_power_on, .power_off = cdns_dphy_power_off, + .set_mode = cdns_dphy_set_mode, }; static int cdns_dphy_probe(struct platform_device *pdev) From patchwork Thu Jun 24 18:41:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12342883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6380C49EA5 for ; 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Thu, 24 Jun 2021 13:41:24 -0500 From: Pratyush Yadav To: Vinod Koul CC: Nikhil Devshatwar , Tomi Valkeinen , Laurent Pinchart , Paul Kocialkowski , Vignesh Raghavendra , Pratyush Yadav , Chunfeng Yun , Kishon Vijay Abraham I , Peter Chen , , Subject: [PATCH v3 4/7] phy: cdns-dphy: Add Rx support Date: Fri, 25 Jun 2021 00:11:05 +0530 Message-ID: <20210624184108.21312-5-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624184108.21312-1-p.yadav@ti.com> References: <20210624184108.21312-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210624_114132_596187_9695026D X-CRM114-Status: GOOD ( 23.71 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The Cadence DPHY can be used to receive image data over the CSI-2 protocol. Add support for Rx mode. The programming sequence differs from the Tx mode so it is added as a separate set of hooks to isolate the two paths. The PHY is in Tx mode by default and it needs to be set in Rx mode by setting the submode to PHY_MIPI_DPHY_SUBMODE_RX in the set_mode() callback. Signed-off-by: Pratyush Yadav --- Changes in v3: - Use a table to select the band. - Use a table to poll the data lane ready bits. - Multiply the DPHY HS clock rate by 2 to get the bit rate since the clock is DDR. drivers/phy/cadence/cdns-dphy.c | 174 ++++++++++++++++++++++++++++++++ 1 file changed, 174 insertions(+) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index 7d5f7b333893..7534ec957dc5 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright: 2017-2018 Cadence Design Systems, Inc. + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include +#include #include #include +#include #include #include #include @@ -25,10 +28,14 @@ #define DPHY_PMA_RCLK(reg) (0x600 + (reg)) #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg)) #define DPHY_PCS(reg) (0xb00 + (reg)) +#define DPHY_ISO(reg) (0xc00 + (reg)) #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) #define DPHY_CMN_SSM_EN BIT(0) +#define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1) #define DPHY_CMN_TX_MODE_EN BIT(9) +#define DPHY_CMN_RX_MODE_EN BIT(10) +#define DPHY_CMN_RX_BANDGAP_TIMER 0x14 #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) #define DPHY_CMN_PWM_DIV(x) ((x) << 20) @@ -45,10 +52,27 @@ #define DPHY_CMN_OPDIV_FROM_REG BIT(6) #define DPHY_CMN_OPDIV(x) ((x) << 7) +#define DPHY_BAND_CFG DPHY_PCS(0x0) +#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) +#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) + #define DPHY_PSM_CFG DPHY_PCS(0x4) #define DPHY_PSM_CFG_FROM_REG BIT(0) #define DPHY_PSM_CLK_DIV(x) ((x) << 1) +#define DPHY_POWER_ISLAND_EN_DATA DPHY_PCS(0x8) +#define DPHY_POWER_ISLAND_EN_DATA_VAL 0xaaaaaaaa +#define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc) +#define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa + +#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10) +#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14) +#define DPHY_ISO_DL_CTRL_L1 DPHY_ISO(0x20) +#define DPHY_ISO_DL_CTRL_L2 DPHY_ISO(0x30) +#define DPHY_ISO_DL_CTRL_L3 DPHY_ISO(0x3c) +#define DPHY_ISO_LANE_READY_BIT 0 +#define DPHY_ISO_LANE_READY_TIMEOUT_MS 100UL + #define DSI_HBP_FRAME_OVERHEAD 12 #define DSI_HSA_FRAME_OVERHEAD 14 #define DSI_HFP_FRAME_OVERHEAD 6 @@ -57,6 +81,9 @@ #define DSI_NULL_FRAME_OVERHEAD 6 #define DSI_EOT_PKT_SIZE 4 +#define DPHY_LANES_MIN 1 +#define DPHY_LANES_MAX 4 + struct cdns_dphy_cfg { u8 pll_ipdiv; u8 pll_opdiv; @@ -103,6 +130,22 @@ struct cdns_dphy_driver_data { const struct cdns_dphy_ops *rx; }; +struct cdns_dphy_rx_band { + unsigned int min_rate; + unsigned int max_rate; +}; + +/* Order of bands is important since the index is the band number. */ +struct cdns_dphy_rx_band bands[] = { + {80, 100}, {100, 120}, {120, 160}, {160, 200}, {200, 240}, + {240, 280}, {280, 320}, {320, 360}, {360, 400}, {400, 480}, + {480, 560}, {560, 640}, {640, 720}, {720, 800}, {800, 880}, + {880, 1040}, {1040, 1200}, {1200, 1350}, {1350, 1500}, {1500, 1750}, + {1750, 2000}, {2000, 2250}, {2250, 2500} +}; + +int num_bands = ARRAY_SIZE(bands); + static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, struct cdns_dphy_cfg *cfg, struct phy_configure_opts_mipi_dphy *opts, @@ -312,6 +355,135 @@ static const struct cdns_dphy_ops tx_ref_dphy_ops = { .set_psm_div = cdns_dphy_ref_set_psm_div, }; +static int cdns_dphy_rx_power_on(struct cdns_dphy *dphy) +{ + /* Start RX state machine. */ + writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN | + FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK, + DPHY_CMN_RX_BANDGAP_TIMER), + dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_power_off(struct cdns_dphy *dphy) +{ + writel(0, dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate) +{ + unsigned int rate; + int i; + + rate = hs_clk_rate / 1000000UL; + /* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */ + rate *= 2; + + if (rate < bands[0].min_rate || rate >= bands[num_bands - 1].max_rate) + return -EOPNOTSUPP; + + for (i = 0; i < num_bands; i++) { + if (rate >= bands[i].min_rate && rate < bands[i].max_rate) + return i; + } + + /* Unreachable. */ + WARN(1, "Reached unreachable code."); + return -EINVAL; +} + +static int cdns_dphy_rx_wait_for_bit(void __iomem *addr, unsigned int bit) +{ + u32 val; + + return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10, + DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000); +} + +static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy *dphy, int lanes) +{ + void __iomem *reg = dphy->regs; + u32 data_lane_ctrl[] = {DPHY_ISO_DL_CTRL_L0, DPHY_ISO_DL_CTRL_L1, + DPHY_ISO_DL_CTRL_L2, DPHY_ISO_DL_CTRL_L3}; + int ret, i; + + /* Data lanes. Minimum one lane is mandatory. */ + if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) + return -EINVAL; + + /* Clock lane */ + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + for (i = 0; i < lanes; i++) { + ret = cdns_dphy_rx_wait_for_bit(reg + data_lane_ctrl[i], + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + } + + return 0; +} + +static int cdns_dphy_rx_configure(struct cdns_dphy *dphy, + union phy_configure_opts *opts) +{ + unsigned int reg; + int band_ctrl, ret; + + band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (band_ctrl < 0) + return band_ctrl; + + reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | + FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); + writel(reg, dphy->regs + DPHY_BAND_CFG); + + /* + * Set the required power island phase 2 time. This is mandated by DPHY + * specs. + */ + reg = DPHY_POWER_ISLAND_EN_DATA_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA); + reg = DPHY_POWER_ISLAND_EN_CLK_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK); + + ret = cdns_dphy_rx_wait_lane_ready(dphy, opts->mipi_dphy.lanes); + if (ret) { + dev_err(dphy->dev, "DPHY wait for lane ready timeout\n"); + return ret; + } + + return 0; +} + +static int cdns_dphy_rx_validate(struct cdns_dphy *dphy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) +{ + int ret; + + if (submode != PHY_MIPI_DPHY_SUBMODE_RX) + return -EINVAL; + + ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (ret < 0) + return ret; + + return phy_mipi_dphy_config_validate(&opts->mipi_dphy); +} + +static const struct cdns_dphy_ops rx_ref_dphy_ops = { + .power_on = cdns_dphy_rx_power_on, + .power_off = cdns_dphy_rx_power_off, + .configure = cdns_dphy_rx_configure, + .validate = cdns_dphy_rx_validate, +}; + /* * This is the reference implementation of DPHY hooks. Specific integration of * this IP may have to re-implement some of them depending on how they decided @@ -319,6 +491,7 @@ static const struct cdns_dphy_ops tx_ref_dphy_ops = { */ static const struct cdns_dphy_driver_data ref_dphy_ops = { .tx = &tx_ref_dphy_ops, + .rx = &rx_ref_dphy_ops, }; static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, @@ -483,5 +656,6 @@ static struct platform_driver cdns_dphy_platform_driver = { module_platform_driver(cdns_dphy_platform_driver); MODULE_AUTHOR("Maxime Ripard "); +MODULE_AUTHOR("Pratyush Yadav "); MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver"); MODULE_LICENSE("GPL"); From patchwork Thu Jun 24 18:41:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12342885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D106C49EAF for ; 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Thu, 24 Jun 2021 13:41:28 -0500 From: Pratyush Yadav To: Vinod Koul CC: Nikhil Devshatwar , Tomi Valkeinen , Laurent Pinchart , Paul Kocialkowski , Vignesh Raghavendra , Pratyush Yadav , Kishon Vijay Abraham I , Rob Herring , , , Subject: [PATCH v3 5/7] phy: dt-bindings: Convert Cadence DPHY binding to YAML Date: Fri, 25 Jun 2021 00:11:06 +0530 Message-ID: <20210624184108.21312-6-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624184108.21312-1-p.yadav@ti.com> References: <20210624184108.21312-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210624_114136_050648_893DDBF6 X-CRM114-Status: GOOD ( 14.41 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Convert Cadence DPHY binding to YAML. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart Reviewed-by: Rob Herring --- Changes in v3: - Add Rob's R-by. Changes in v2: - Drop reg description. - Add a description for each DPHY clock. - Rename dphy@... to phy@... in example. - Add Laurent's R-by. - Re-order subject prefixes. .../devicetree/bindings/phy/cdns,dphy.txt | 20 -------- .../devicetree/bindings/phy/cdns,dphy.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt deleted file mode 100644 index 1095bc4e72d9..000000000000 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.txt +++ /dev/null @@ -1,20 +0,0 @@ -Cadence DPHY -============ - -Cadence DPHY block. - -Required properties: -- compatible: should be set to "cdns,dphy". -- reg: physical base address and length of the DPHY registers. -- clocks: DPHY reference clocks. -- clock-names: must contain "psm" and "pll_ref". -- #phy-cells: must be set to 0. - -Example: - dphy0: dphy@fd0e0000{ - compatible = "cdns,dphy"; - reg = <0x0 0xfd0e0000 0x0 0x1000>; - clocks = <&psm_clk>, <&pll_ref_clk>; - clock-names = "psm", "pll_ref"; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml new file mode 100644 index 000000000000..b90a58773bf2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DPHY Device Tree Bindings + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: cdns,dphy + + reg: + maxItems: 1 + + clocks: + items: + - description: PMA state machine clock + - description: PLL reference clock + + clock-names: + items: + - const: psm + - const: pll_ref + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + + dphy0: phy@fd0e0000{ + compatible = "cdns,dphy"; + reg = <0xfd0e0000 0x1000>; + clocks = <&psm_clk>, <&pll_ref_clk>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + }; From patchwork Thu Jun 24 18:41:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12342887 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F27B8C49EA6 for ; Thu, 24 Jun 2021 18:41:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A85C96142C for ; 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Thu, 24 Jun 2021 13:41:35 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 24 Jun 2021 13:41:35 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Thu, 24 Jun 2021 13:41:35 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 15OIf9I3041395; Thu, 24 Jun 2021 13:41:32 -0500 From: Pratyush Yadav To: Vinod Koul CC: Nikhil Devshatwar , Tomi Valkeinen , Laurent Pinchart , Paul Kocialkowski , Vignesh Raghavendra , Pratyush Yadav , Kishon Vijay Abraham I , Rob Herring , , , Subject: [PATCH v3 6/7] phy: dt-bindings: cdns,dphy: make clocks optional Date: Fri, 25 Jun 2021 00:11:07 +0530 Message-ID: <20210624184108.21312-7-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624184108.21312-1-p.yadav@ti.com> References: <20210624184108.21312-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210624_114139_380151_C10191E9 X-CRM114-Status: UNSURE ( 8.28 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The clocks are not used by the DPHY when used in Rx mode so make them optional. Signed-off-by: Pratyush Yadav Acked-by: Rob Herring --- Changes in v3: - Add Rob's Ack. Changes in v2: - Re-order subject prefixes. Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index b90a58773bf2..3bb5be05e825 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -33,8 +33,6 @@ properties: required: - compatible - reg - - clocks - - clock-names - "#phy-cells" additionalProperties: false From patchwork Thu Jun 24 18:41:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12342889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4040C49EA6 for ; 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Thu, 24 Jun 2021 13:41:39 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 15OIf9I4041395; Thu, 24 Jun 2021 13:41:35 -0500 From: Pratyush Yadav To: Vinod Koul CC: Nikhil Devshatwar , Tomi Valkeinen , Laurent Pinchart , Paul Kocialkowski , Vignesh Raghavendra , Pratyush Yadav , Kishon Vijay Abraham I , Rob Herring , , , Subject: [PATCH v3 7/7] phy: dt-bindings: cdns, dphy: add power-domains property Date: Fri, 25 Jun 2021 00:11:08 +0530 Message-ID: <20210624184108.21312-8-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210624184108.21312-1-p.yadav@ti.com> References: <20210624184108.21312-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210624_114143_447736_5A86F8B3 X-CRM114-Status: UNSURE ( 8.93 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This property is needed on TI platforms to enable the PD of the DPHY before it can be used. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart Acked-by: Rob Herring --- Changes in v3: - Add Rob's Ack. Changes in v2: - Add power-domain to the example. - Add Laurent's R-by. - Re-order subject prefixes. Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index 3bb5be05e825..d5a5e1f0b671 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -30,6 +30,9 @@ properties: "#phy-cells": const: 0 + power-domains: + maxItems: 1 + required: - compatible - reg @@ -39,11 +42,13 @@ additionalProperties: false examples: - | + #include dphy0: phy@fd0e0000{ compatible = "cdns,dphy"; reg = <0xfd0e0000 0x1000>; clocks = <&psm_clk>, <&pll_ref_clk>; clock-names = "psm", "pll_ref"; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; #phy-cells = <0>; };