From patchwork Fri Jun 25 07:42:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Hundeb=C3=B8ll?= X-Patchwork-Id: 12343921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9672C49EAF for ; Fri, 25 Jun 2021 07:42:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 929D661426 for ; Fri, 25 Jun 2021 07:42:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230010AbhFYHpI (ORCPT ); Fri, 25 Jun 2021 03:45:08 -0400 Received: from first.geanix.com ([116.203.34.67]:34902 "EHLO first.geanix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229616AbhFYHpI (ORCPT ); Fri, 25 Jun 2021 03:45:08 -0400 Received: from zen.. (unknown [185.17.218.86]) by first.geanix.com (Postfix) with ESMTPSA id 3EE7A4C41BE; Fri, 25 Jun 2021 07:42:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=geanix.com; s=first; t=1624606965; bh=I4CaXQmrIoZGKkHneB3jqMMq5ESOCyFcDhfuGZWM4N0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Y/AEmpr4z+Vr+2ydH0NnwaAM3m5bu8dZ0dPyx6XR2TlM+aSEfyI1m/jTyRb/TLV9E JXNkcyjASYvQa0oxdLBy6Kp67/tOiPSkojTZk8iAbD6/sNecLLmVtK/JyknfmCo9LN Tmss7MYjzRQc4Axj9P3pasi8CxZFJG1MpF1/+90d+4TWUSEMVT1xAmNdarohK2jNS0 9aUgDbh7yBMriGRZq1UPPryLP4T0encp1yNm7tdB2V4xm0xue7qGc19iOh/3zZg4Uo pnp/1d57VmzNnqOTx06C9CzQJGZOfSabdzbrrqzU21YghVoUskGQZlUIwVO8bta9TJ S80XzdohQUbcQ== From: =?utf-8?q?Martin_Hundeb=C3=B8ll?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , Jean Delvare , Guenter Roeck , Lee Jones , Mark Brown Cc: =?utf-8?q?Martin_Hundeb=C3=B8ll?= , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org Subject: [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards Date: Fri, 25 Jun 2021 09:42:09 +0200 Message-Id: <20210625074213.654274-2-martin@geanix.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210625074213.654274-1-martin@geanix.com> References: <20210625074213.654274-1-martin@geanix.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Martin Hundebøll This adds the approved PCI Express Device IDs for the Silicom PAC N5010 and N5011 cards (aka. Silicom Lightning Creek cards). The N5010 features an FPGA that manages/interfaces four QSFP ports, and allows on-board custom packet processing/filtering/routing, based on logic loaded with user-provided FPGA bitstreams. The N5011 cards adds a PCIe switch that exposes, in addition to the FPGA itself, two Intel E810 (aka Columbiaville) ethernet controllers. With this, packets can be forwarded from the FPGA to the host for further processing. Signed-off-by: Martin Hundebøll Acked-by: Wu Hao --- Changes since v1: * Commit message is updated with card description * Added Hao's Acked-by drivers/fpga/dfl-pci.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index b44523ea8c91..4d68719e608f 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -74,6 +74,9 @@ static void cci_pci_free_irq(struct pci_dev *pcidev) #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4 #define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30 #define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B +#define PCIE_DEVICE_ID_SILICOM_PAC_N5010 0x1000 +#define PCIE_DEVICE_ID_SILICOM_PAC_N5011 0x1001 + /* VF Device */ #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1 @@ -90,6 +93,8 @@ static struct pci_device_id cci_pcie_id_tbl[] = { {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),}, {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),}, {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),}, + {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),}, + {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),}, {0,} }; MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl); From patchwork Fri Jun 25 07:42:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Hundeb=C3=B8ll?= X-Patchwork-Id: 12343923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B55AAC2B9F4 for ; Fri, 25 Jun 2021 07:42:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 946BA61425 for ; Fri, 25 Jun 2021 07:42:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230032AbhFYHpJ (ORCPT ); Fri, 25 Jun 2021 03:45:09 -0400 Received: from first.geanix.com ([116.203.34.67]:34920 "EHLO first.geanix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbhFYHpJ (ORCPT ); Fri, 25 Jun 2021 03:45:09 -0400 Received: from zen.. (unknown [185.17.218.86]) by first.geanix.com (Postfix) with ESMTPSA id 72A204C41C1; Fri, 25 Jun 2021 07:42:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=geanix.com; s=first; t=1624606966; bh=X8roa3GuawxUKfdPK2iIp5BV1M0ebt6KSUxD3FXNSOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=joPtKVO+6JevAg9tjBjmtFI3nlHDmGYrk01SO+jKdAGj1w+KqQ08Al8lR6UlWRQ/Y 2LLkO7tyeMflG9QJxkRlyrX11apFuzM9gxgMVkrPVTQJKRbwm9zubQF+/EpFNnqaow MFu3CXdoq2RWxxMtTHJbXDaZbCug8Qj6BWA1e5O6T1Zapn/RB8v9vkORVrnT9oAQjX 5LJGWjd+XfKG2F+LsxqvutMXIbhhunC8xy2qKLBxV224zcwHmKaHAql6Jpw8/7XDAB B/lX8jEjYPyvbJ2A1zAtVVPrEFm3ncq7YWXZ/VHtIi7qtdSg1gOw6XL0LUKfub50ov G1sY4PWOMUcQg== From: =?utf-8?q?Martin_Hundeb=C3=B8ll?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , Jean Delvare , Guenter Roeck , Lee Jones , Mark Brown Cc: =?utf-8?q?Martin_Hundeb=C3=B8ll?= , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org Subject: [PATCH v2 2/5] fpga: dfl: expose feature revision from struct dfl_device Date: Fri, 25 Jun 2021 09:42:10 +0200 Message-Id: <20210625074213.654274-3-martin@geanix.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210625074213.654274-1-martin@geanix.com> References: <20210625074213.654274-1-martin@geanix.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Martin Hundebøll Drivers can make use of the feature field from the DFL header, but shouldn't know about the header structure. To avoid exposing such info, and to reduce the number of reads from the io-mem, the revision is added to struct dfl_device. Signed-off-by: Martin Hundebøll --- Changes since v1: * This patch replaces the previous patch 2 and exposes the feature revision through struct dfl_device instead of a helper reading from io-mem drivers/fpga/dfl.c | 27 +++++++++++++++++---------- drivers/fpga/dfl.h | 1 + include/linux/dfl.h | 1 + 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 511b20ff35a3..9381c579d1cd 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -381,6 +381,7 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, ddev->type = feature_dev_id_type(pdev); ddev->feature_id = feature->id; + ddev->revision = feature->revision; ddev->cdev = pdata->dfl_cdev; /* add mmio resource */ @@ -717,6 +718,7 @@ struct build_feature_devs_info { */ struct dfl_feature_info { u16 fid; + u8 rev; struct resource mmio_res; void __iomem *ioaddr; struct list_head node; @@ -796,6 +798,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo) /* save resource information for each feature */ feature->dev = fdev; feature->id = finfo->fid; + feature->revision = finfo->rev; /* * the FIU header feature has some fundamental functions (sriov @@ -910,19 +913,17 @@ static void build_info_free(struct build_feature_devs_info *binfo) devm_kfree(binfo->dev, binfo); } -static inline u32 feature_size(void __iomem *start) +static inline u32 feature_size(u64 value) { - u64 v = readq(start + DFH); - u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v); + u32 ofst = FIELD_GET(DFH_NEXT_HDR_OFST, value); /* workaround for private features with invalid size, use 4K instead */ return ofst ? ofst : 4096; } -static u16 feature_id(void __iomem *start) +static u16 feature_id(u64 value) { - u64 v = readq(start + DFH); - u16 id = FIELD_GET(DFH_ID, v); - u8 type = FIELD_GET(DFH_TYPE, v); + u16 id = FIELD_GET(DFH_ID, value); + u8 type = FIELD_GET(DFH_TYPE, value); if (type == DFH_TYPE_FIU) return FEATURE_ID_FIU_HEADER; @@ -1021,10 +1022,15 @@ create_feature_instance(struct build_feature_devs_info *binfo, unsigned int irq_base, nr_irqs; struct dfl_feature_info *finfo; int ret; + u8 rev; + u64 v; + + v = readq(binfo->ioaddr + ofst); + rev = FIELD_GET(DFH_REVISION, v); /* read feature size and id if inputs are invalid */ - size = size ? size : feature_size(binfo->ioaddr + ofst); - fid = fid ? fid : feature_id(binfo->ioaddr + ofst); + size = size ? size : feature_size(v); + fid = fid ? fid : feature_id(v); if (binfo->len - ofst < size) return -EINVAL; @@ -1038,6 +1044,7 @@ create_feature_instance(struct build_feature_devs_info *binfo, return -ENOMEM; finfo->fid = fid; + finfo->rev = rev; finfo->mmio_res.start = binfo->start + ofst; finfo->mmio_res.end = finfo->mmio_res.start + size - 1; finfo->mmio_res.flags = IORESOURCE_MEM; @@ -1166,7 +1173,7 @@ static int parse_feature_private(struct build_feature_devs_info *binfo, { if (!is_feature_dev_detected(binfo)) { dev_err(binfo->dev, "the private feature 0x%x does not belong to any AFU.\n", - feature_id(binfo->ioaddr + ofst)); + feature_id(readq(binfo->ioaddr + ofst))); return -EINVAL; } diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 2b82c96ba56c..422157cfd742 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -243,6 +243,7 @@ struct dfl_feature_irq_ctx { struct dfl_feature { struct platform_device *dev; u16 id; + u8 revision; int resource_index; void __iomem *ioaddr; struct dfl_feature_irq_ctx *irq_ctx; diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 6cc10982351a..431636a0dc78 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -38,6 +38,7 @@ struct dfl_device { int id; u16 type; u16 feature_id; + u8 revision; struct resource mmio_res; int *irqs; unsigned int num_irqs; From patchwork Fri Jun 25 07:42:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Hundeb=C3=B8ll?= X-Patchwork-Id: 12343925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EEA6C48BC2 for ; Fri, 25 Jun 2021 07:42:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10C3A61431 for ; Fri, 25 Jun 2021 07:42:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229995AbhFYHpN (ORCPT ); Fri, 25 Jun 2021 03:45:13 -0400 Received: from first.geanix.com ([116.203.34.67]:34952 "EHLO first.geanix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230025AbhFYHpK (ORCPT ); Fri, 25 Jun 2021 03:45:10 -0400 Received: from zen.. (unknown [185.17.218.86]) by first.geanix.com (Postfix) with ESMTPSA id CD7334C41C2; Fri, 25 Jun 2021 07:42:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=geanix.com; s=first; t=1624606968; bh=KqpbJ6G/4HtHo9jdTQoQrgQLylu4HU0NQpLl5hC5Uok=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=K+6Ao/sSZOLuKeZcKFLeNjy+uUAtdSmWpBp4oa9XG7PJfaysbtQY01oedcKV9PRsr 5tEUj1eeuQHf8R8mUTGPUok1zaIp3J0Z9bh/qZfB6uUnQ45k19+7RV5ZCnuIbOXjKF rXEv/MxJFR3Qmv4f9h6gFXNcymbJXJM09MKu7FwsAn9HDVTqT/1CNSbSVhc+OKh/vp rxb2i9YuOS140XWVtSnM7pdE8XwW7DFINq5GuiwI2TawNhr9vvAduIedE4BFbDECoZ 3nvayORsaN5MVG33mZtNnOT3NsvuOjTdjaguN4AwTXyO5zn4UEoKYhWKLP0XICfRz7 vyUc+0Y5hWy2w== From: =?utf-8?q?Martin_Hundeb=C3=B8ll?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , Jean Delvare , Guenter Roeck , Lee Jones , Mark Brown Cc: =?utf-8?q?Martin_Hundeb=C3=B8ll?= , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org Subject: [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision Date: Fri, 25 Jun 2021 09:42:11 +0200 Message-Id: <20210625074213.654274-4-martin@geanix.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210625074213.654274-1-martin@geanix.com> References: <20210625074213.654274-1-martin@geanix.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Martin Hundebøll The Max10 BMC on the Silicom n5010 PAC is slightly different than the existing BMC's, so use a dedicated feature revision detect it. Signed-off-by: Martin Hundebøll --- Changes since v1: * use feature revision from struct dfl_device instead of reading it from io-mem drivers/spi/spi-altera-dfl.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-altera-dfl.c b/drivers/spi/spi-altera-dfl.c index 3e32e4fe5895..f6cf7c8d9dac 100644 --- a/drivers/spi/spi-altera-dfl.c +++ b/drivers/spi/spi-altera-dfl.c @@ -111,6 +111,13 @@ static struct spi_board_info m10_bmc_info = { .chip_select = 0, }; +static struct spi_board_info m10_n5010_bmc_info = { + .modalias = "m10-n5010", + .max_speed_hz = 12500000, + .bus_num = 0, + .chip_select = 0, +}; + static void config_spi_master(void __iomem *base, struct spi_master *master) { u64 v; @@ -130,6 +137,7 @@ static void config_spi_master(void __iomem *base, struct spi_master *master) static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) { + struct spi_board_info *board_info = &m10_bmc_info; struct device *dev = &dfl_dev->dev; struct spi_master *master; struct altera_spi *hw; @@ -172,9 +180,12 @@ static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) goto exit; } - if (!spi_new_device(master, &m10_bmc_info)) { + if (dfl_dev->revision == FME_FEATURE_REV_MAX10_SPI_N5010) + board_info = &m10_n5010_bmc_info; + + if (!spi_new_device(master, board_info)) { dev_err(dev, "%s failed to create SPI device: %s\n", - __func__, m10_bmc_info.modalias); + __func__, board_info->modalias); } return 0; From patchwork Fri Jun 25 07:42:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Hundeb=C3=B8ll?= X-Patchwork-Id: 12343927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B838FC49EB9 for ; Fri, 25 Jun 2021 07:42:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3F2B61426 for ; Fri, 25 Jun 2021 07:42:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230107AbhFYHpO (ORCPT ); Fri, 25 Jun 2021 03:45:14 -0400 Received: from first.geanix.com ([116.203.34.67]:34920 "EHLO first.geanix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230072AbhFYHpL (ORCPT ); Fri, 25 Jun 2021 03:45:11 -0400 Received: from zen.. (unknown [185.17.218.86]) by first.geanix.com (Postfix) with ESMTPSA id 2575E4C41C3; Fri, 25 Jun 2021 07:42:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=geanix.com; s=first; t=1624606969; bh=OKf6/wgB4ByxaDS2MUvVAWCddXMhFEU98vb6qMw2YFY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=mmAUhgMbswgWarxJrCs4wz7LlzzraEhgzo1XE3e04M1OBcDUEZiYmP10wRX8/5tKl mgC1m4YctSvqdVART116Z2pwkYGN2QZ8zeLxrKnwtljaDYjbM70BeOygDaXR/BNQnp DQeYpROeZLPRQngUsScBuVjrF4C5IrYt5PSrF8DCscca62EMwSn05GanFI2pMTqjmN ssNYCEFDLXcHUTzX7W9vOnMBouZXp6uZTDtNCgpHUJwfk4PCjvtb3+3bWmgCNe5fYG 4o+KZgtbtcZpTbmWENCY25NKVjD20IV+BqX1JH8mrR4WmVbEcEzvGM0wrVeK7lb53v 7Ab0tWtMApANw== From: =?utf-8?q?Martin_Hundeb=C3=B8ll?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , Jean Delvare , Guenter Roeck , Lee Jones , Mark Brown Cc: =?utf-8?q?Martin_Hundeb=C3=B8ll?= , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org Subject: [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant Date: Fri, 25 Jun 2021 09:42:12 +0200 Message-Id: <20210625074213.654274-5-martin@geanix.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210625074213.654274-1-martin@geanix.com> References: <20210625074213.654274-1-martin@geanix.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Martin Hundebøll The m10-bmc is used on the Silicom N5010 PAC too, so add it to list of m10bmc types. Signed-off-by: Martin Hundebøll Acked-by: Moritz Fischer Reviewed-by: Xu Yilun --- Changes since v1: * Patch split out to separate mfd changes drivers/mfd/intel-m10-bmc.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c index 1a9bfb7f48cd..8db3bcf5fccc 100644 --- a/drivers/mfd/intel-m10-bmc.c +++ b/drivers/mfd/intel-m10-bmc.c @@ -15,7 +15,8 @@ enum m10bmc_type { M10_N3000, - M10_D5005 + M10_D5005, + M10_N5010, }; static struct mfd_cell m10bmc_d5005_subdevs[] = { @@ -28,6 +29,10 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = { { .name = "n3000bmc-secure" }, }; +static struct mfd_cell m10bmc_n5010_subdevs[] = { + { .name = "n5010bmc-hwmon" }, +}; + static const struct regmap_range m10bmc_regmap_range[] = { regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER), regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END), @@ -192,6 +197,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi) cells = m10bmc_d5005_subdevs; n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs); break; + case M10_N5010: + cells = m10bmc_n5010_subdevs; + n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs); + break; default: return -ENODEV; } @@ -207,6 +216,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi) static const struct spi_device_id m10bmc_spi_id[] = { { "m10-n3000", M10_N3000 }, { "m10-d5005", M10_D5005 }, + { "m10-n5010", M10_N5010 }, { } }; MODULE_DEVICE_TABLE(spi, m10bmc_spi_id); From patchwork Fri Jun 25 07:42:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Hundeb=C3=B8ll?= X-Patchwork-Id: 12343929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99981C49EA7 for ; Fri, 25 Jun 2021 07:42:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 90C7E61404 for ; Fri, 25 Jun 2021 07:42:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230235AbhFYHpS (ORCPT ); Fri, 25 Jun 2021 03:45:18 -0400 Received: from first.geanix.com ([116.203.34.67]:35012 "EHLO first.geanix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230111AbhFYHpN (ORCPT ); Fri, 25 Jun 2021 03:45:13 -0400 Received: from zen.. (unknown [185.17.218.86]) by first.geanix.com (Postfix) with ESMTPSA id 72B074C41C4; Fri, 25 Jun 2021 07:42:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=geanix.com; s=first; t=1624606970; bh=aDUZ0AgR1EgGJ3Ugg1Y9UNyeqVYYqsdMlaYYv9bnPXw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Vq8Lf5C3zgGgYY35Qkf84P22g/37c+nirj2U3tJfxzyi9ImOViewZJzEUhnVVmwQA Fx/ukZlckLV31Cos5HjAKp9VrpKl44IltFaq0WTQCOQ3u+UAVQq1f3c8LO1U0UcyxO JkgVub8okvYHVoffx+8sMnvsFoboFxwUhRVayV9R6BKxu2jOrbOWnikZX9BHwCKOkJ UQptN6QYHazRxog44x/8MXjJrH1uiRKxloCkkDkWNmTHtPAl5P5VGpmLoMpDSxBiGN 6/RAHqMqyNYZYf1irEig1Z/q+T1q1wJgernm3HS+d/CzIX16SVbbMxrHrawwko8UTH kHzFRItenWF8w== From: =?utf-8?q?Martin_Hundeb=C3=B8ll?= To: Wu Hao , Tom Rix , Moritz Fischer , Xu Yilun , Jean Delvare , Guenter Roeck , Lee Jones , Mark Brown Cc: =?utf-8?q?Martin_Hundeb=C3=B8ll?= , linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org Subject: [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Date: Fri, 25 Jun 2021 09:42:13 +0200 Message-Id: <20210625074213.654274-6-martin@geanix.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210625074213.654274-1-martin@geanix.com> References: <20210625074213.654274-1-martin@geanix.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Martin Hundebøll Add the list of sensors supported by the Silicom n5010 PAC, and enable the drivers as a subtype of the intel-m10-bmc multi-function driver. Signed-off-by: Martin Hundebøll Reviewed-by: Guenter Roeck Reviewed-by: Moritz Fischer Reviewed-by: Xu Yilun --- Changes since v1: * Patch split out to separate hwmon changes drivers/hwmon/intel-m10-bmc-hwmon.c | 116 ++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/drivers/hwmon/intel-m10-bmc-hwmon.c b/drivers/hwmon/intel-m10-bmc-hwmon.c index bd7ed2ed3a1e..7a08e4c44a4b 100644 --- a/drivers/hwmon/intel-m10-bmc-hwmon.c +++ b/drivers/hwmon/intel-m10-bmc-hwmon.c @@ -228,6 +228,118 @@ static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = { .hinfo = d5005bmc_hinfo, }; +static const struct m10bmc_sdata n5010bmc_temp_tbl[] = { + { 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" }, + { 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" }, + { 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" }, + { 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" }, + { 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" }, + { 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" }, + { 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" }, + { 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" }, + { 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" }, + { 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" }, + { 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" }, + { 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" }, + { 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" }, + { 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" }, + { 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" }, + { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" }, + { 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" }, +}; + +static const struct m10bmc_sdata n5010bmc_in_tbl[] = { + { 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" }, + { 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" }, + { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" }, + { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" }, + { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" }, + { 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" }, + { 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" }, + { 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" }, + { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" }, + { 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" }, + { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" }, + { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" }, + { 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" }, +}; + +static const struct m10bmc_sdata n5010bmc_curr_tbl[] = { + { 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" }, + { 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" }, + { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" }, + { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" }, + { 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" }, + { 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" }, + { 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" }, + { 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" }, + { 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" }, + { 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" }, + { 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" }, + { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" }, + { 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" }, +}; + +static const struct hwmon_channel_info *n5010bmc_hinfo[] = { + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_LABEL), + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL), + HWMON_CHANNEL_INFO(curr, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL, + HWMON_C_INPUT | HWMON_C_LABEL), + NULL +}; + +static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = { + .tables = { + [hwmon_temp] = n5010bmc_temp_tbl, + [hwmon_in] = n5010bmc_in_tbl, + [hwmon_curr] = n5010bmc_curr_tbl, + }, + + .hinfo = n5010bmc_hinfo, +}; + static umode_t m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr, int channel) @@ -438,6 +550,10 @@ static const struct platform_device_id intel_m10bmc_hwmon_ids[] = { .name = "d5005bmc-hwmon", .driver_data = (unsigned long)&d5005bmc_hwmon_bdata, }, + { + .name = "n5010bmc-hwmon", + .driver_data = (unsigned long)&n5010bmc_hwmon_bdata, + }, { } };