From patchwork Fri Jun 25 09:03:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12344403 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AEC2C49EAB for ; Fri, 25 Jun 2021 09:05:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 475F56142B for ; Fri, 25 Jun 2021 09:05:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230526AbhFYJHd (ORCPT ); Fri, 25 Jun 2021 05:07:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:57980 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230490AbhFYJHb (ORCPT ); Fri, 25 Jun 2021 05:07:31 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6B7D461431; Fri, 25 Jun 2021 09:05:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624611911; bh=Pbrm1uRTSvRmcoLNtqhDtj7irFXEs2zlkumxeogs/Ks=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ntVClOhHsHumuEoNFfmTKiKy31pCihbGzn7VBndYbYRAT4+DARIUGMoceuU7bllzY 1MgEH6fleICmwDueWtbAuaS9nC5WSAF5iblBMe6qdDn+cxa0oeihI1yOD70Vz0AQ51 YIPsTWccI/2leiIt/aNMrGlNTC5Rl+yBppzl9QkFDvZXP+JNzQbHsFJkmAzYDEcJyi U6yvYttaGJqKmmjM+R3MCgNehJaJ+OjnaQmBpA9JQTnw/WYUaxHj9PCBaV6XUnlt6u 5PyWKRMuUEwjNs594L6u+cJeBnFwndyusSjqZIFjFeLR+YpknsRkzWJnhRkmcDpTTx xNTSGOl38gNzA== Received: by pali.im (Postfix) id 8AA28A7D; Fri, 25 Jun 2021 11:05:09 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] PCI: aardvark: Do not touch status bits of masked interrupts in interrupt handler Date: Fri, 25 Jun 2021 11:03:13 +0200 Message-Id: <20210625090319.10220-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625090319.10220-1-pali@kernel.org> References: <20210625090319.10220-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It is incorrect to clear status bits of masked interrupts. The aardvark driver clears all status interrupt bits when no unmasked status bit was set. When some unmasked bit was set then masked bits were not cleared. Fix this so that masked bits are never cleared. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index d4215da17a59..36fcc077ec72 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1210,11 +1210,8 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); - if (!isr0_status && !isr1_status) { - advk_writel(pcie, isr0_val, PCIE_ISR0_REG); - advk_writel(pcie, isr1_val, PCIE_ISR1_REG); + if (!isr0_status && !isr1_status) return; - } /* Process MSI interrupts */ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) From patchwork Fri Jun 25 09:03:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12344399 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB814C2B9F4 for ; Fri, 25 Jun 2021 09:05:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF3646143B for ; Fri, 25 Jun 2021 09:05:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230513AbhFYJHc (ORCPT ); Fri, 25 Jun 2021 05:07:32 -0400 Received: from mail.kernel.org ([198.145.29.99]:57972 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230463AbhFYJHb (ORCPT ); Fri, 25 Jun 2021 05:07:31 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2D44A61429; Fri, 25 Jun 2021 09:05:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624611911; bh=/yKmQjvvAriWKaSF8AZeFSHN6aUtEK+OaFQo4i93O88=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aeDwti3I4RIA3eHvRfcRsx4CLOxp41zE6bUYJNauasCY2YkVUNP7lQw87u2nI182E VRVsHSKA96lSJiPFK7sNM9ADAPxsJw1q50xoMRYHR6Y7q6toMePEDmfRbqnX6zvU+7 4Q7Pxge3nTMh2+OyHLb8P5dSY4KXZQz7ld/HOcmm8QU+B+2Osj/16xbrWncTMG/4Nf zR/AA3y6TPJIfPG59fZCiPl62DLK0IhqzfxDeiJojyo3Tm1Owg3Gzcn4X5BT3gJqR7 jKqdMuZbmzTzNIqahKcM4ExnMn1+iZ2dbhw5n33KVBwnHvMP1ggbpenw98cJg9/c7T vvxVIZZGm8aRg== Received: by pali.im (Postfix) id E059C60E; Fri, 25 Jun 2021 11:05:10 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] PCI: aardvark: Check for virq mapping when processing INTx IRQ Date: Fri, 25 Jun 2021 11:03:14 +0200 Message-Id: <20210625090319.10220-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625090319.10220-1-pali@kernel.org> References: <20210625090319.10220-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It is possible that we receive spurious INTx interrupt. So add needed check before calling generic_handle_irq() function. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 36fcc077ec72..59f91fad2481 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1226,7 +1226,11 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) PCIE_ISR1_REG); virq = irq_find_mapping(pcie->irq_domain, i); - generic_handle_irq(virq); + if (virq) + generic_handle_irq(virq); + else + dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n", + (char)i+'A'); } } From patchwork Fri Jun 25 09:03:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12344405 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08937C2B9F4 for ; Fri, 25 Jun 2021 09:05:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E556E61431 for ; Fri, 25 Jun 2021 09:05:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231144AbhFYJHe (ORCPT ); Fri, 25 Jun 2021 05:07:34 -0400 Received: from mail.kernel.org ([198.145.29.99]:57994 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230452AbhFYJHc (ORCPT ); Fri, 25 Jun 2021 05:07:32 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 61DC26142D; Fri, 25 Jun 2021 09:05:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624611912; bh=L9Vq1i7R7xru0XqrFwmNPS8E0uTO1HEZvLpOaOBqDiY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Nm5DsR+HXqjcQ9IOW+H8zPWHnx/fmvVNixMByH8a+QwktgvpzX6qGTMkznIBV2q6F 1pzTro9KhYxY9pVk2Q0JXLRwJf4wgcUyCM/wf4cgDUT05VjB64cZzKn5FBiiYhU0zv Uszm1XUEi9SKdeEUhRQ1QYVWI01pTto2szTsvOEstnnVRpIqr5jlDJ2u/ktH42ycoi XafpbucCa/WJsi/+e8Q4IwlPrfaNlI1cn0275GlCZthSP73mPfBHtjpWs5Jx8XngzM FFKyWVbw9eZMwLtcDQwAijTDTPccFTe1AO0QmvLBMN/+NupbIPZ6pCC1Ug1eKNtb/k W4gMYs+6QwA+A== Received: by pali.im (Postfix) id 1FB7160E; Fri, 25 Jun 2021 11:05:12 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] PCI: aardvark: Remove irq_mask_ack callback for INTx interrupts Date: Fri, 25 Jun 2021 11:03:15 +0200 Message-Id: <20210625090319.10220-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625090319.10220-1-pali@kernel.org> References: <20210625090319.10220-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Callback for irq_mask_ack is the same as for irq_mask. As there is no special handling for irq_ack, there is no need to define irq_mask_ack too. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Acked-by: Marc Zyngier --- drivers/pci/controller/pci-aardvark.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 59f91fad2481..bf44d6bfd0ca 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1152,7 +1152,6 @@ static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) } irq_chip->irq_mask = advk_pcie_irq_mask; - irq_chip->irq_mask_ack = advk_pcie_irq_mask; irq_chip->irq_unmask = advk_pcie_irq_unmask; pcie->irq_domain = From patchwork Fri Jun 25 09:03:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12344407 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04E4DC48BC2 for ; Fri, 25 Jun 2021 09:05:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E15CE61445 for ; Fri, 25 Jun 2021 09:05:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231158AbhFYJHf (ORCPT ); Fri, 25 Jun 2021 05:07:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:58010 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231139AbhFYJHe (ORCPT ); Fri, 25 Jun 2021 05:07:34 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7C74461436; Fri, 25 Jun 2021 09:05:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624611913; bh=qwjHHo7IaX3Xq/QUrlAe0vmXBBdE06HBmCIPvLbwMlM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qu4yU4BSuS2PuQAeH4d9ZkwNPs4a7xLK1Lbf4Tere70haxHYndy2ZBKh+2BVIIZxs NvXpnVT5DymP+GBvYJHHEqLQarC/iwfSyTFYyxyfgxDcqG5gdQvpOxn+q5MrY5Uk5s sPVP8T/ZxSCgF57mgyfm1k5/zsItKQTtBBmyiWFGhUwsd4PsWQCclkNXg8V7LexelV EEGMBmMEWEeYSQc7HlE1d7mJpLMI6coQ4QuSLFj2srLYlDa82egeyriSi7HP+bMwfq K9yCCHWTDlZayzkfBDN/JKuIu9Vy2Wb4BrwA1JCbHRrtVOapA+bSMiSYlTSRG3GPMB FQ8P5TlVp2PaQ== Received: by pali.im (Postfix) id 3F0F060E; Fri, 25 Jun 2021 11:05:13 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] PCI: aardvark: Don't mask irq when mapping Date: Fri, 25 Jun 2021 11:03:16 +0200 Message-Id: <20210625090319.10220-5-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625090319.10220-1-pali@kernel.org> References: <20210625090319.10220-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org By default, all Legacy INTx interrupts are masked, so there is no need to mask this interrupt during irq_map callback. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index bf44d6bfd0ca..c4fa64a31733 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1060,7 +1060,6 @@ static int advk_pcie_irq_map(struct irq_domain *h, { struct advk_pcie *pcie = h->host_data; - advk_pcie_irq_mask(irq_get_irq_data(virq)); irq_set_status_flags(virq, IRQ_LEVEL); irq_set_chip_and_handler(virq, &pcie->irq_chip, handle_level_irq); From patchwork Fri Jun 25 09:03:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12344409 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66CC8C49EA7 for ; Fri, 25 Jun 2021 09:05:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5109C61438 for ; Fri, 25 Jun 2021 09:05:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231150AbhFYJHg (ORCPT ); Fri, 25 Jun 2021 05:07:36 -0400 Received: from mail.kernel.org ([198.145.29.99]:58044 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231151AbhFYJHf (ORCPT ); Fri, 25 Jun 2021 05:07:35 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 844DD6141C; Fri, 25 Jun 2021 09:05:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624611914; bh=fTrExx4lUe1+OYor3MHjWSqFRo0mXnbToGcYLaZhcRw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rmigltSB/m9gVU1OtHSdfUL62ncbKyXqmHJ+zEsVsB/B1XlL4EFmz8rtkRkQNioqb u4Xbp4u/W1lO+rzHXa7aRa00iEJu/VMRKBXfBNJBggB5clEm7ZGUIiucyl20M77Niv ZMbQYuY9qBDh9l8kdT9CYaFFQCkaQssHP37RD9SOnLv5E8RLWsfTAFC3Xk6jArBgMy k8Gs+u4ehhTOxwJzWepVcoSwTHoAlVrklGIH3hZj9GKGs+jvfjTJmdQ3XTG0rT8mpc SJjIrEPd1Rd4nmcs7VeYmU7AoxfllOmW9cLlO7CkbSA7tyzq9EE+UJJj1LSAzHwg0U hla+F/Wif8mKw== Received: by pali.im (Postfix) id 46F8960E; Fri, 25 Jun 2021 11:05:14 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] PCI: aardvark: Fix support for MSI interrupts Date: Fri, 25 Jun 2021 11:03:17 +0200 Message-Id: <20210625090319.10220-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625090319.10220-1-pali@kernel.org> References: <20210625090319.10220-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org MSI domain callback .alloc (implemented by advk_msi_irq_domain_alloc() function) should return zero on success. Returning non-zero value indicates failure. Fix return value of this function as in many cases it now returns failure while allocating IRQs. Aardvark hardware supports Multi-MSI and MSI_FLAG_MULTI_PCI_MSI is already set. But when allocating MSI interrupt numbers for Multi-MSI, they need to be properly aligned, otherwise endpoint devices send MSI interrupt with incorrect numbers. Fix this issue by using function bitmap_find_free_region() instead of bitmap_find_next_zero_area(). To ensure that aligned MSI interrupt numbers are used by endpoint devices, we cannot use Linux virtual irq numbers (as they are random and not properly aligned). So use hwirq numbers allocated by the function bitmap_find_free_region(), which are aligned. This needs an update in advk_msi_irq_compose_msi_msg() and advk_pcie_handle_msi() functions to do proper mapping between Linux virtual irq numbers and hwirq MSI inner domain numbers. Also the whole 16-bit MSI number is stored in the PCIE_MSI_PAYLOAD_REG register, not only lower 8 bits. Fix reading content of this register. This change fixes receiving MSI interrupts on Armada 3720 boards and allows using NVMe disks which use Multi-MSI feature with 3 interrupts. Without this change, NVMe disks just freeze booting Linux on Armada 3720 boards as linux nvme-core.c driver is waiting 60s for an interrupt. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") --- drivers/pci/controller/pci-aardvark.c | 32 ++++++++++++++++----------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index c4fa64a31733..0e81d89f307d 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -118,6 +118,7 @@ #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) +#define PCIE_MSI_DATA_MASK GENMASK(15, 0) /* PCIe window configuration */ #define OB_WIN_BASE_ADDR 0x4c00 @@ -981,7 +982,7 @@ static void advk_msi_irq_compose_msi_msg(struct irq_data *data, msg->address_lo = lower_32_bits(msi_msg); msg->address_hi = upper_32_bits(msi_msg); - msg->data = data->irq; + msg->data = data->hwirq; } static int advk_msi_set_affinity(struct irq_data *irq_data, @@ -998,15 +999,11 @@ static int advk_msi_irq_domain_alloc(struct irq_domain *domain, int hwirq, i; mutex_lock(&pcie->msi_used_lock); - hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, - 0, nr_irqs, 0); - if (hwirq >= MSI_IRQ_NUM) { - mutex_unlock(&pcie->msi_used_lock); - return -ENOSPC; - } - - bitmap_set(pcie->msi_used, hwirq, nr_irqs); + hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, + order_base_2(nr_irqs)); mutex_unlock(&pcie->msi_used_lock); + if (hwirq < 0) + return -ENOSPC; for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, hwirq + i, @@ -1014,7 +1011,7 @@ static int advk_msi_irq_domain_alloc(struct irq_domain *domain, domain->host_data, handle_simple_irq, NULL, NULL); - return hwirq; + return 0; } static void advk_msi_irq_domain_free(struct irq_domain *domain, @@ -1024,7 +1021,7 @@ static void advk_msi_irq_domain_free(struct irq_domain *domain, struct advk_pcie *pcie = domain->host_data; mutex_lock(&pcie->msi_used_lock); - bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); + bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); mutex_unlock(&pcie->msi_used_lock); } @@ -1176,6 +1173,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) { u32 msi_val, msi_mask, msi_status, msi_idx; u16 msi_data; + int virq; msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); @@ -1185,9 +1183,17 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) if (!(BIT(msi_idx) & msi_status)) continue; + /* + * msi_idx contains bits [4:0] of the msi_data and msi_data + * contains 16bit MSI interrupt number from MSI inner domain + */ advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); - msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; - generic_handle_irq(msi_data); + msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; + virq = irq_find_mapping(pcie->msi_inner_domain, msi_data); + if (virq) + generic_handle_irq(virq); + else + dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%04hx\n", msi_data); } advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, From patchwork Fri Jun 25 09:03:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12344411 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0969C48BC2 for ; Fri, 25 Jun 2021 09:05:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D617A60C3F for ; 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Fri, 25 Jun 2021 11:05:15 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] PCI: aardvark: Correctly clear and unmask all MSI interrupts Date: Fri, 25 Jun 2021 11:03:18 +0200 Message-Id: <20210625090319.10220-7-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625090319.10220-1-pali@kernel.org> References: <20210625090319.10220-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Define a new macro PCIE_MSI_ALL_MASK and use it for masking, unmasking and clearing all MSI interrupts. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 0e81d89f307d..7cad6d989f6c 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -117,6 +117,7 @@ #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) +#define PCIE_MSI_ALL_MASK GENMASK(31, 0) #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) #define PCIE_MSI_DATA_MASK GENMASK(15, 0) @@ -470,19 +471,22 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); /* Clear all interrupts */ + advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); /* Disable All ISR0/1 Sources */ - reg = PCIE_ISR0_ALL_MASK; - reg &= ~PCIE_ISR0_MSI_INT_PENDING; - advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); - + advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); /* Unmask all MSIs */ - advk_writel(pcie, 0, PCIE_MSI_MASK_REG); + advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); + + /* Unmask summary MSI interrupt */ + reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); + reg &= ~PCIE_ISR0_MSI_INT_PENDING; + advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); /* Enable summary interrupt for GIC SPI source */ reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); @@ -1177,7 +1181,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); - msi_status = msi_val & ~msi_mask; + msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK); for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { if (!(BIT(msi_idx) & msi_status)) From patchwork Fri Jun 25 09:03:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 12344413 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FA25C48BC2 for ; Fri, 25 Jun 2021 09:05:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6DD626141F for ; Fri, 25 Jun 2021 09:05:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231235AbhFYJHo (ORCPT ); Fri, 25 Jun 2021 05:07:44 -0400 Received: from mail.kernel.org ([198.145.29.99]:58150 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231225AbhFYJHh (ORCPT ); Fri, 25 Jun 2021 05:07:37 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A98B261430; Fri, 25 Jun 2021 09:05:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624611917; bh=7rRm/q8fAPvDNEHFrOmUDFjPtfaxc24KmQZoezmDFow=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R2h482+ZytKgB/HtcV8UAiWzwa434koKn+f4CPYtzLkKWiQ7NbNtDBemoDOyZcIWF bFdAfdGK9NyQEtZQstUYaOksg8oX0Iv/UOD0K8cin8XNDIRCqa2YjQF8YiG1HtzCwM Hr+3n6nFm1+26b2Sn0OC9EGekJxkxZ2mvtqgR25ig0G18TBgyZqt97JdhN0kdebDyB MWl4jzfAMVlVokdmQtMEK1bzvAWyFrLiEv9N9rZi5O7lIocpe7fwNPvHLDbGW0nILz NcUriVVQKcEpSz+vmZuehuTE2giU9yxFShDtB/eynaICXcUf/TM+1KSfx2+ag/7Bn0 Oa2+MaRbwAgdg== Received: by pali.im (Postfix) id 6A80360E; Fri, 25 Jun 2021 11:05:16 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Lorenzo Pieralisi , Thomas Petazzoni , Bjorn Helgaas , Rob Herring Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , Marc Zyngier , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] PCI: aardvark: Fix setting MSI address Date: Fri, 25 Jun 2021 11:03:19 +0200 Message-Id: <20210625090319.10220-8-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625090319.10220-1-pali@kernel.org> References: <20210625090319.10220-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org MSI address for receiving MSI interrupts needs to be correctly set before enabling processing of MSI interrupts. Move code for setting PCIE_MSI_ADDR_LOW_REG and PCIE_MSI_ADDR_HIGH_REG registers with MSI address from advk_pcie_init_msi_irq_domain() function to advk_pcie_setup_hw() function before enabling PCIE_CORE_CTRL2_MSI_ENABLE. As part of this change, also remove unused variable msi_msg, which was used only for MSI doorbell address. MSI address can be any address which cannot be used to DMA to. So change it to the address of the main struct advk_pcie Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Acked-by: Marc Zyngier Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") --- drivers/pci/controller/pci-aardvark.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 7cad6d989f6c..84ecc418e6be 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -244,7 +244,6 @@ struct advk_pcie { struct msi_domain_info msi_domain_info; DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; - u16 msi_msg; int link_gen; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; @@ -403,6 +402,7 @@ static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) static void advk_pcie_setup_hw(struct advk_pcie *pcie) { + phys_addr_t msi_addr; u32 reg; int i; @@ -465,6 +465,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg |= LANE_COUNT_1; advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* Set MSI address */ + msi_addr = virt_to_phys(pcie); + advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); + advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); + /* Enable MSI */ reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); reg |= PCIE_CORE_CTRL2_MSI_ENABLE; @@ -982,10 +987,10 @@ static void advk_msi_irq_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); - phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); + phys_addr_t msi_addr = virt_to_phys(pcie); - msg->address_lo = lower_32_bits(msi_msg); - msg->address_hi = upper_32_bits(msi_msg); + msg->address_lo = lower_32_bits(msi_addr); + msg->address_hi = upper_32_bits(msi_addr); msg->data = data->hwirq; } @@ -1080,7 +1085,6 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) struct device_node *node = dev->of_node; struct irq_chip *bottom_ic, *msi_ic; struct msi_domain_info *msi_di; - phys_addr_t msi_msg_phys; mutex_init(&pcie->msi_used_lock); @@ -1098,13 +1102,6 @@ static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) MSI_FLAG_MULTI_PCI_MSI; msi_di->chip = msi_ic; - msi_msg_phys = virt_to_phys(&pcie->msi_msg); - - advk_writel(pcie, lower_32_bits(msi_msg_phys), - PCIE_MSI_ADDR_LOW_REG); - advk_writel(pcie, upper_32_bits(msi_msg_phys), - PCIE_MSI_ADDR_HIGH_REG); - pcie->msi_inner_domain = irq_domain_add_linear(NULL, MSI_IRQ_NUM, &advk_msi_domain_ops, pcie);