From patchwork Fri Aug 3 14:10:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 10555135 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4CE7915E9 for ; Fri, 3 Aug 2018 14:11:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 370222C741 for ; Fri, 3 Aug 2018 14:11:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 281092C788; Fri, 3 Aug 2018 14:11:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 780022C741 for ; Fri, 3 Aug 2018 14:11:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732350AbeHCQHP (ORCPT ); Fri, 3 Aug 2018 12:07:15 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:39302 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731781AbeHCQHO (ORCPT ); Fri, 3 Aug 2018 12:07:14 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5CDF76035F; Fri, 3 Aug 2018 14:10:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533305443; bh=eq+JmpWl1jnqMYGKuroI0esBUvPo2zjNZb7Agt1ZXAA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OgZAWuPV10e7PIQBOrjLqJaz84k3eUkylRqxY1rBOQrpxE/Vz+KIIbrU3AItkLK2s eycUlTE40hEUNI3Z8531VirvyjshrcrYrw6jb+lg2BX7mPxHlTnRYOpYMR0/BqM6sz FULdU/Rc3ariujKgutavnU80CnpxdOlKMaeup5u4= Received: from srichara-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sricharan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 62E9C6079C; Fri, 3 Aug 2018 14:10:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533305441; bh=eq+JmpWl1jnqMYGKuroI0esBUvPo2zjNZb7Agt1ZXAA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cshXWqIZ1/byV6+PYdPBJKdhTR7hO7xEq+DCFmbzoV3w9MQSOcQm9TiygDrX0ZztC TEpdzyZe4Rk3thCkjshUTImaN0MxRZM5wQksCEo+MQvPqEuN34xBSLR5O594ty6J9p 6Tt8dzlDkbewg6doybtKYjNONal5m2I133Og9ZkE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 62E9C6079C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: sricharan@codeaurora.org Subject: [PATCH 1/5] arm: dts: qcom: Add pcie nodes for ipq8064 Date: Fri, 3 Aug 2018 19:40:15 +0530 Message-Id: <1533305419-29152-2-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> References: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding the pcie nodes and pins. Signed-off-by: Sricharan R --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 182 ++++++++++++++++++++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 70790ac..e02d588 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -2,8 +2,11 @@ /dts-v1/; #include "skeleton.dtsi" +#include #include #include +#include +#include #include #include @@ -114,6 +117,33 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = ; + + pcie0_pins: pcie0_pinmux { + mux { + pins = "gpio3"; + function = "pcie1_rst"; + drive-strength = <12>; + bias-disable; + }; + }; + + pcie1_pins: pcie1_pinmux { + mux { + pins = "gpio48"; + function = "pcie2_rst"; + drive-strength = <12>; + bias-disable; + }; + }; + + pcie2_pins: pcie2_pinmux { + mux { + pins = "gpio63"; + function = "pcie3_rst"; + drive-strength = <12>; + bias-disable; + }; + }; }; intc: interrupt-controller@2000000 { @@ -373,5 +403,157 @@ #reset-cells = <1>; }; + pcie0: pci@1b500000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b500000 0x1000 + 0x1b502000 0x80 + 0x1b600000 0x100 + 0x0ff00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + + assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + status = "disabled"; + perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + }; + + pcie1: pci@1b700000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b700000 0x1000 + 0x1b702000 0x80 + 0x1b800000 0x100 + 0x31f00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc PCIE_1_A_CLK>, + <&gcc PCIE_1_H_CLK>, + <&gcc PCIE_1_PHY_CLK>, + <&gcc PCIE_1_AUX_CLK>, + <&gcc PCIE_1_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + + assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_1_ACLK_RESET>, + <&gcc PCIE_1_HCLK_RESET>, + <&gcc PCIE_1_POR_RESET>, + <&gcc PCIE_1_PCI_RESET>, + <&gcc PCIE_1_PHY_RESET>, + <&gcc PCIE_1_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + + status = "disabled"; + perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + }; + + pcie2: pci@1b900000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b900000 0x1000 + 0x1b902000 0x80 + 0x1ba00000 0x100 + 0x35f00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc PCIE_2_A_CLK>, + <&gcc PCIE_2_H_CLK>, + <&gcc PCIE_2_PHY_CLK>, + <&gcc PCIE_2_AUX_CLK>, + <&gcc PCIE_2_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + + assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_2_ACLK_RESET>, + <&gcc PCIE_2_HCLK_RESET>, + <&gcc PCIE_2_POR_RESET>, + <&gcc PCIE_2_PCI_RESET>, + <&gcc PCIE_2_PHY_RESET>, + <&gcc PCIE_2_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + pinctrl-0 = <&pcie2_pins>; + pinctrl-names = "default"; + + status = "disabled"; + perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; + }; }; }; From patchwork Fri Aug 3 14:10:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 10555133 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4FACE15A6 for ; Fri, 3 Aug 2018 14:11:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3F5B72C741 for ; Fri, 3 Aug 2018 14:11:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3359F2C788; Fri, 3 Aug 2018 14:11:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B807B2C741 for ; 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Fri, 3 Aug 2018 14:10:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533305444; bh=EQG9sK43bVGDuVMPcKecmT+aVLbOulTMdTKleQjXmPY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mPxDkm2+biroyDKzsybqO4/UP9gzDFEsTnBMNgW+lPPmvTXNwgiVyIC3DJu4H4XoZ FFLztyf0wXZQ0hs6sqJA/Ql6LXjr8qJSpoOgaQ6xa+d5Hvsg9+AeOi2Xu1q24fHW4+ 9FfhaOJgjADbj/imt2mXnmDOO4HUrd9MuPKrDguU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2DA7860AD9 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: sricharan@codeaurora.org Subject: [PATCH 2/5] arm: dts: qcom: Add sdcc nodes for ipq8064 Date: Fri, 3 Aug 2018 19:40:16 +0530 Message-Id: <1533305419-29152-3-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> References: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The relevant data for sdcc. Signed-off-by: Sricharan R --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 76 +++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index e02d588..e78618e 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -555,5 +555,81 @@ status = "disabled"; perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; }; + + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdcc1bam:dma@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = ; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc3bam:dma@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = ; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + #mmc-ddr-1_8v; + sd-uhs-sdr104; + sd-uhs-ddr50; + vqmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + }; }; }; From patchwork Fri Aug 3 14:10:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 10555131 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 58DA215E9 for ; Fri, 3 Aug 2018 14:11:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 480D92C788 for ; Fri, 3 Aug 2018 14:11:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3C1D12C78D; Fri, 3 Aug 2018 14:11:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF0A52C788 for ; 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Fri, 3 Aug 2018 14:10:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533305447; bh=e1jCYZyOjK2cepkiEYHcHm0ColVjHvst2rpq/6QZIzc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DbUBe9P068TxJTZLZBrQVeCyZCJ+ZgLRNK8yxBYLYC7q94KJsQ0BG4aN+O0marp3F W1pbFJJT4Qk2901vbrTzHSUIR07GlSzzoLQQkXjHiIvNVQzTHJcb03UBnj6mHzaz95 Xq3aka8W5ASCzh8cFL9UmH8JLw/1M7H1bd3H0Pbs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 32E5A602D7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: sricharan@codeaurora.org Subject: [PATCH 3/5] arm: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi Date: Fri, 3 Aug 2018 19:40:17 +0530 Message-Id: <1533305419-29152-4-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> References: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The nodes in ipq8064-ap148.dts currently are common with boards that we will add next. So move the common data to ipq8064-v.1.0.dtsi. Signed-off-by: Sricharan R --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 83 ++------------------------------ arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 65 +++++++++++++++++++++++++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 9 ++++ 3 files changed, 77 insertions(+), 80 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index bcf53e3..f45b05e 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -2,26 +2,8 @@ #include "qcom-ipq8064-v1.0.dtsi" / { - model = "Qualcomm IPQ8064/AP148"; - compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; + model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; + compatible = "qcom,ipq8064-ap148"; soc { pinmux@800000 { @@ -30,74 +12,15 @@ function = "gsbi4"; bias-disable; }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - }; }; gsbi@16300000 { - qcom,mode = ; - status = "ok"; - serial@16340000 { - status = "ok"; - }; - - i2c4: i2c@16380000 { + i2c@16380000 { status = "ok"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c4_pins>; pinctrl-names = "default"; }; }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "ok"; - - spi4: spi@1a280000 { - status = "ok"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: m25p80@0 { - compatible = "s25fl256s1"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "rootfs"; - reg = <0x0 0x1000000>; - }; - - partition@1 { - label = "scratch"; - reg = <0x1000000 0x1000000>; - }; - }; - }; - }; - - sata-phy@1b400000 { - status = "ok"; - }; - - sata@29000000 { - ports-implemented = <0x1>; - status = "ok"; - }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi index e118119..ee32f97 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -1,2 +1,67 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-ipq8064.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; + + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + gsbi@16300000 { + qcom,mode = ; + status = "ok"; + + serial@16340000 { + status = "ok"; + }; + }; + + gsbi5: gsbi@1a200000 { + qcom,mode = ; + status = "ok"; + + spi4: spi@1a280000 { + status = "ok"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 0>; + + flash: m25p80@0 { + compatible = "s25fl256s1"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "rootfs"; + reg = <0x0 0x1000000>; + }; + + partition@1 { + label = "scratch"; + reg = <0x1000000 0x1000000>; + }; + }; + }; + }; + + sata-phy@1b400000 { + status = "ok"; + }; + + sata@29000000 { + ports-implemented = <0x1>; + status = "ok"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index e78618e..04cc822 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -144,6 +144,15 @@ bias-disable; }; }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + drive-strength = <10>; + bias-none; + }; + }; }; intc: interrupt-controller@2000000 { From patchwork Fri Aug 3 14:10:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 10555127 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F17115A6 for ; Fri, 3 Aug 2018 14:10:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7EB3E2C77F for ; Fri, 3 Aug 2018 14:10:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7304A2C788; Fri, 3 Aug 2018 14:10:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 184DE2C77F for ; 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Fri, 3 Aug 2018 14:10:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533305450; bh=DVGdmtNtKpeKURO1+P5XZeWTqDAOj6c1fbHeVSBaRmM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JAzrJV7xjQCMHcuUrAgeZwdtK5hfq0mP1vxvxnVhE7zhn074K6MQjMbvK6+pHtZG5 3ClDtyqLuQU2MDQFXAAUGKagLJz0Y1eyPnyNO3ulKOKallE8ZITY+P294guJ984slQ V6v622jWEWbXJWpFb6zafzXFEjgRaLZSqsdrnDIY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0061560117 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: sricharan@codeaurora.org Subject: [PATCH 4/5] arm: dts: qcom: Add ipq8064-ap161.dts Date: Fri, 3 Aug 2018 19:40:18 +0530 Message-Id: <1533305419-29152-5-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> References: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a new board dts for ipq8064-ap161. Signed-off-by: Sricharan R --- Documentation/devicetree/bindings/arm/qcom.txt | 2 ++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 7 +++++++ 3 files changed, 10 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap161.dts diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt index ee532e7..2325135 100644 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ b/Documentation/devicetree/bindings/arm/qcom.txt @@ -15,6 +15,7 @@ The 'SoC' and 'board' elements are required. All other elements are optional. The 'SoC' element must be one of the following strings: + ipq8064 apq8016 apq8074 apq8084 @@ -30,6 +31,7 @@ The 'SoC' element must be one of the following strings: The 'board' element must be one of the following strings: + ap cdp liquid dragonboard diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de7..233661a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -772,6 +772,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq4019-ap.dk07.1-c1.dtb \ qcom-ipq4019-ap.dk07.1-c2.dtb \ qcom-ipq8064-ap148.dtb \ + qcom-ipq8064-ap161.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-fairphone-fp2.dtb \ diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/arch/arm/boot/dts/qcom-ipq8064-ap161.dts new file mode 100644 index 0000000..aab5174 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-ap161.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064/AP-161"; + compatible = "qcom,ipq8064-ap161"; +}; From patchwork Fri Aug 3 14:10:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 10555129 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF2B915E9 for ; Fri, 3 Aug 2018 14:11:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF3712C77F for ; Fri, 3 Aug 2018 14:11:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B2FED2C788; Fri, 3 Aug 2018 14:11:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 437752C77F for ; Fri, 3 Aug 2018 14:11:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732090AbeHCQH1 (ORCPT ); Fri, 3 Aug 2018 12:07:27 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:39668 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731781AbeHCQHZ (ORCPT ); Fri, 3 Aug 2018 12:07:25 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id EF3B1606DD; Fri, 3 Aug 2018 14:10:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533305454; bh=HRLNskszb2CfH6uA2uDPUxATm0RAB/xV76iIRWy3Uco=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SRmfaUqQOxPbrsKnjX9UM+VJVdcE0fYLVEuIdW1Fng9z4btDQDTYdIa8qz6qPKgXv dTXhIixnAzKC/p6jKISywt5ztomov2mm4PhJDbpt6GWY31XdJc50w4cq8k6Ln0qGlx VXIVman5eVpuTTXPOdLvHVU2zwHRs1miLEv15oCU= Received: from srichara-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sricharan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C73FE6063A; Fri, 3 Aug 2018 14:10:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1533305453; bh=HRLNskszb2CfH6uA2uDPUxATm0RAB/xV76iIRWy3Uco=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o0FJQPnMiMmND46af93hbNAQsAhmRL23G5nN2SeMChnDV6Vs+lzoTVRMHzQGSqkrw qfXZz56Gg6+8kBtYCtZOhtwQ9wyr0Eyp0EuamkguyiNepm+IsRF9e/Zh99qOMjYEzj jwRO1DMX86b+JOhMDv355asxqt/KsCZ2Vk7U2qm4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C73FE6063A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org From: Sricharan R To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: sricharan@codeaurora.org Subject: [PATCH 5/5] arm: dts: qcom: Add led and gpio-button nodes to ipq8064 boards Date: Fri, 3 Aug 2018 19:40:19 +0530 Message-Id: <1533305419-29152-6-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> References: <1533305419-29152-1-git-send-email-sricharan@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the dt nodes for enabling the leds and gpio-buttons. Signed-off-by: Sricharan R --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8 +++++ arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 60 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 ++++++++++ 3 files changed, 87 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index f45b05e..554c65e 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -12,6 +12,14 @@ function = "gsbi4"; bias-disable; }; + + buttons_pins: buttons_pins { + mux { + pins = "gpio54", "gpio65"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; gsbi@16300000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi index ee32f97..e239a04 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-ipq8064.dtsi" +#include / { model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; @@ -63,5 +64,64 @@ ports-implemented = <0x1>; status = "ok"; }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&buttons_pins>; + pinctrl-names = "default"; + + button@1 { + label = "reset"; + linux,code = ; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + button@2 { + label = "wps"; + linux,code = ; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led@7 { + label = "led_usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbdev"; + default-state = "off"; + }; + + led@8 { + label = "led_usb3"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbdev"; + default-state = "off"; + }; + + led@9 { + label = "status_led_fail"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@26 { + label = "sata_led"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@53 { + label = "status_led_pass"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 04cc822..f793cd1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -153,6 +153,25 @@ bias-none; }; }; + + leds_pins: leds_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", + "gpio26", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + buttons_pins: buttons_pins { + mux { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; intc: interrupt-controller@2000000 {