From patchwork Tue Jun 29 12:49:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34A37C11F66 for ; Tue, 29 Jun 2021 13:17:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EBEEE61D5D for ; Tue, 29 Jun 2021 13:17:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EBEEE61D5D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TK9VCQqQaSzcAf606vggdvTO4J9gLNzMGXnobC1gGl4=; b=TZdT3rKXWn2Pq8 k4DhwZdaLQImw0ZWFCjXWCtDs4/xxXgJOOPHC8J9HKoM4P/AJagOYzbIej7zSfUsAS3ul03G+fy0s PYpDKYDmKAHfMokOcggFvZxNRsM/6MxFOwNHksd0QwG99rCmxnhIzaexK2lnaeGPlqTRdHYkHSqp6 Jqli1CowlyHhg9eGQJdSHgz71YSsGZry2DPAavO964WbNmEquCs1QhtNq+1CbGS2MjzpZxvaEyA9U l+RuWIhDHkK0S9EYrxA9IFoeu+Spph3LYeR+FdOkS70MIdf8BT7aKP5arPF8HII7o+t/OoNh+TZ0J l/JLnm2q2VuG66jWk+CQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDaQ-00AyHj-Oy; Tue, 29 Jun 2021 13:15:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDCW-00AsxU-PO for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 12:50:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B3DF911B3; Tue, 29 Jun 2021 05:50:47 -0700 (PDT) Received: from e113632-lin.cambridge.arm.com (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B24703F718; Tue, 29 Jun 2021 05:50:46 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 01/13] genirq: Add chip flag to denote automatic IRQ (un)masking Date: Tue, 29 Jun 2021 13:49:58 +0100 Message-Id: <20210629125010.458872-2-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055052_986624_37F1D94C X-CRM114-Status: GOOD ( 12.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some IRQ chips such as the Arm GICs automagically mask / unmask an IRQ during the handling of said IRQ. This renders further mask / unmask operations within the flow handlers redundant, which we do want to leverage as masking by itself is not cheap (Distributor access via MMIO for GICs). This is different from having a chip->irq_mask_ack() callback as this masking is: - inherent to the chip->irq_ack() and *cannot* be omitted - a *different* masking state than chip->irq_mask() (chip->irq_mask() is idempotent, chip->irq_ack() really isn't) Add a chip flag, IRQCHIP_AUTOMASKS_FLOW, to denote chips with such behaviour. Add a new IRQ data flag, IRQD_IRQ_FLOW_MASKED, to keep this flow-induced mask state separate from regular mask / unmask operations (IRQD_IRQ_MASKED). Signed-off-by: Valentin Schneider --- include/linux/irq.h | 10 ++++++++++ kernel/irq/chip.c | 5 +++++ kernel/irq/debugfs.c | 2 ++ kernel/irq/internals.h | 5 +++++ 4 files changed, 22 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index 8e9a9ae471a6..ef179245a642 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -221,6 +221,8 @@ struct irq_data { * irq_chip::irq_set_affinity() when deactivated. * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set. + * IRQD_IRQ_FLOW_MASKED - Interrupt is masked by ACK. Only EOI can + * clear this. */ enum { IRQD_TRIGGER_MASK = 0xf, @@ -247,6 +249,7 @@ enum { IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28), IRQD_AFFINITY_ON_ACTIVATE = (1 << 29), IRQD_IRQ_ENABLED_ON_SUSPEND = (1 << 30), + IRQD_IRQ_FLOW_MASKED = (1 << 31), }; #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) @@ -351,6 +354,11 @@ static inline bool irqd_irq_masked(struct irq_data *d) return __irqd_to_state(d) & IRQD_IRQ_MASKED; } +static inline bool irqd_irq_flow_masked(struct irq_data *d) +{ + return __irqd_to_state(d) & IRQD_IRQ_FLOW_MASKED; +} + static inline bool irqd_irq_inprogress(struct irq_data *d) { return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; @@ -569,6 +577,7 @@ struct irq_chip { * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs * in the suspend path if they are in disabled state + * IRQCHIP_AUTOMASKS_FLOW: chip->ack() masks and chip->eoi() unmasks */ enum { IRQCHIP_SET_TYPE_MASKED = (1 << 0), @@ -581,6 +590,7 @@ enum { IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), IRQCHIP_SUPPORTS_NMI = (1 << 8), IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), + IRQCHIP_AUTOMASKS_FLOW = (1 << 10), }; #include diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 7f04c7d8296e..21a21baa1366 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -173,6 +173,11 @@ static void irq_state_clr_masked(struct irq_desc *desc) irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); } +static void irq_state_clr_flow_masked(struct irq_desc *desc) +{ + irqd_clear(&desc->irq_data, IRQD_IRQ_FLOW_MASKED); +} + static void irq_state_clr_started(struct irq_desc *desc) { irqd_clear(&desc->irq_data, IRQD_IRQ_STARTED); diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c index e4cff358b437..3ae83622d701 100644 --- a/kernel/irq/debugfs.c +++ b/kernel/irq/debugfs.c @@ -58,6 +58,7 @@ static const struct irq_bit_descr irqchip_flags[] = { BIT_MASK_DESCR(IRQCHIP_SUPPORTS_LEVEL_MSI), BIT_MASK_DESCR(IRQCHIP_SUPPORTS_NMI), BIT_MASK_DESCR(IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND), + BIT_MASK_DESCR(IRQCHIP_AUTOMASKS_FLOW), }; static void @@ -103,6 +104,7 @@ static const struct irq_bit_descr irqdata_states[] = { BIT_MASK_DESCR(IRQD_IRQ_STARTED), BIT_MASK_DESCR(IRQD_IRQ_DISABLED), BIT_MASK_DESCR(IRQD_IRQ_MASKED), + BIT_MASK_DESCR(IRQD_IRQ_FLOW_MASKED), BIT_MASK_DESCR(IRQD_IRQ_INPROGRESS), BIT_MASK_DESCR(IRQD_PER_CPU), diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 54363527feea..b6c1cceddec0 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -245,6 +245,11 @@ static inline void irq_state_set_masked(struct irq_desc *desc) irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); } +static inline void irq_state_set_flow_masked(struct irq_desc *desc) +{ + irqd_set(&desc->irq_data, IRQD_IRQ_FLOW_MASKED); +} + #undef __irqd_to_state static inline void __kstat_incr_irqs_this_cpu(struct irq_desc *desc) From patchwork Tue Jun 29 12:49:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B995C11F68 for ; Tue, 29 Jun 2021 13:20:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2343961D72 for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDdU-00Ayzw-0O; Tue, 29 Jun 2021 13:18:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDCY-00AsyH-Ee for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 12:50:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E886111D4; Tue, 29 Jun 2021 05:50:48 -0700 (PDT) Received: from e113632-lin.cambridge.arm.com (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E7F3E3F718; Tue, 29 Jun 2021 05:50:47 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 02/13] genirq: Define ack_irq() and eoi_irq() helpers Date: Tue, 29 Jun 2021 13:49:59 +0100 Message-Id: <20210629125010.458872-3-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055054_624756_92A807C8 X-CRM114-Status: UNSURE ( 9.21 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The newly-added IRQCHIP_AUTOMASKS_FLOW flag requires some additional bookkeeping around chip->{irq_ack, irq_eoi}() calls. Define wrappers around those chip callbacks to drive the IRQD_IRQ_FLOW_MASKED state of an IRQ when the chip has the IRQCHIP_AUTOMASKS_FLOW flag. Signed-off-by: Valentin Schneider --- kernel/irq/chip.c | 16 ++++++++++++++++ kernel/irq/internals.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 21a21baa1366..793dbd8307b9 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -408,6 +408,22 @@ void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) cpumask_clear_cpu(cpu, desc->percpu_enabled); } +void ack_irq(struct irq_desc *desc) +{ + desc->irq_data.chip->irq_ack(&desc->irq_data); + + if (desc->irq_data.chip->flags & IRQCHIP_AUTOMASKS_FLOW) + irq_state_set_flow_masked(desc); +} + +void eoi_irq(struct irq_desc *desc) +{ + desc->irq_data.chip->irq_eoi(&desc->irq_data); + + if (desc->irq_data.chip->flags & IRQCHIP_AUTOMASKS_FLOW) + irq_state_clr_flow_masked(desc); +} + static inline void mask_ack_irq(struct irq_desc *desc) { if (desc->irq_data.chip->irq_mask_ack) { diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index b6c1cceddec0..6d6a621dc74c 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -87,6 +87,8 @@ extern void irq_enable(struct irq_desc *desc); extern void irq_disable(struct irq_desc *desc); extern void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu); extern void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu); +extern void ack_irq(struct irq_desc *desc); +extern void eoi_irq(struct irq_desc *desc); extern void mask_irq(struct irq_desc *desc); extern void unmask_irq(struct irq_desc *desc); extern void unmask_threaded_irq(struct irq_desc *desc); From patchwork Tue Jun 29 12:50:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C764C11F66 for ; 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bh=Tc8RMAwgOegy3MbMYti/2eq6mB+oO5kcs0jFheVc2QU=; b=YVRwfWu/se5NO0BNgVsGfmsR3J qHisWkoSV9kgdOla3hqhFD7ZEMg3eTuKKez7ibEi8OnKCkd8eeyMcMNhtbuVsoKVCVrskmljhXGxL GC9XfifuYTSncl48isVySBgcZiHu+iTcqBZSATIo5w4OH4BGLiRLyqv5LLaekSIxNEV/T7h/qmSYq tLz9XpTZ4VI1ulAw1M2AQIU4gwrt65cSXR81ok4bYdYVMmMHf2DXGjAj5aGQQNZRDcVHNrLjF9ewD BNuYVMIOkn81/E/YdoBOlf+CJzjKzSh4DKsNqJLrqg4EOStMuMzio697OYROKRAEaDLqcs1Q64wb0 OFyQLVuw==; Received: from foss.arm.com ([217.140.110.172]) by desiato.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDCa-00Cu9B-SU for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 12:50:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 28EAD11FB; Tue, 29 Jun 2021 05:50:50 -0700 (PDT) Received: from e113632-lin.cambridge.arm.com (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 288633F718; Tue, 29 Jun 2021 05:50:49 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 03/13] genirq: Employ ack_irq() and eoi_irq() where relevant Date: Tue, 29 Jun 2021 13:50:00 +0100 Message-Id: <20210629125010.458872-4-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_135057_125193_8D0311D8 X-CRM114-Status: GOOD ( 11.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This can easily be coccinelle'd to replace all existing chip->irq_{ack, eoi} callsites, however not all callsites benefit from this replacement: fasteoi flow handlers for instance only deal with an ->irq_eoi() callback. Instead, only patch callsites that can benefit from the added functionality. Signed-off-by: Valentin Schneider --- kernel/irq/chip.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 793dbd8307b9..4d3bde55c5d9 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -429,10 +429,12 @@ static inline void mask_ack_irq(struct irq_desc *desc) if (desc->irq_data.chip->irq_mask_ack) { desc->irq_data.chip->irq_mask_ack(&desc->irq_data); irq_state_set_masked(desc); + if (desc->irq_data.chip->flags & IRQCHIP_AUTOMASKS_FLOW) + irq_state_set_flow_masked(desc); } else { mask_irq(desc); if (desc->irq_data.chip->irq_ack) - desc->irq_data.chip->irq_ack(&desc->irq_data); + ack_irq(desc); } } @@ -463,7 +465,7 @@ void unmask_threaded_irq(struct irq_desc *desc) struct irq_chip *chip = desc->irq_data.chip; if (chip->flags & IRQCHIP_EOI_THREADED) - chip->irq_eoi(&desc->irq_data); + eoi_irq(desc); unmask_irq(desc); } @@ -680,7 +682,7 @@ EXPORT_SYMBOL_GPL(handle_level_irq); static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) { if (!(desc->istate & IRQS_ONESHOT)) { - chip->irq_eoi(&desc->irq_data); + eoi_irq(desc); return; } /* @@ -691,10 +693,10 @@ static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) */ if (!irqd_irq_disabled(&desc->irq_data) && irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { - chip->irq_eoi(&desc->irq_data); + eoi_irq(desc); unmask_irq(desc); } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { - chip->irq_eoi(&desc->irq_data); + eoi_irq(desc); } } From patchwork Tue Jun 29 12:50:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5067AC11F66 for ; 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Tue, 29 Jun 2021 05:50:50 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 04/13] genirq: Add handle_strict_flow_irq() flow handler Date: Tue, 29 Jun 2021 13:50:01 +0100 Message-Id: <20210629125010.458872-5-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055054_091143_7F83E269 X-CRM114-Status: GOOD ( 17.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GIC family of irqchips have been so far treated as "fasteoi" chips. As handle_fasteoi_irq() states, this implies: * Only a single callback will be issued to the chip: an ->eoi() * call when the interrupt has been serviced. However, the GICs have an operating mode (EOImode=1) which requires an additional chip interaction during the IRQ handling. Said operating mode already has some uses with virtualization, but could also be leveraged to slightly optimize ONESHOT IRQs. This extra interaction is currently hidden away in the drivers, but further exploiting its effects (see IRQD_IRQ_FLOW_MASKED) requires lifting it from the driver code into core code. It so happens that it fits the role of ->irq_ack(); unfortunately, the GICs require both callbacks to be strictly paired with one another: for a given IRQ activation, there must be a single ->irq_ack() followed by a single ->irq_eoi(). No more, no less, and in that order. Introduce a new flow handler which guarantees said ack / eoi pairing. Note that it is strikingly similar to handle_fasteoi_mask_irq() for now, but will be further modified in later patches Signed-off-by: Valentin Schneider --- include/linux/irq.h | 1 + kernel/irq/chip.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index ef179245a642..37075929e329 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -663,6 +663,7 @@ extern void handle_edge_irq(struct irq_desc *desc); extern void handle_edge_eoi_irq(struct irq_desc *desc); extern void handle_simple_irq(struct irq_desc *desc); extern void handle_untracked_irq(struct irq_desc *desc); +extern void handle_strict_flow_irq(struct irq_desc *desc); extern void handle_percpu_irq(struct irq_desc *desc); extern void handle_percpu_devid_irq(struct irq_desc *desc); extern void handle_bad_irq(struct irq_desc *desc); diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 4d3bde55c5d9..699e70b51aae 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -896,6 +896,54 @@ void handle_edge_eoi_irq(struct irq_desc *desc) } #endif +/** + * handle_strict_flow_irq - irq handler for strict controllers + * @desc: the interrupt description structure for this irq + * + * Ensures strict pairing of ->ack() and ->eoi() for any IRQ passing + * through here. The ->eoi() may be deferred to the tail of the IRQ thread + * for ONESHOT IRQs. + */ +void handle_strict_flow_irq(struct irq_desc *desc) +{ + struct irq_chip *chip = desc->irq_data.chip; + + raw_spin_lock(&desc->lock); + mask_ack_irq(desc); + + if (!irq_may_run(desc)) + goto out; + + desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); + + /* + * If it's disabled or no action available then keep it masked and + * get out of here: + */ + if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { + desc->istate |= IRQS_PENDING; + goto out; + } + + kstat_incr_irqs_this_cpu(desc); + + handle_irq_event(desc); + + cond_unmask_eoi_irq(desc, chip); + + raw_spin_unlock(&desc->lock); + return; +out: + /* + * XXX: this is where IRQCHIP_EOI_IF_HANDLED would be checked, but + * it's conceptually incompatible with this handler (it breaks the + * strict pairing) + */ + eoi_irq(desc); + raw_spin_unlock(&desc->lock); +} +EXPORT_SYMBOL_GPL(handle_strict_flow_irq); + /** * handle_percpu_irq - Per CPU local irq handler * @desc: the interrupt description structure for this irq From patchwork Tue Jun 29 12:50:02 2021 Content-Type: text/plain; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDgn-00AzuQ-Ht; Tue, 29 Jun 2021 13:22:09 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDCe-00At16-6J for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 12:51:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9C2FD13D5; Tue, 29 Jun 2021 05:50:52 -0700 (PDT) Received: from e113632-lin.cambridge.arm.com (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 917883F718; Tue, 29 Jun 2021 05:50:51 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 05/13] genirq: Let purely flow-masked ONESHOT irqs through unmask_threaded_irq() Date: Tue, 29 Jun 2021 13:50:02 +0100 Message-Id: <20210629125010.458872-6-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055100_333683_F4E1651B X-CRM114-Status: GOOD ( 10.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A subsequent patch will let IRQs end up in irq_finalize_oneshot() without IRQD_IRQ_MASKED, but with IRQD_IRQ_FLOW_MASKED set instead. Let such IRQs receive their final ->irq_eoi(). Signed-off-by: Valentin Schneider --- kernel/irq/manage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index ef30b4762947..e6d6d32ddcbc 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -1107,7 +1107,7 @@ static void irq_finalize_oneshot(struct irq_desc *desc, desc->threads_oneshot &= ~action->thread_mask; if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && - irqd_irq_masked(&desc->irq_data)) + (irqd_irq_masked(&desc->irq_data) | irqd_irq_flow_masked(&desc->irq_data))) unmask_threaded_irq(desc); out_unlock: From patchwork Tue Jun 29 12:50:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DE09C11F66 for ; Tue, 29 Jun 2021 13:25:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 02B0D61D7B for ; Tue, 29 Jun 2021 13:25:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 02B0D61D7B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+gcOJA81KKqU22uyDDhm0tCrXc81UXT0D/5Pzb1vP2U=; b=z9iJfhhU1CQFMd HP9grwYH1KKVxk0+KF3zkiSqFiQFaPxVRSoCqEjPWad3EO/r2MR1z18r6uVAsoNtWiRFgMO23gZam 4FBEbI0eTBIuGr3uW2oqOzZkYOcxq934brKG+jsYxQ2npKsN12ks6QWjC/Amekv6Ptnt7tnc8GmaI wF/+bO+EmHlrYnzSiX8iJmMPbtriOLnCmRedNG971KU+taSHgqAalz+i3QfncbP5TAypi4EHjwg7/ cs994HkjarN5xbBOuqU4P49fjTwXmJoQeIE7pYPeJ4ti4+mKuEdnKzCvK8CPFqdzCFPRe1hFwpKMv kXaxUAKcwcAThIUUdC9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDiV-00B0OL-4E; Tue, 29 Jun 2021 13:23:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDCf-00At20-9j for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 12:51:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF188143B; Tue, 29 Jun 2021 05:50:53 -0700 (PDT) Received: from e113632-lin.cambridge.arm.com (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CEFB53F718; Tue, 29 Jun 2021 05:50:52 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 06/13] genirq: Don't mask IRQ within flow handler if IRQ is flow-masked Date: Tue, 29 Jun 2021 13:50:03 +0100 Message-Id: <20210629125010.458872-7-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055101_470616_4268B5F6 X-CRM114-Status: GOOD ( 14.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org mask_irq() lets an IRQ with IRQD_IRQ_FLOW_MASKED set be further masked via chip->irq_mask(). This is necessary for unhandled IRQs as we want to keep them masked beyond eoi_irq() (which clears IRQD_IRQ_FLOW_MASKED). This is however not necessary in paths that do end up handling the IRQ and are bounded by a final eoi_irq() - this is the case for chips with IRQCHIP_AUTOMASKS_FLOW and IRQCHIP_EOI_THREADED. Make handle_strict_flow_irq() leverage IRQCHIP_AUTOMASKS_FLOW and issue an ack_irq() rather than a mask_ack_irq() when possible. Signed-off-by: Valentin Schneider --- kernel/irq/chip.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 699e70b51aae..c2ca6b748987 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -896,6 +896,12 @@ void handle_edge_eoi_irq(struct irq_desc *desc) } #endif +/* + * AUTOMASKS_FLOW tells us ack/eoi handle the masking, EOI_THREADED tells us + * that masking will persist until irq_finalize_oneshot() + */ +#define ONESHOT_AUTOMASK_FLAGS (IRQCHIP_AUTOMASKS_FLOW | IRQCHIP_EOI_THREADED) + /** * handle_strict_flow_irq - irq handler for strict controllers * @desc: the interrupt description structure for this irq @@ -909,10 +915,9 @@ void handle_strict_flow_irq(struct irq_desc *desc) struct irq_chip *chip = desc->irq_data.chip; raw_spin_lock(&desc->lock); - mask_ack_irq(desc); if (!irq_may_run(desc)) - goto out; + goto out_mask; desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); @@ -922,10 +927,20 @@ void handle_strict_flow_irq(struct irq_desc *desc) */ if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { desc->istate |= IRQS_PENDING; - goto out; + goto out_mask; } kstat_incr_irqs_this_cpu(desc); + /* + * Masking is required if IRQ is ONESHOT and we can't rely on the + * flow-masking persisting down to irq_finalize_oneshot() + * (in the IRQ thread). + */ + if ((desc->istate & IRQS_ONESHOT) && + ((chip->flags & ONESHOT_AUTOMASK_FLAGS) != ONESHOT_AUTOMASK_FLAGS)) + mask_ack_irq(desc); + else + ack_irq(desc); handle_irq_event(desc); @@ -933,7 +948,8 @@ void handle_strict_flow_irq(struct irq_desc *desc) raw_spin_unlock(&desc->lock); return; -out: +out_mask: + mask_ack_irq(desc); /* * XXX: this is where IRQCHIP_EOI_IF_HANDLED would be checked, but * it's conceptually incompatible with this handler (it breaks the From patchwork Tue Jun 29 12:50:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDB52C11F66 for ; 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Tue, 29 Jun 2021 05:50:53 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 07/13] genirq, irq-gic-v3: Make NMI flow handlers use ->irq_ack() if available Date: Tue, 29 Jun 2021 13:50:04 +0100 Message-Id: <20210629125010.458872-8-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055101_532296_CF7BB3D5 X-CRM114-Status: GOOD ( 15.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Subsequent patches will make the gic-v3 irqchip use an ->irq_ack() callback. As a preparation, make the NMI flow handlers call said callback if it is available. Since this departs from the fasteoi scheme of only issuing a suffix ->eoi(), rename the NMI flow handlers. Signed-off-by: Valentin Schneider --- drivers/irqchip/irq-gic-v3.c | 4 ++-- include/linux/irq.h | 4 ++-- kernel/irq/chip.c | 25 ++++++++++++++----------- 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 37a23aa6de37..af11396996e3 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -484,10 +484,10 @@ static int gic_irq_nmi_setup(struct irq_data *d) /* Setting up PPI as NMI, only switch handler for first NMI */ if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { refcount_set(&ppi_nmi_refs[idx], 1); - desc->handle_irq = handle_percpu_devid_fasteoi_nmi; + desc->handle_irq = handle_percpu_devid_nmi; } } else { - desc->handle_irq = handle_fasteoi_nmi; + desc->handle_irq = handle_nmi; } gic_irq_set_prio(d, GICD_INT_NMI_PRI); diff --git a/include/linux/irq.h b/include/linux/irq.h index 37075929e329..0b45e42812d6 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -669,8 +669,8 @@ extern void handle_percpu_devid_irq(struct irq_desc *desc); extern void handle_bad_irq(struct irq_desc *desc); extern void handle_nested_irq(unsigned int irq); -extern void handle_fasteoi_nmi(struct irq_desc *desc); -extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc); +extern void handle_nmi(struct irq_desc *desc); +extern void handle_percpu_devid_nmi(struct irq_desc *desc); extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); extern int irq_chip_pm_get(struct irq_data *data); diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index c2ca6b748987..099bc7e13d1b 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -748,18 +748,16 @@ void handle_fasteoi_irq(struct irq_desc *desc) EXPORT_SYMBOL_GPL(handle_fasteoi_irq); /** - * handle_fasteoi_nmi - irq handler for NMI interrupt lines + * handle_nmi - irq handler for NMI interrupt lines * @desc: the interrupt description structure for this irq * * A simple NMI-safe handler, considering the restrictions * from request_nmi. * - * Only a single callback will be issued to the chip: an ->eoi() - * call when the interrupt has been serviced. This enables support - * for modern forms of interrupt handlers, which handle the flow - * details in hardware, transparently. + * An ->ack() callback will be issued before servicing the interrupt, + * followed by an ->eoi() call. */ -void handle_fasteoi_nmi(struct irq_desc *desc) +void handle_nmi(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct irqaction *action = desc->action; @@ -768,6 +766,9 @@ void handle_fasteoi_nmi(struct irq_desc *desc) __kstat_incr_irqs_this_cpu(desc); + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); + trace_irq_handler_entry(irq, action); /* * NMIs cannot be shared, there is only one action. @@ -778,7 +779,7 @@ void handle_fasteoi_nmi(struct irq_desc *desc) if (chip->irq_eoi) chip->irq_eoi(&desc->irq_data); } -EXPORT_SYMBOL_GPL(handle_fasteoi_nmi); +EXPORT_SYMBOL_GPL(handle_nmi); /** * handle_edge_irq - edge type IRQ handler @@ -1032,14 +1033,13 @@ void handle_percpu_devid_irq(struct irq_desc *desc) } /** - * handle_percpu_devid_fasteoi_nmi - Per CPU local NMI handler with per cpu + * handle_percpu_devid_nmi - Per CPU local NMI handler with per cpu * dev ids * @desc: the interrupt description structure for this irq * - * Similar to handle_fasteoi_nmi, but handling the dev_id cookie - * as a percpu pointer. + * Similar to handle_nmi, but handling the dev_id cookie as a percpu pointer. */ -void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc) +void handle_percpu_devid_nmi(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct irqaction *action = desc->action; @@ -1048,6 +1048,9 @@ void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc) __kstat_incr_irqs_this_cpu(desc); + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); + trace_irq_handler_entry(irq, action); res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id)); trace_irq_handler_exit(irq, action, res); From patchwork Tue Jun 29 12:50:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 793B1C11F66 for ; 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Tue, 29 Jun 2021 05:50:55 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 08/13] genirq/msi: Provide default .irq_eoi() for MSI chips Date: Tue, 29 Jun 2021 13:50:05 +0100 Message-Id: <20210629125010.458872-9-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055102_110519_59C33F52 X-CRM114-Status: GOOD ( 11.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently only platform-MSI irqchips get a default .irq_eoi() when MSI_FLAG_USE_DEF_CHIP_OPS is set. There's no reason PCI-MSI irqchips couldn't benefit from this too, so let all MSI irqchips benefit from this default. Signed-off-by: Valentin Schneider --- drivers/base/platform-msi.c | 2 -- kernel/irq/msi.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/base/platform-msi.c b/drivers/base/platform-msi.c index 0b72b134a304..659881da0593 100644 --- a/drivers/base/platform-msi.c +++ b/drivers/base/platform-msi.c @@ -101,8 +101,6 @@ static void platform_msi_update_chip_ops(struct msi_domain_info *info) chip->irq_mask = irq_chip_mask_parent; if (!chip->irq_unmask) chip->irq_unmask = irq_chip_unmask_parent; - if (!chip->irq_eoi) - chip->irq_eoi = irq_chip_eoi_parent; if (!chip->irq_set_affinity) chip->irq_set_affinity = msi_domain_set_affinity; if (!chip->irq_write_msi_msg) diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index c41965e348b5..c97590945e99 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -274,6 +274,8 @@ static void msi_domain_update_chip_ops(struct msi_domain_info *info) BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask); if (!chip->irq_set_affinity) chip->irq_set_affinity = msi_domain_set_affinity; + if (!chip->irq_eoi) + chip->irq_eoi = irq_chip_eoi_parent; } /** From patchwork Tue Jun 29 12:50:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349871 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C526C11F66 for ; Tue, 29 Jun 2021 13:29:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23F0B61D7B for ; Tue, 29 Jun 2021 13:29:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 23F0B61D7B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lqnkHRGlDPvSRH9aeBg/GKXvW4ph3jDpTjVPYWp1jWk=; b=5EcgduJvpGTaz5 hE6uqa7HTK6K8xh+pQPtSzOXNYE4aIkbscTLMkB8A3Ink/KVIL2nzod8qJVoG/7fgn4GRkDjUwJdl epBiXb7Y9pM+BzfxKHEv50Ei74IBnRCJkJDEw5V1ajkpqeg1R9N9hRdAgQFNZANZRwx65AsY7LTT8 F48A5xi7pZ2rJ3fikM7h8rOWj0f06x/9oE2MauaahMFycyhZUdUFwhxRZubweQ9ffy/XfmEjzGtzG jsu1T4YQ0U+pdjRGsoUN7rhJxiXlskAZ/Ze1F2wp1DGLr/6Becn/WGcye7GsP+fNABEwgVqNTAUaj Ap3InHZ2JSBgrFm7+N9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDlR-00B1CV-UE; Tue, 29 Jun 2021 13:26:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDCf-00At27-E4 for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 12:51:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 783DF1478; Tue, 29 Jun 2021 05:50:57 -0700 (PDT) Received: from e113632-lin.cambridge.arm.com (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 778083F718; Tue, 29 Jun 2021 05:50:56 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 09/13] irqchip/gic: Rely on MSI default .irq_eoi() Date: Tue, 29 Jun 2021 13:50:06 +0100 Message-Id: <20210629125010.458872-10-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055101_610276_D212D29F X-CRM114-Status: UNSURE ( 9.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Previously, only platform-MSI irqchips would get a default .irq_eoi(). GIC-based platform-MSI irqchip's rely on this default callback, while PCI-MSI ones are initialized explicitly. As all MSI domains now get a default .irq_eoi(), drop the explicit .irq_eoi() initialization for PCI-MSI chips. Signed-off-by: Valentin Schneider --- drivers/irqchip/irq-gic-v2m.c | 1 - drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c | 1 - drivers/irqchip/irq-gic-v3-its-pci-msi.c | 1 - drivers/irqchip/irq-gic-v3-mbi.c | 1 - 4 files changed, 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index be9ea6fd6f8b..27a97c76ba0d 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -87,7 +87,6 @@ static struct irq_chip gicv2m_msi_irq_chip = { .name = "MSI", .irq_mask = gicv2m_mask_msi_irq, .irq_unmask = gicv2m_unmask_msi_irq, - .irq_eoi = irq_chip_eoi_parent, .irq_write_msi_msg = pci_msi_domain_write_msg, }; diff --git a/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c b/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c index 634263dfd7b5..105ee646cd12 100644 --- a/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c +++ b/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c @@ -21,7 +21,6 @@ static struct irq_chip its_msi_irq_chip = { .name = "ITS-fMSI", .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, - .irq_eoi = irq_chip_eoi_parent, .irq_set_affinity = msi_domain_set_affinity }; diff --git a/drivers/irqchip/irq-gic-v3-its-pci-msi.c b/drivers/irqchip/irq-gic-v3-its-pci-msi.c index ad2810c017ed..14f6e63c630c 100644 --- a/drivers/irqchip/irq-gic-v3-its-pci-msi.c +++ b/drivers/irqchip/irq-gic-v3-its-pci-msi.c @@ -27,7 +27,6 @@ static struct irq_chip its_msi_irq_chip = { .name = "ITS-MSI", .irq_unmask = its_unmask_msi_irq, .irq_mask = its_mask_msi_irq, - .irq_eoi = irq_chip_eoi_parent, .irq_write_msi_msg = pci_msi_domain_write_msg, }; diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-mbi.c index e81e89a81cb5..a69ac299a533 100644 --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c @@ -169,7 +169,6 @@ static struct irq_chip mbi_msi_irq_chip = { .name = "MSI", .irq_mask = mbi_mask_msi_irq, .irq_unmask = mbi_unmask_msi_irq, - .irq_eoi = irq_chip_eoi_parent, .irq_compose_msi_msg = mbi_compose_msi_msg, .irq_write_msi_msg = pci_msi_domain_write_msg, }; From patchwork Tue Jun 29 12:50:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349869 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AAD8C11F66 for ; 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Tue, 29 Jun 2021 05:50:57 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 10/13] genirq/msi: Provide default .irq_ack() for MSI chips Date: Tue, 29 Jun 2021 13:50:07 +0100 Message-Id: <20210629125010.458872-11-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055101_433574_262B0A17 X-CRM114-Status: UNSURE ( 9.28 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MSI_FLAG_USE_DEF_CHIP_OPS can now provide a default .irq_eoi() to any irqchip attached to an MSI domain. Complement it by adding a default .irq_ack() implementation. Signed-off-by: Valentin Schneider --- kernel/irq/msi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index c97590945e99..127e0dd72b60 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -274,6 +274,8 @@ static void msi_domain_update_chip_ops(struct msi_domain_info *info) BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask); if (!chip->irq_set_affinity) chip->irq_set_affinity = msi_domain_set_affinity; + if (!chip->irq_ack) + chip->irq_ack = irq_chip_ack_parent; if (!chip->irq_eoi) chip->irq_eoi = irq_chip_eoi_parent; } From patchwork Tue Jun 29 12:50:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E939CC11F66 for ; Tue, 29 Jun 2021 13:30:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ACFC661D4D for ; Tue, 29 Jun 2021 13:30:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ACFC661D4D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ljE4WOU2d/TX9CNNSiE+36Hq2kZLXr0CeqlTxVePTGo=; b=ieGr3sZpyacOBc M+aj/EXyTZcLMEz1c2tB5f12yZk5Peq6bUdjzaGp+06sNyrBIJa+FBHqs42L5XdWxKYZG0blxucCN Xg1SpwhpY4mlOZX3GRQ6qLfCtRoazqLq1LbGEYZMXzK63GtFoXNq6bc1qlxXjF/EzFSyJnYR/s69y gG2RkjJoM1BmT7RIzl3UAaaYiyteItugH6Gs/QsE/lmiyrO7w7VjJ/xiFJpJKX7GNcUL//B2doAu+ 6A6Y0QucXuTIkXiJHdtqKIXzw9kZMxCgQw9ERmioZJPlfk/9jo/n04tKoeSi0/HTbv0mUOEqvmWGo T7/2pePWlx1laTAfolCQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDmp-00B1cl-Pa; Tue, 29 Jun 2021 13:28:24 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDCf-00At26-Jo for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 12:51:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB141106F; Tue, 29 Jun 2021 05:50:59 -0700 (PDT) Received: from e113632-lin.cambridge.arm.com (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EA71F3F718; Tue, 29 Jun 2021 05:50:58 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 11/13] irqchip/gic: Add .irq_ack() to GIC-based irqchips Date: Tue, 29 Jun 2021 13:50:08 +0100 Message-Id: <20210629125010.458872-12-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055101_743382_C6E1EA99 X-CRM114-Status: GOOD ( 11.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Subsequent patches will make the GIC IRQs use a flow handler that issues an irq_ack(), thus irqchips of child domains need to have an .irq_ack() of their own. Most cases are covered by the default MSI callbacks, but nexus domains and other non-MSI domains still need tending do. Signed-off-by: Valentin Schneider --- drivers/irqchip/irq-gic-v2m.c | 1 + drivers/irqchip/irq-gic-v3-its.c | 3 +++ drivers/irqchip/irq-gic-v3-mbi.c | 1 + 3 files changed, 5 insertions(+) diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index 27a97c76ba0d..b8cf3ff87b15 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -126,6 +126,7 @@ static struct irq_chip gicv2m_irq_chip = { .name = "GICv2m", .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, + .irq_ack = irq_chip_ack_parent, .irq_eoi = irq_chip_eoi_parent, .irq_set_affinity = irq_chip_set_affinity_parent, .irq_compose_msi_msg = gicv2m_compose_msi_msg, diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index ba39668c3e08..8a372ac0079e 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1976,6 +1976,7 @@ static struct irq_chip its_irq_chip = { .name = "ITS", .irq_mask = its_mask_irq, .irq_unmask = its_unmask_irq, + .irq_ack = irq_chip_ack_parent, .irq_eoi = irq_chip_eoi_parent, .irq_set_affinity = its_set_affinity, .irq_compose_msi_msg = its_irq_compose_msi_msg, @@ -3997,6 +3998,7 @@ static struct irq_chip its_vpe_irq_chip = { .name = "GICv4-vpe", .irq_mask = its_vpe_mask_irq, .irq_unmask = its_vpe_unmask_irq, + .irq_ack = irq_chip_ack_parent, .irq_eoi = irq_chip_eoi_parent, .irq_set_affinity = its_vpe_set_affinity, .irq_retrigger = its_vpe_retrigger, @@ -4152,6 +4154,7 @@ static struct irq_chip its_vpe_4_1_irq_chip = { .name = "GICv4.1-vpe", .irq_mask = its_vpe_4_1_mask_irq, .irq_unmask = its_vpe_4_1_unmask_irq, + .irq_ack = irq_chip_ack_parent, .irq_eoi = irq_chip_eoi_parent, .irq_set_affinity = its_vpe_set_affinity, .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity, diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-mbi.c index a69ac299a533..b0e919f78191 100644 --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c @@ -33,6 +33,7 @@ static struct irq_chip mbi_irq_chip = { .name = "MBI", .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, + .irq_ack = irq_chip_ack_parent, .irq_eoi = irq_chip_eoi_parent, .irq_set_type = irq_chip_set_type_parent, .irq_set_affinity = irq_chip_set_affinity_parent, From patchwork Tue Jun 29 12:50:09 2021 Content-Type: text/plain; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDqa-00B2xX-Lv; Tue, 29 Jun 2021 13:32:17 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyDCg-00At16-SC for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 12:51:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2CCDD11B3; Tue, 29 Jun 2021 05:51:01 -0700 (PDT) Received: from e113632-lin.cambridge.arm.com (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2AF003F718; Tue, 29 Jun 2021 05:51:00 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 12/13] irqchip/gic: Convert to handle_strict_flow_irq() Date: Tue, 29 Jun 2021 13:50:09 +0100 Message-Id: <20210629125010.458872-13-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055103_007362_206C4D56 X-CRM114-Status: GOOD ( 14.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that the proper infrastructure is in place, convert the irq-gic chip to use handle_strict_flow_irq() along with IRQCHIP_AUTOMASKS_FLOW. For EOImode=1, the Priority Drop is moved from gic_handle_irq() into chip->irq_ack(). This effectively pushes the EOI write down into ->handle_irq(), but doesn't change its ordering wrt the irqaction handling. The EOImode=1 irqchip also gains IRQCHIP_EOI_THREADED, which allows the ->irq_eoi() call to be deferred to the tail of ONESHOT IRQ threads. This means a threaded ONESHOT IRQ can now be handled entirely without a single chip->irq_mask() call. EOImode=0 handling remains unchanged. Signed-off-by: Valentin Schneider --- drivers/irqchip/irq-gic.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 46c9c5fafdbc..f278b39b2238 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -344,8 +344,6 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) if (unlikely(irqnr >= 1020)) break; - if (static_branch_likely(&supports_deactivate_key)) - writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); isb(); /* @@ -1009,7 +1007,9 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, break; default: irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, - handle_fasteoi_irq, NULL, NULL); + static_branch_likely(&supports_deactivate_key) ? + handle_strict_flow_irq : handle_fasteoi_irq, + NULL, NULL); irq_set_probe(irq); irqd_set_single_target(irqd); break; @@ -1113,8 +1113,16 @@ static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, if (use_eoimode1) { gic->chip.irq_mask = gic_eoimode1_mask_irq; + gic->chip.irq_ack = gic_eoi_irq; gic->chip.irq_eoi = gic_eoimode1_eoi_irq; gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; + + /* + * eoimode0 shouldn't expose FLOW_MASK because the priority + * drop is undissociable from the deactivation, and we do need + * the priority drop to happen within the flow handler. + */ + gic->chip.flags |= IRQCHIP_AUTOMASKS_FLOW | IRQCHIP_EOI_THREADED; } if (gic == &gic_data[0]) { From patchwork Tue Jun 29 12:50:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Schneider X-Patchwork-Id: 12349881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B4D4C11F66 for ; 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Tue, 29 Jun 2021 05:51:01 -0700 (PDT) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: [PATCH v3 13/13] irqchip/gic-v3: Convert to handle_strict_flow_irq() Date: Tue, 29 Jun 2021 13:50:10 +0100 Message-Id: <20210629125010.458872-14-valentin.schneider@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629125010.458872-1-valentin.schneider@arm.com> References: <20210629125010.458872-1-valentin.schneider@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_055104_007215_C452D88E X-CRM114-Status: GOOD ( 15.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that the proper infrastructure is in place, convert the irq-gic-v3 chip to use handle_strict_flow_irq() along with IRQCHIP_AUTOMASKS_FLOW. For EOImode=1, the Priority Drop is moved from gic_handle_irq() into chip->irq_ack(). This effectively pushes the EOIR write down into ->handle_irq(), but doesn't change its ordering wrt the irqaction handling. The EOImode=1 irqchip also gains IRQCHIP_EOI_THREADED, which allows the ->irq_eoi() call to be deferred to the tail of ONESHOT IRQ threads. This means a threaded ONESHOT IRQ can now be handled entirely without a single chip->irq_mask() call. Despite not having an Active state, LPIs are made to use handle_strict_flow_irq() as well. This lets them re-use gic_eoimode1_chip.irq_ack() as Priority Drop, rather than special-case them in gic_handle_irq(). EOImode=0 handling remains unchanged. Signed-off-by: Valentin Schneider --- drivers/irqchip/irq-gic-v3.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index af11396996e3..c2677c5353a4 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -626,8 +626,6 @@ static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) if (irqs_enabled) nmi_enter(); - if (static_branch_likely(&supports_deactivate_key)) - gic_write_eoir(irqnr); /* * Leave the PSR.I bit set to prevent other NMIs to be * received while handling this one. @@ -663,9 +661,11 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs gic_arch_enable_irqs(); } - if (static_branch_likely(&supports_deactivate_key)) - gic_write_eoir(irqnr); - else + /* + * eoimode1 will give us an isb in handle_domain_irq(), before + * handle_irq_event(). + */ + if (!static_branch_likely(&supports_deactivate_key)) isb(); if (handle_domain_irq(gic_data.domain, irqnr, regs)) { @@ -1276,6 +1276,7 @@ static struct irq_chip gic_eoimode1_chip = { .name = "GICv3", .irq_mask = gic_eoimode1_mask_irq, .irq_unmask = gic_unmask_irq, + .irq_ack = gic_eoi_irq, .irq_eoi = gic_eoimode1_eoi_irq, .irq_set_type = gic_set_type, .irq_set_affinity = gic_set_affinity, @@ -1288,7 +1289,9 @@ static struct irq_chip gic_eoimode1_chip = { .ipi_send_mask = gic_ipi_send_mask, .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE | - IRQCHIP_MASK_ON_SUSPEND, + IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_AUTOMASKS_FLOW | + IRQCHIP_EOI_THREADED, }; static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, @@ -1312,7 +1315,9 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, case SPI_RANGE: case ESPI_RANGE: irq_domain_set_info(d, irq, hw, chip, d->host_data, - handle_fasteoi_irq, NULL, NULL); + static_branch_likely(&supports_deactivate_key) ? + handle_strict_flow_irq : handle_fasteoi_irq, + NULL, NULL); irq_set_probe(irq); irqd_set_single_target(irqd); break; @@ -1321,7 +1326,9 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, if (!gic_dist_supports_lpis()) return -EPERM; irq_domain_set_info(d, irq, hw, chip, d->host_data, - handle_fasteoi_irq, NULL, NULL); + static_branch_likely(&supports_deactivate_key) ? + handle_strict_flow_irq : handle_fasteoi_irq, + NULL, NULL); break; default: