From patchwork Thu Jul 1 21:02:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?S3J6eXN6dG9mIFdpbGN6ee+/ve+/vXNraQ==?= X-Patchwork-Id: 12355093 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 519D1C11F67 for ; Thu, 1 Jul 2021 21:02:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 283E061402 for ; Thu, 1 Jul 2021 21:02:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232926AbhGAVF1 (ORCPT ); Thu, 1 Jul 2021 17:05:27 -0400 Received: from mail-lf1-f44.google.com ([209.85.167.44]:36422 "EHLO mail-lf1-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229934AbhGAVF0 (ORCPT ); Thu, 1 Jul 2021 17:05:26 -0400 Received: by mail-lf1-f44.google.com with SMTP id d16so14220087lfn.3 for ; Thu, 01 Jul 2021 14:02:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=JE6sI1cXi9IoYmq2Jf3nI0zQd5U5PWje0uxRZUNbQZY=; b=tsjCqqRVGRHjll+hgVIyZvD2xPqJGkTw3xWIxVnRISofmWzEkXgcsQoinLTbNgnG9q NP/PXXuNERdQg8RNmH3gS0aYn3uGmmfagPL8GolH6HklMCX3b02HnSThrloQjLFhqAJO qhBfYGBNVv5soOMctltQRArE3n3yDfi6XnwRrNmUaLUZCdEOO+w9NiHH0euwBRf2CTj2 v4k6xdY9T6ciywOMpR9DxoeEbztyonofBYxRRl2lQIrXgmz6tDY7RqSAQ1X2sp6+rIEm s1rUyXhufvQBg3xGOdiLvVX2W5ylAD4ctwtZmORZ4dw9lp5Q7tX6WAHe89lGAHK9LdUU P/rQ== X-Gm-Message-State: AOAM530gxpFjBMCkRz1Jy+Q7fYDXAfYSgaP3CSCi2Kd1asHK6l1FIvm6 NJXxGGJRDwqXIJnI4xw+XLU= X-Google-Smtp-Source: ABdhPJwd/vc5UfafJqN5CCMYGBinKTkl1VjKUD7L0aakEih9zH6usEE+Hhz9EiQELu2soXrTnQ0gTg== X-Received: by 2002:ac2:4f89:: with SMTP id z9mr1218811lfs.46.1625173374134; Thu, 01 Jul 2021 14:02:54 -0700 (PDT) Received: from workstation.lan ([95.155.85.46]) by smtp.gmail.com with ESMTPSA id f21sm72175lfk.212.2021.07.01.14.02.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jul 2021 14:02:53 -0700 (PDT) From: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= To: Jingoo Han Cc: Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , linux-pci@vger.kernel.org Subject: [PATCH] PCI: dwc: Remove surplus break statement after return Date: Thu, 1 Jul 2021 21:02:52 +0000 Message-Id: <20210701210252.1638709-1-kw@linux.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org As part of code refactoring completed in the commit a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code") the function dw_plat_add_pcie_ep() has been removed and the call to the dw_pcie_ep_init() has been moved into dw_plat_pcie_probe(). This change left a break statement behind that is not needed any more as as the function dw_plat_pcie_probe() returns immediately after making a call to dw_pcie_ep_init(). Thus remove this surplus break statement that became a dead code. Suggested-by: Bjorn Helgaas Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/dwc/pcie-designware-plat.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 9b397c807261..8851eb161a0e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -164,7 +164,6 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) pci->ep.ops = &pcie_ep_ops; return dw_pcie_ep_init(&pci->ep); - break; default: dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode); }