From patchwork Wed Jul 7 08:48:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Gallais-Pou X-Patchwork-Id: 12362065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26F87C07E9B for ; Wed, 7 Jul 2021 08:50:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E6C9061CBF for ; Wed, 7 Jul 2021 08:50:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E6C9061CBF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=foss.st.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7kaVYkO9mCRSo1RYTWC8MInUkfxphgvmawomvYydPjg=; b=fskVMJ3RT4XNKX U8uhYjYtTtnzXSb/GwhsyCdqWLsW0X+r4QvvKsj8lDqdwQmNWcPeK+HasE35Z60a8H5jzp1f1yk6W qXQMbK2zmnTN3E7zDV/vi0+78D9ohF00UoBRKI6DmGMRdyqWwIpqqkuTcev0scgX88HEsi7FC9VX/ AXdBI3Klwn1oJHiAP45lvfV1/lgVApHbuPaW2eVkpggChynv+pwJmD96kQZMGXN7c5J26ilGPWVv+ q5wE+Gh12oHOG+qiV53hIRhcVuzPHMP1z99XA2ZDxmNcEbLZN7tVHNCLtOb59KdgK5HsCvJLKRlPL qjBkptq9G4hWWOIeWa0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m13Ew-00E5IM-7a; Wed, 07 Jul 2021 08:49:06 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m13Er-00E5HJ-Ui for linux-arm-kernel@lists.infradead.org; Wed, 07 Jul 2021 08:49:04 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1678fZUn029506; Wed, 7 Jul 2021 10:48:48 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=selector1; bh=eKU02lLY0IdlfNuBs4AUcL0xc5nbjziRkKjN9rzKsyc=; b=AqoF6xfkWkXmmWVurHnYVfBYkqlYJVj1/D314fUYSbG3NrL9hNrUHp4LUiUvfscE7yJM vt+q0vSF5BkS4ZoppINGfzSTk+z1aNRUOROI5qzkKXeLdQM4ZGnqYE1uP8lVOzf7cK7S Ea7cpaf4EV1cPw+T440TVJi8XUXiuRAQMENYUhoU9A70ALmWCZSGALYC4qz3Sc0fYOyY oHfW4au1ktMqjXcQlE/GXreWFVRVzGo/Sb7LWhJ2RBOFeE/e48RbCjdHmW1tCN/pVcnY T4ZuIfnWwjxMxuOcKTMkEijarX2adjCGR1ifxrNb/4BsPUk8rCoy+PPRQ5YgmSBKckfg Ug== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 39n8ysr1ka-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Jul 2021 10:48:48 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D3E3E10002A; Wed, 7 Jul 2021 10:48:47 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node1.st.com [10.75.127.4]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B83FF2171D3; Wed, 7 Jul 2021 10:48:47 +0200 (CEST) Received: from SFHDAG2NODE3.st.com (10.75.127.6) by SFHDAG2NODE1.st.com (10.75.127.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 7 Jul 2021 10:48:47 +0200 Received: from SFHDAG2NODE3.st.com ([fe80::31b3:13bf:2dbe:f64c]) by SFHDAG2NODE3.st.com ([fe80::31b3:13bf:2dbe:f64c%20]) with mapi id 15.00.1497.015; Wed, 7 Jul 2021 10:48:47 +0200 From: Raphael GALLAIS-POU - foss To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Yannick FERTRE - foss , Philippe CORNU - foss , Benjamin Gaignard , Maxime Coquelin , Alexandre TORGUE - foss , Matt Roper , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" CC: Yannick FERTRE , Philippe CORNU , Raphael GALLAIS-POU - foss , Raphael GALLAIS-POU Subject: [PATCH 1/2] drm: add crtc background color property Thread-Topic: [PATCH 1/2] drm: add crtc background color property Thread-Index: AQHXcwzmIWr2Mk6FgEuDfOXYcahi7g== Date: Wed, 7 Jul 2021 08:48:47 +0000 Message-ID: <20210707084557.22443-2-raphael.gallais-pou@foss.st.com> References: <20210707084557.22443-1-raphael.gallais-pou@foss.st.com> In-Reply-To: <20210707084557.22443-1-raphael.gallais-pou@foss.st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.47] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-07_05:2021-07-06, 2021-07-07 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210707_014902_324805_639ACB78 X-CRM114-Status: GOOD ( 32.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some display controllers can be programmed to present non-black colors for pixels not covered by any plane (or pixels covered by the transparent regions of higher planes). Compositors that want a UI with a solid color background can potentially save memory bandwidth by setting the CRTC background property and using smaller planes to display the rest of the content. To avoid confusion between different ways of encoding RGB data, we define a standard 64-bit format that should be used for this property's value. Helper functions and macros are provided to generate and dissect values in this standard format with varying component precision values. Signed-off-by: Raphael Gallais-Pou Signed-off-by: Matt Roper --- drivers/gpu/drm/drm_atomic_state_helper.c | 1 + drivers/gpu/drm/drm_atomic_uapi.c | 4 +++ drivers/gpu/drm/drm_blend.c | 34 +++++++++++++++++++++-- drivers/gpu/drm/drm_mode_config.c | 6 ++++ include/drm/drm_blend.h | 1 + include/drm/drm_crtc.h | 12 ++++++++ include/drm/drm_mode_config.h | 5 ++++ include/uapi/drm/drm_mode.h | 28 +++++++++++++++++++ 8 files changed, 89 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index ddcf5c2c8e6a..1b95a4ecdb2b 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -72,6 +72,7 @@ __drm_atomic_helper_crtc_state_reset(struct drm_crtc_state *crtc_state, struct drm_crtc *crtc) { crtc_state->crtc = crtc; + crtc_state->bgcolor = drm_argb(16, 0xffff, 0, 0, 0); } EXPORT_SYMBOL(__drm_atomic_helper_crtc_state_reset); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 438e9585b225..fea68f8f17f8 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -483,6 +483,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, set_out_fence_for_crtc(state->state, crtc, fence_ptr); } else if (property == crtc->scaling_filter_property) { state->scaling_filter = val; + } else if (property == config->bgcolor_property) { + state->bgcolor = val; } else if (crtc->funcs->atomic_set_property) { return crtc->funcs->atomic_set_property(crtc, state, property, val); } else { @@ -520,6 +522,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = 0; else if (property == crtc->scaling_filter_property) *val = state->scaling_filter; + else if (property == config->bgcolor_property) + *val = state->bgcolor; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c index ec37cbfabb50..6692d6a6db22 100644 --- a/drivers/gpu/drm/drm_blend.c +++ b/drivers/gpu/drm/drm_blend.c @@ -186,8 +186,7 @@ * assumed to be 1.0 * * Note that all the property extensions described here apply either to the - * plane or the CRTC (e.g. for the background color, which currently is not - * exposed and assumed to be black). + * plane or the CRTC. * * SCALING_FILTER: * Indicates scaling filter to be used for plane scaler @@ -201,6 +200,21 @@ * * Drivers can set up this property for a plane by calling * drm_plane_create_scaling_filter_property + * + * BACKGROUND_COLOR: + * Defines the ARGB color of a full-screen layer that exists below all + * planes. This color will be used for pixels not covered by any plane + * and may also be blended with plane contents as allowed by a plane's + * alpha values. The background color defaults to black, and is assumed + * to be black for drivers that do not expose this property. Although + * background color isn't a plane, it is assumed that the color provided + * here undergoes the same pipe-level degamma/CSC/gamma transformations + * that planes undergo. Note that the color value provided here includes + * an alpha channel...non-opaque background color values are allowed, + * but are generally only honored in special cases (e.g., when a memory + * writeback connector is in use). + * + * This property is setup with drm_crtc_add_bgcolor_property(). */ /** @@ -616,3 +630,19 @@ int drm_plane_create_blend_mode_property(struct drm_plane *plane, return 0; } EXPORT_SYMBOL(drm_plane_create_blend_mode_property); + +/** + * drm_crtc_add_bgcolor_property - add background color property + * @crtc: drm crtc + * + * Adds the background color property to @crtc. The property defaults to + * solid black and will accept 64-bit ARGB values in the format generated by + * drm_argb(). + */ +void drm_crtc_add_bgcolor_property(struct drm_crtc *crtc) +{ + drm_object_attach_property(&crtc->base, + crtc->dev->mode_config.bgcolor_property, + drm_argb(16, 0xffff, 0, 0, 0)); +} +EXPORT_SYMBOL(drm_crtc_add_bgcolor_property); diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index 37b4b9f0e468..d62d6585399b 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -371,6 +371,12 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.modifiers_property = prop; + prop = drm_property_create_range(dev, 0, "BACKGROUND_COLOR", + 0, GENMASK_ULL(63, 0)); + if (!prop) + return -ENOMEM; + dev->mode_config.bgcolor_property = prop; + return 0; } diff --git a/include/drm/drm_blend.h b/include/drm/drm_blend.h index 88bdfec3bd88..9e2538dd7b9a 100644 --- a/include/drm/drm_blend.h +++ b/include/drm/drm_blend.h @@ -58,4 +58,5 @@ int drm_atomic_normalize_zpos(struct drm_device *dev, struct drm_atomic_state *state); int drm_plane_create_blend_mode_property(struct drm_plane *plane, unsigned int supported_modes); +void drm_crtc_add_bgcolor_property(struct drm_crtc *crtc); #endif diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 13eeba2a750a..12601eb63c45 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -288,6 +288,18 @@ struct drm_crtc_state { */ struct drm_property_blob *gamma_lut; + /** + * @bgcolor: + * + * RGB value representing the pipe's background color. The background + * color (aka "canvas color") of a pipe is the color that will be used + * for pixels not covered by a plane, or covered by transparent pixels + * of a plane. The value here should be built via drm_argb(); + * individual color components can be extracted with desired precision + * via the DRM_ARGB_*() macros. + */ + u64 bgcolor; + /** * @target_vblank: * diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 1ddf7783fdf7..76c491d10d8d 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -867,6 +867,11 @@ struct drm_mode_config { */ struct drm_property *hdcp_content_type_property; + /** + * @bgcolor_property: RGB background color for CRTC. + */ + struct drm_property *bgcolor_property; + /* dumb ioctl parameters */ uint32_t preferred_depth, prefer_shadow; diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 98bf130feda5..035f06c6750e 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1154,6 +1154,34 @@ struct drm_mode_rect { __s32 y2; }; +/* + * Put ARGB values into a standard 64-bit representation that can be used + * for ioctl parameters, inter-driver commmunication, etc. If the component + * values being provided contain less than 16 bits of precision, they'll + * be shifted into the most significant bits. + */ +static inline __u64 +drm_argb(__u8 bpc, __u16 alpha, __u16 red, __u16 green, __u16 blue) +{ + int msb_shift = 16 - bpc; + + return (__u64)alpha << msb_shift << 48 | + (__u64)red << msb_shift << 32 | + (__u64)green << msb_shift << 16 | + (__u64)blue << msb_shift; +} + +/* + * Extract the specified number of bits of a specific color component from a + * standard 64-bit ARGB value. + */ +#define DRM_ARGB_COMP(c, shift, numbits) \ + ((__u16)(((c) & 0xFFFFull << (shift)) >> ((shift) + 16 - (numbits)))) +#define DRM_ARGB_BLUE(c, numbits) DRM_ARGB_COMP(c, 0, numbits) +#define DRM_ARGB_GREEN(c, numbits) DRM_ARGB_COMP(c, 16, numbits) +#define DRM_ARGB_RED(c, numbits) DRM_ARGB_COMP(c, 32, numbits) +#define DRM_ARGB_ALPHA(c, numbits) DRM_ARGB_COMP(c, 48, numbits) + #if defined(__cplusplus) } #endif From patchwork Wed Jul 7 08:48:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Gallais-Pou X-Patchwork-Id: 12362067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C09AC07E95 for ; Wed, 7 Jul 2021 08:50:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5FB5F61CBE for ; Wed, 7 Jul 2021 08:50:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5FB5F61CBE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=foss.st.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=raaVdmm45o42ADmXIJ27xYuoE0S1smOuL6zfI1HOxtc=; b=rOvdP6u+wWTw9X c8vV96lVMla1QtYIOoeu//sV8ahNqG9Pyo16iWZP2X1PlNlG/rmiYwaWG8cveSv7cZTZTi/1V+02u wJEJ6+3hBqzLnRSpvpVY4PCBgZS/YUwsM2waND2uOZAuD7ATP8S+lhbmtHZOIiXiGOLIMktlPLUAU zCkSSAzK1p0evtsn9coHuS1SZnDAvPzlx/0709brt+KnF8cFwXjZUpOFu2/jqmkTv+g0AKwNinf7n oEwCJqnRH7yqb3r4TzE1Hnqgn+aGY/H7KgsUXTOL2DetWuMt3K3ddVgYidxtuN2V/Bo7mcF3RPirI OCJlRB1X96bI44KA9EFw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m13F8-00E5LB-Mr; Wed, 07 Jul 2021 08:49:18 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m13Ey-00E5J2-D9 for linux-arm-kernel@lists.infradead.org; Wed, 07 Jul 2021 08:49:10 +0000 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1678anIb000467; Wed, 7 Jul 2021 10:48:56 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=selector1; bh=+UHKiuimh8eGcdGlwiV/tjsefnaHThxouA+MIurBhCk=; b=xXLhM1iuO/fkOho6EetbmJpYk9bWVj+574460Ba99eAcXuZI2zDjrKzD6hrMeP9OAcII mys7N2c3np3okzuFPasf1LZUBXsJwc6jTqPTCH0b+ox+WNT0Vaf7wycAlbIDCRPCJjQ4 ytAXwIm5VXf3bFrEquoE9SRauDCx/ZpQH5sOLarVZ48BxXBINaBwwOkmLLJtixedjvd6 DMypjp0wUBu50BeOu5QVDSBtaUUNSEwRCejtOp6rkJQQCMtcbNjKjf4Y3Hks+SUdaBe2 aBgOTUQjxkKFCFbZVA+JtH8m4syotz95wWSr9WGk3iTV6EwJj7V9BIa8J9cUokGCi31s Rg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 39mxgxjw08-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Jul 2021 10:48:56 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id EAAC510002A; Wed, 7 Jul 2021 10:48:55 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D1B462171D3; Wed, 7 Jul 2021 10:48:55 +0200 (CEST) Received: from SFHDAG2NODE3.st.com (10.75.127.6) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 7 Jul 2021 10:48:55 +0200 Received: from SFHDAG2NODE3.st.com ([fe80::31b3:13bf:2dbe:f64c]) by SFHDAG2NODE3.st.com ([fe80::31b3:13bf:2dbe:f64c%20]) with mapi id 15.00.1497.015; Wed, 7 Jul 2021 10:48:55 +0200 From: Raphael GALLAIS-POU - foss To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Yannick FERTRE - foss , Philippe CORNU - foss , Benjamin Gaignard , Maxime Coquelin , Alexandre TORGUE - foss , Matt Roper , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" CC: Yannick FERTRE , Philippe CORNU , Raphael GALLAIS-POU - foss , Raphael GALLAIS-POU Subject: [PATCH 2/2] drm/stm: ltdc: add crtc background color property support Thread-Topic: [PATCH 2/2] drm/stm: ltdc: add crtc background color property support Thread-Index: AQHXcwzrULWoh8jFv0qA90zmnYXzxA== Date: Wed, 7 Jul 2021 08:48:55 +0000 Message-ID: <20210707084557.22443-3-raphael.gallais-pou@foss.st.com> References: <20210707084557.22443-1-raphael.gallais-pou@foss.st.com> In-Reply-To: <20210707084557.22443-1-raphael.gallais-pou@foss.st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.47] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-07_05:2021-07-06, 2021-07-07 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210707_014908_778366_023755D6 X-CRM114-Status: GOOD ( 27.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch comes from the need to display small resolution pictures with very few DDR usage. In practice, using a background color, produced by the drm CRTC, around this picture allows to fetch less data in memory than setting a full frame picture. And therefore the picture in DDR is smaller than the size of the screen. It uses the DRM framework background color property and modifies the color to any value between 0x000000 and 0xFFFFFF from userland with a RGB24 value (0x00RRGGBB). Using this feature is observable only if layers are not full screen or if layers use color formats with alpha and are "transparent" at least on some pixels. Depending on the hardware version, the background color can not be properly displayed with non-alpha color formats derived from native alpha color formats (such as XR24 or XR15) since the use of this pixel format generates a non transparent layer. As a workaround, the stage background color of the layer and the general background color need to be synced. Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/ltdc.c | 48 ++++++++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 1f9392fb58e1..0aca245288cc 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -196,6 +196,11 @@ #define NB_PF 8 /* Max nb of HW pixel format */ +#define DRM_ARGB_TO_LTDC_RGB24(bgcolor) \ + ((u32)(DRM_ARGB_RED(bgcolor, 8) << 16 \ + | DRM_ARGB_GREEN(bgcolor, 8) << 8 \ + | DRM_ARGB_BLUE(bgcolor, 8))) + enum ltdc_pix_fmt { PF_NONE, /* RGB formats */ @@ -364,6 +369,15 @@ static inline u32 get_pixelformat_without_alpha(u32 drm) } } +/* + * All non-alpha color formats derived from native alpha color formats are + * either characterized by a FourCC format code (such as XR24, RX24, BX24...) + */ +static inline u32 is_xrgb(u32 drm) +{ + return ((drm & 'X') == 'X' || (drm & ('X' << 8)) == ('X' << 8)); +} + static irqreturn_t ltdc_irq_thread(int irq, void *arg) { struct drm_device *ddev = arg; @@ -431,7 +445,8 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, pm_runtime_get_sync(ddev->dev); /* Sets the background color value */ - reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); + reg_write(ldev->regs, LTDC_BCCR, + DRM_ARGB_TO_LTDC_RGB24(crtc->state->bgcolor)); /* Enable IRQ */ reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); @@ -452,6 +467,9 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, drm_crtc_vblank_off(crtc); + /* Reset background color */ + reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); + /* disable IRQ */ reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); @@ -790,6 +808,7 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; u32 src_x, src_y, src_w, src_h; u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; + u32 bgcolor = DRM_ARGB_TO_LTDC_RGB24(newstate->crtc->state->bgcolor); enum ltdc_pix_fmt pf; if (!newstate->crtc || !fb) { @@ -853,10 +872,28 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane, if (!fb->format->has_alpha) val = BF1_CA | BF2_1CA; - /* Manage hw-specific capabilities */ - if (ldev->caps.non_alpha_only_l1 && - plane->type != DRM_PLANE_TYPE_PRIMARY) - val = BF1_PAXCA | BF2_1PAXCA; + /* + * Manage hw-specific capabilities + * + * Depending on the hardware version, the background color can not be + * properly displayed with non-alpha color formats derived from native + * alpha color formats (such as XR24 or XR15) since the use of this + * pixel format generates a non transparent layer. As a workaround, + * the stage background color of the layer and the general background + * color need to be synced. + * + * This is done by activating for all XRGB color format the default + * color as the background color and then setting blending factor + * accordingly. + */ + if (ldev->caps.non_alpha_only_l1) { + if (is_xrgb(fb->format->format)) { + val = BF1_CA | BF2_1CA; + reg_write(ldev->regs, LTDC_L1DCCR + lofs, bgcolor); + } else { + val = BF1_PAXCA | BF2_1PAXCA; + } + } reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, LXBFCR_BF2 | LXBFCR_BF1, val); @@ -1033,6 +1070,7 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); + drm_crtc_add_bgcolor_property(crtc); drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);