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Fri, 9 Jul 2021 07:54:00 +0000 From: Joakim Zhang To: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org, andrew@lunn.ch Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com Subject: [PATCH V1 1/5] dt-bindings: fec: add the missing clocks properties Date: Fri, 9 Jul 2021 15:53:51 +0800 Message-Id: <20210709075355.27218-2-qiangqing.zhang@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210709075355.27218-1-qiangqing.zhang@nxp.com> References: <20210709075355.27218-1-qiangqing.zhang@nxp.com> X-ClientProxiedBy: SG2PR06CA0147.apcprd06.prod.outlook.com (2603:1096:1:1f::25) To DB8PR04MB6795.eurprd04.prod.outlook.com (2603:10a6:10:fa::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SG2PR06CA0147.apcprd06.prod.outlook.com (2603:1096:1:1f::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4308.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: puS214lZmU/hgNspzKICIdybPTk0fIzejCPblfJRewV1/Q56/2+jC6dDpL+mgbap8pGT/eKzLNTpHkv3SG0wqNQCASoT1plpsgSPqBf6FMELHrp/kP54JymZH8F40X3Vng5BMRh/Pl4dqxNivNZkkb0L6JKg47KJeESMkq4KjdB0Whm3vu6TVk/mOnJn5OmUipDJkWq0W1geu48tQnECE1/P16Fks9j+0aCalVpckOGG3SPEDMY+LvhUt+xWLO8cgElLe+tAW6wUs1zZDnfgGH4UnSD1cW637hVv7A0A+Q/+g+JIcx9ontMYayL49m5sG9quqRz1Vkl+dw4NGqwdFDAL/AlRn62thg6DnH4EFAWpcHRPYKbuQtitk5effYfaMi1VAKoetWsnUgol4zQJyhK2scFid761KUSDuIg/vNo5RgyAovpXLFsdDOUI9YUgaL6CVg4KgG0qgHyDbK07y23gcBCTAH8imOtPj19nNJh5BM7TGfuSfcbYH3QKoadWOZhwPgB793aVerZqmpuEb8qe0xLGDGzFOFYd8BMaVF86AfubDsdcBYtLiQbeyALOQOtH2KT+XUE9zusgYgv3rCd3BPhPTA2QgCQyX6n8I9bkY3wAL/AaH27xrLJ3E2Thw4p7SwcbKXULqwcE9yB5gibDY+RXgKj27Rw9XMnBa8I00hczxZwTBuetL4TBcfd7JHSklpvKo3447uYK5UXcUxrzoZo8bRdHCESuDA0d2v+5sCnUOeQ9dhL2JVaUvLopv4JG/XZYVtKRfk8/A08KbwdOxu6ZbuNbnF1hBBj/CwZH/VlA58JI/7i0ZzvA0C2JQU46mue9zUTZYftXzv8JGEgJS8O9Lwxpn0Kn1lEcr6pY0w7d+hhoBd5T1vo5C0KTUerEwsCOr0KEcxY/5ZkoSACLMWGYC9tA/UEWEBVIqyA7bO4DH9Sb7O31xDG31cGo9eUHTU3TnaLgvHyz7UcyyPm1pDDtlo7oGkhTTtE70HxMiRT0t4BqQsOVLQ3T/fcMvLunBevjl8znOGBRtmK5enJQIv71g+XLN+egZ82XzRS3V/EVbNYFLlwcVAmptrkhDIqewNBtqQGMgYvOqnKh3huIMsdJn+JOCg7Rss0ZAeqoubUokp+65VPyzymjyfep7QA2WWoxziE37Jb3MSIh+eNiBi4omOLLphQL935ly9W4czHRppDFpCZS8hB0G975Lm0UmSAB9qNDxkCwmiCYUfVTybRSXObp2hY7DnlxJs3aFe6Jp7j8DDGTSluiIZng8hqtlj4eYHqMX61NdNCpl2OrlLD7IARvwK8S88xvho1sswZHl0QD4g1tdJqUA0YL X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b7e27411-49ef-4aa5-8a9e-08d942aeb6a8 X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB6795.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2021 07:54:00.7619 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qFQxxa5zWtkTt7FWxncaQ0/1KeDQXI1fpseiVrguwyxpHE29MRLDBUfv8vrMeikWsF6uVclE3WYZFPlz2EW3Pw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0401MB2502 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Fugang Duan Both driver and dts have already used these clocks properties, so add the missing clocks info. Signed-off-by: Fugang Duan Signed-off-by: Joakim Zhang --- Documentation/devicetree/bindings/net/fsl-fec.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 9b543789cd52..6754be1b91c4 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -39,6 +39,17 @@ Optional properties: tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts. For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse per second interrupt associated with 1588 precision time protocol(PTP). +- clocks: Phandles to input clocks. +- clock-name: Should be the names of the clocks + - "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing. + - "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock. + - "ptp"(option), for IEEE1588 timer clock that requires the clock. + - "enet_clk_ref"(option), for MAC transmit/receiver reference clock like + RGMII TXC clock or RMII reference clock. It depends on board design, + the clock is required if RGMII TXC and RMII reference clock source from + SOC internal PLL. + - "enet_out"(option), output clock for external device, like supply clock + for PHY. The clock is required if PHY clock source from SOC. Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes From patchwork Fri Jul 9 07:53:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Zhang X-Patchwork-Id: 12366899 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2745EC07E9C for ; Fri, 9 Jul 2021 07:54:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E23A613B5 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +2Afkm2uGeEC15l9yw68CV2uSveQ1gWz8Ft4zx7OxIyA7v6FdM2k/ntvPtP4ANi59dgW7ZjyoEY2PwhynrZCieUNNt1A6rS6G7PbldDNpRV5PQ2GFUVpI79u5WTboNguArtnFwn4GXF8fZ/jv5Ie12lvkqf68aHCCjYgSEA97T8lWSNE/AItYCSpfKHz/D0EQjEq7+xn1TXs9p4IBiItusa0O63938W4iZBvLzNkFHfJsioi3GU5lZkhL/Eu8IsOf7bIEHR6l3EgBmkxtCqnnAoJC8NfVxRUBOf41yczwP3GeJzA93aUGrkpjlvV8Lsj9sLK8JRvp1XZdhzYe0Th9dEQt9VrDe+yjvvNdQlRIWumAunm9BJ7wAarM1oaEdkF0rbDzcDEZTTSvG1hshbhK3jxLlTwvCQ/wQ9/mLnw4eGrhW1NY94GsDuoQ9x/EvWzIWrj+C7399/3KEEz4y35TSVdfcW/nicoZ/Byug/AmRSy2yHNaNb9v+wYPe849gY/tjXNy04ZBDp4g/xwT2VCZ7Lcblne0TTSojZyksl5kk7wFMxsGNVDsZK43MVUXdVZW5Non+8E6RS5LtjGdP5tmQwNMj1JDeVgNpB45CKtE/jgiTrfKG30XZ9/jg7XHVqKaOTvhdw/7t7O05hzJpcHvNST5EytW7ZKibWNtr4Ng5Pf155fcKiX960xMkOYidQdI/CUvkuzHpVl288ySxdUr4XHwkKpY2C6SlEDGxY6kfNKU0sSGN5CG1iqtZwS07+GqY9HHG84EUb2VM9TSTNtveu/ZkGRqtfPQkYBar8a03FpymTiCorUQd3ViVFgmL6PARS/TkR3MQEsDfmadoea4OKPnrlWGV034p17alkFFOV3FYGgkSUzeNtI4UDrjYMGLIHoGYCWljjs2ExIw6YXDFkHFjOAK760sdKPtFz12dVlXy7eU3Y3OughnuTTZf53xQNZISWgTWDgie//w/ITKH+1MW1q4Y7sGfakNoGXNLCM2X+OihSAEXDmJICdZZC3CHPpdKTtXBHGpb3kncUwRA2yxo3qOMypShHG+faRUK1TF8keSJHWuFJYXaSnpkUsABjKSPiEW0m7EaYpkjxFHCAtMMLgy2PdCDBbVKF72FfIg6u/qW9LMj3nwjHvrZ3RGIeSy4oBSETSxsQAzqdYkxYZcayQ2hqC/Toq0ft4G9Q/TX8Fea6dRWnWfce3OxWMwpAi7fPXOusXO4DLGDoKRojqUEkL5C6Ba4ZILWz9VWmD0P9+XYcVsMs557TyfmJ7+J/F8Pgq9AwdH1o9ptTXxYVahR8mzoRN4U/QJQUcmQ2ntupakbv421vnWxyNLt3L X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: bf827d59-e31d-4d8c-0c32-08d942aeb86c X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB6795.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2021 07:54:03.8543 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wiYBy86Tr67QPgPAJ1qFG/jmndrRpki5uPqnA2T2FtRz8Wl/BxKnhgVsaaEZq9GQofqg/ES2ZTfKRmUJTDWxkw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0401MB2502 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Fugang Duan Add property for RGMII delayed clock. Signed-off-by: Fugang Duan Signed-off-by: Joakim Zhang --- Documentation/devicetree/bindings/net/fsl-fec.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 6754be1b91c4..f93b9552cfc5 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -50,6 +50,10 @@ Optional properties: SOC internal PLL. - "enet_out"(option), output clock for external device, like supply clock for PHY. The clock is required if PHY clock source from SOC. + - "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz. + The clock is required if SOC RGMII enable clock delay. +- fsl,rgmii_txc_dly: add RGMII TXC delayed clock from MAC. +- fsl,rgmii_rxc_dly: add RGMII RXC delayed clock from MAC. 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: e3mOqyKmMpqMt5kS1vsaNYfqpk7bt3cELpDLNKbD+9/HuZ3FsgyjaTPa//rMlRZ1UeDqPDlkQaK9INaFnzkBkLE/e1P1VbnczLWme7uwVGH2O7O2t590slGAjr15CbzNcWZRxvQcKYbdX77z/zFeLrfRcJbaVBS9S/DvZyb6bAZVQIx31K4495YMRGwXyWo2WBzTnkJAru9ZatFnOlK2lUcyYPmQqTvuBec36YwlcVl43DjkiPeUJYKEkT1eeeUB7Zoza05BjP7wGoZDg1QBKS9CTjJ9FeiOQLu4L0dutcVqznPsjGcbbE6+LEFyl88nNyW9VeNq4a8IFXMIoH46mUAqXMe53JUeUvJ3Fva38Qy1JMQ/NkuRWd6X0rJE7l4g3DH/gt8Xtkao4PCkiVKWYCJoUx1ZV8zci90E8l3mJn9+yneEvOy/ocQ+k7PqETv2EHYhdgZeyvm9Lf61U2AdS3dPMfRoj8VR8QaU6JosiOLc0rkeqDqIHVZ/ebjqOZl0ijC0lrZ+bjA7WDpbcTn1xpPEamFyAe9BCVE6mkr8PU+uUx6hVtBzBoEGNNCxZiPk5fQafEoNiwdIADI9/e9ek9l2AC/Qwalib+RiBSK84mvkWoUyPfqCDtzghUcR36iD7/bIqOB1Xy4ywtO6ra2njaTDl8r0UogZkmtpL/Olao1jqDK5CnKdG15GtwqJcxiApRvUAb1ylWJYQt8dSoXpokQjHpgs74H7V0CsrJ+24hDoykZHfuVBYTAC/2uivDrzYBFm4kb1B4grwvpF8PeFVKZXCAInDPCzHJ5KFQDYsl+RkYNlKiEgawO9l759Kl7OrgbTMx8PgKRatKZ6fYjPPRI9kPi6IqtzbWOPfcgzEk/ek9mRvXlMiuItkjL9vOEtj04BolhyA6YGK3Gxuo2rrfgvtWs1N+1bWBQF5YrmkhaX/QfIL6bUhLLjnIJN4GJDc6MbwgesnNoP7EHl2fqSI+MIdNV1WR+GH7W5+zb4hAcvikGEa4mmcSraahf7LJxvnN9d7/VI2sYMVmhUSaRt/s7xRF2brgfOIzTZLNmvIxs1tfieEOsxf6uROZdlBBxfVTb6qCvzE0xkqu37gfJ7KnmAvAkdQ6X2e/cFBfEcNJXjwF6ebgCnweVlo61inE38Wt3xmD9C88lL6wOhceqiXDs9lD+yLhxyp727BSsbvXSTciNljd/YkAKochnWXko5HqX64DqVEKp/nmfy+8iCrgyv5OEXcgJLNz2a1TOeoolNUguDIDfyt3w3twRgGfb/61elKUH3F4weQsSf8QmRNdtpOO2R179rLzbTrLPFid+YUPsQ20aQ8/QGw5VNFm+6 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e4fbeeee-1512-49a6-ac16-08d942aeba44 X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB6795.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2021 07:54:06.9229 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HOiit8BeCPF/WLx2lxeR9lcDQvNHVYBzSfGm6vao5GsEW8FHUphK2aRsbfZkQZA5ASN9Ga+E1Uc5iOXiyqr2og== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7628 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Fugang Duan The ENET of imx8mq and imx8qm are basically the same as imx6sx, but they have new features support based on imx6sx, like: - imx8mq: supports IEEE 802.3az EEE standard. - imx8qm: supports RGMII mode delayed clock. Signed-off-by: Fugang Duan Signed-off-by: Joakim Zhang --- drivers/net/ethernet/freescale/fec.h | 13 ++++++++++ drivers/net/ethernet/freescale/fec_main.c | 30 +++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h index 2e002e4b4b4a..c1f93aa79d63 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -472,6 +472,19 @@ struct bufdesc_ex { */ #define FEC_QUIRK_HAS_MULTI_QUEUES (1 << 19) +/* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE + * standard. For the transmission, MAC supply two user registers to set + * Sleep (TS) and Wake (TW) time. + */ +#define FEC_QUIRK_HAS_EEE (1 << 20) + +/* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC + * as an alternative option to make sure it works well with various PHYs. + * For the implementation of delayed clock, ENET takes synchronized 250MHz + * clocks to generate 2ns delay. + */ +#define FEC_QUIRK_DELAYED_CLKS_SUPPORT (1 << 21) + struct bufdesc_prop { int qid; /* Address of Rx and Tx buffers */ diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 8aea707a65a7..dd0b8715e84e 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -135,6 +135,26 @@ static const struct fec_devinfo fec_imx6ul_info = { FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII, }; +static const struct fec_devinfo fec_imx8mq_info = { + .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | + FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | + FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | + FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | + FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | + FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | + FEC_QUIRK_HAS_EEE, +}; + +static const struct fec_devinfo fec_imx8qm_info = { + .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | + FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | + FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | + FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | + FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | + FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES | + FEC_QUIRK_DELAYED_CLKS_SUPPORT, +}; + static struct platform_device_id fec_devtype[] = { { /* keep it for coldfire */ @@ -161,6 +181,12 @@ static struct platform_device_id fec_devtype[] = { }, { .name = "imx6ul-fec", .driver_data = (kernel_ulong_t)&fec_imx6ul_info, + }, { + .name = "imx8mq-fec", + .driver_data = (kernel_ulong_t)&fec_imx8mq_info, + }, { + .name = "imx8qm-fec", + .driver_data = (kernel_ulong_t)&fec_imx8qm_info, }, { /* sentinel */ } @@ -175,6 +201,8 @@ enum imx_fec_type { MVF600_FEC, IMX6SX_FEC, IMX6UL_FEC, + IMX8MQ_FEC, + IMX8QM_FEC, }; static const struct of_device_id fec_dt_ids[] = { @@ -185,6 +213,8 @@ static const struct of_device_id fec_dt_ids[] = { { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, + { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], }, + { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], }, { /* sentinel */ } }; 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Fri, 9 Jul 2021 07:54:09 +0000 From: Joakim Zhang To: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org, andrew@lunn.ch Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com Subject: [PATCH V1 4/5] net: fec: add eee mode tx lpi support Date: Fri, 9 Jul 2021 15:53:54 +0800 Message-Id: <20210709075355.27218-5-qiangqing.zhang@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210709075355.27218-1-qiangqing.zhang@nxp.com> References: <20210709075355.27218-1-qiangqing.zhang@nxp.com> X-ClientProxiedBy: SG2PR06CA0147.apcprd06.prod.outlook.com (2603:1096:1:1f::25) To DB8PR04MB6795.eurprd04.prod.outlook.com (2603:10a6:10:fa::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SG2PR06CA0147.apcprd06.prod.outlook.com (2603:1096:1:1f::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4308.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6/aXIDyws3QdOzV0PCK5SchQY/Six/0R5YLrAl2JijUx7FVwh3evq0rGuyz4NVJIp2wnGh4sKp6LAxNYtu7+R4tPGoIq1b0FBpVXuN6UyLz2ZMechf6xgXKDaGvuda44oNRqkx++ThxLVstTMQSP7bCzhBtoaAspYXbhc8u0/IILX0NCzoxC6JmUh/lW/tbctK29DIehKhhehv8Vhycld63m1jnc7dnrtKA4kgvQAwWYGJKhBLQHBSxPbAEBallYYy1uewIC52xnpjzHJRsbX77FZVRthr/jCrTBauR0e1yC3p8ZzIaJ3+FX/TUWc4R48NhypCSvUkr1e2XTyl4vTJ+O2Jm+pmVJEBJ0U0NUxA18srLjKw6b5ZLHngl6Q7ukYUKcAL9qIFjTIsN28eozpAKLT5S9HjMUJmQv5mDjb9VAh4pGONdJ1gThgfBMTckcjsZGeh62KwEv+LSCcq/+SJymoqgvtZ7huGKptIIzb3e0afCSD4lwMGlCzvgHn1BaHrE4ZmlTWMoGf9hoQ+Lsp9dHPOjPq8zzE9TWQ3S7JQCEM5xrPv9WioVpQZEryWJcYL73MDoIwWmYJ/0qDprPpbMF9NFANqIuY/nrbiHW6mlTU3hdgSeppAjO5z7hYJtBRN40WOpzJGxya18BLINov4PVrEK2SJyYGB5rtu3+r+duFJO1ByZLctts3npLy7cisXYYFUvRCYQIczMjA9bK0Fv2SjIro5r8OHqdIplfahMtzaiPjDMh1i0lxIQX1qU/+K6Q3BvdnpzniUx87GQxlOMuMAG6zz+RTjuG61dXFOeQOxe228Kikp8qYU0aGtVKutu4XQO+LvE1UsJRX2j6iao1tzRM8vSCB5HFpbCp3/tVEspGlLZHpfNe6h/xdcWX5uttmghOE3STFhTcWqM6gS5Ev7oUyvNe0gRM7laM5yvnubf1i6+Pt9NjXl0RZtqHffaF1qikZ2GPlaTaAaYrtxqwvGwjtHDD3hPTV8xo6eZMWWJ5nUKEL3nV9U55uZWeLYcj0G42KzHzW8v97eQuDj4DCq5RPxxIFQf2C+ljbYRN0DVYXDb00mWTGpB6NCG271lq8fP3udT/rtJAoWOHlQ+VTd0OODuVIwaj8iVUHZS+uPLZ28H6hijp6B2tEb9zHHrXLiskySnO7S+C/ukZOLrD3HoZIGR6NpVUQE2NMVsYLXzRb4TbYnRkzFiQ70sPtk1fDCx/Ss7XRb+9Omof74M2ahXPW5kCAtwfzbhoS1Fb+02v+13ZfspI94yaYiVTAlTuqiHBy/K22wjmkAWuFoXxHGfZGynKmRjABC217bNYR69lPHwRj1QAtpTpXcRR X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d5be34a8-4162-4239-2c71-08d942aebc1b X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB6795.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2021 07:54:09.9078 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Gc6b4FLT5veYWsqjyU+qYV4ewuuX+R95ctv9X6MuA+adYJGydXuX0KovECnvz0sVSCNmNxtJd3+nonzXbCQgag== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6793 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Fugang Duan The i.MX8MQ ENET version support IEEE802.3az eee mode, add eee mode tx lpi enable to support ethtool interface. usage: 1. set sleep and wake timer to 5ms: ethtool --set-eee eth0 eee on tx-lpi on tx-timer 5000 2. check the eee mode: ~# ethtool --show-eee eth0 EEE Settings for eth0: EEE status: enabled - active Tx LPI: 5000 (us) Supported EEE link modes: 100baseT/Full 1000baseT/Full Advertised EEE link modes: 100baseT/Full 1000baseT/Full Link partner advertised EEE link modes: 100baseT/Full Note: For realtime case and IEEE1588 ptp case, it should disable EEE mode. Signed-off-by: Fugang Duan Signed-off-by: Joakim Zhang --- drivers/net/ethernet/freescale/fec.h | 6 ++ drivers/net/ethernet/freescale/fec_main.c | 89 +++++++++++++++++++++++ 2 files changed, 95 insertions(+) diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h index c1f93aa79d63..0a741bc440e4 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -77,6 +77,8 @@ #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */ #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */ #define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */ +#define FEC_LPI_SLEEP 0x1f4 /* Set IEEE802.3az LPI Sleep Ts time */ +#define FEC_LPI_WAKE 0x1f8 /* Set IEEE802.3az LPI Wake Tw time */ #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ @@ -602,6 +604,10 @@ struct fec_enet_private { unsigned int tx_time_itr; unsigned int itr_clk_rate; + /* tx lpi eee mode */ + struct ethtool_eee eee; + unsigned int clk_ref_rate; + u32 rx_copybreak; /* ptp clock period in ns*/ diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index dd0b8715e84e..24082b3f2118 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -2722,6 +2722,92 @@ static int fec_enet_set_tunable(struct net_device *netdev, return ret; } +/* LPI Sleep Ts count base on tx clk (clk_ref). + * The lpi sleep cnt value = X us / (cycle_ns). + */ +static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us) +{ + struct fec_enet_private *fep = netdev_priv(ndev); + + return us * (fep->clk_ref_rate / 1000) / 1000; +} + +static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable) +{ + struct fec_enet_private *fep = netdev_priv(ndev); + struct ethtool_eee *p = &fep->eee; + unsigned int sleep_cycle, wake_cycle; + int ret = 0; + + if (enable) { + ret = phy_init_eee(ndev->phydev, 0); + if (ret) + return ret; + + sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); + wake_cycle = sleep_cycle; + } else { + sleep_cycle = 0; + wake_cycle = 0; + } + + p->tx_lpi_enabled = enable; + p->eee_enabled = enable; + p->eee_active = enable; + + writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); + writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); + + return 0; +} + +static int +fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata) +{ + struct fec_enet_private *fep = netdev_priv(ndev); + struct ethtool_eee *p = &fep->eee; + + if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) + return -EOPNOTSUPP; + + if (!netif_running(ndev)) + return -ENETDOWN; + + edata->eee_enabled = p->eee_enabled; + edata->eee_active = p->eee_active; + edata->tx_lpi_timer = p->tx_lpi_timer; + edata->tx_lpi_enabled = p->tx_lpi_enabled; + + return phy_ethtool_get_eee(ndev->phydev, edata); +} + +static int +fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata) +{ + struct fec_enet_private *fep = netdev_priv(ndev); + struct ethtool_eee *p = &fep->eee; + int ret = 0; + + if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) + return -EOPNOTSUPP; + + if (!netif_running(ndev)) + return -ENETDOWN; + + p->tx_lpi_timer = edata->tx_lpi_timer; + + if (!edata->eee_enabled || !edata->tx_lpi_enabled || + !edata->tx_lpi_timer) + ret = fec_enet_eee_mode_set(ndev, false); + else + ret = fec_enet_eee_mode_set(ndev, true); + + if (ret) + return ret; + + return phy_ethtool_set_eee(ndev->phydev, edata); +} + static void fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) { @@ -2782,6 +2868,8 @@ static const struct ethtool_ops fec_enet_ethtool_ops = { .set_tunable = fec_enet_set_tunable, .get_wol = fec_enet_get_wol, .set_wol = fec_enet_set_wol, + .get_eee = fec_enet_get_eee, + .set_eee = fec_enet_set_eee, .get_link_ksettings = phy_ethtool_get_link_ksettings, .set_link_ksettings = phy_ethtool_set_link_ksettings, .self_test = net_selftest, @@ -3722,6 +3810,7 @@ fec_probe(struct platform_device *pdev) fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); if (IS_ERR(fep->clk_ref)) fep->clk_ref = NULL; + fep->clk_ref_rate = clk_get_rate(fep->clk_ref); fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); From patchwork Fri Jul 9 07:53:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Zhang X-Patchwork-Id: 12366905 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19682C11F66 for ; Fri, 9 Jul 2021 07:54:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E7F5E613BA for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0EOcp+CpwdGzRLdky1qu94h+REPgZpMZ/JFeI/fkxkcTUII2zO9IJTqc/31PK+6O5rORD2mwZt0jsoV3Hav35yO8JJbcWWU71s/CMHI2PHer/poo50lRPHqYnOKmEagsWI5wCj0+F8ahdGgYl0kpelT2cxSsYpz5s+J4ii9ib6nqt0RsmVCzZswoVRRRKTL7gT8Nxe+w6MscP8RMHJy4KYezLrrbO7ygiiEu6uAPJvotL4IteNOLB+f75OgLJmaWCgh9lWCExRI5LFlMKXgx74dtxECSUemuwfWjOB0R5xTnVsTzsmGrAdR4Zf+FnPrcyL/9+fg720olDd4f3XaaNQd89My2oVCC6w9zSPR/EKSoyX2QTIWQY/51eQaQLD1COb6mrjzaM7pHL0FwygqX3HiMzwoXneuT7itjd+8KfCflF8PIqQYgFFEi8/CuQkqAFrR1LdDb5xcp3tG181tf4W+pBiQvZKgLrBlf0sAlq6LmFOGT3zg1RyPKfDSH7k41O+PhBo2YoTotCPOphOzoCEkJ2lFDV7uO7vSbprRfXbynPjSMgKd6C7cw87gqKV5p0Yo/6Eu+4/TRWrcr/04rgyQg0hpxhsBIo+Aq9IPasmF1HfkRV4QB2xQvhjZ8EqEkkhfrd4E25uA/jY+mBA3CMEutQl8IOl9KyX4h+OvjGScCgWlmwBxqoWGzzPuer20oowOyPtQw+EMiNzIN1/4d4KJw1DYPqNjFXXPhp8UD5rptX/v7QoG4NKVF6kWmicrZ1kPbjU3sCY75WNp7cL3G23znRaFYJEgUD6xsKRzD45CjmwBzitlS+LcCnX2NeZEsP5d9ERFKfxUQBUE/w0ndspwKRKqBkBgNSwy3uv2pFYEEjP298LsyvcjpIrpBfhGkLZZUfa7czCZi+6oCkQU2j8p8tbPw/TPzABBFvDCT5tZdLZsN/sv8iRSsGMlYe81V0BxkUSKzaDFEwONL9fnk0I6Tp4jpn/Ir41PKk2Fq8XDKgXRptEFrRmSAoYXUGrnZ8UyfQYWCr2A7ARtSxlTllEQFHS8K6pQCIuyZ7Wuw0EFip5k0wdaa/uH5vuM0OabPa8H7RJvVuLoVi2yU78q9ODgEVFJ4s/LL3YNaRpeKBeOqvKYNHMCDp8KeHK+oJF1PIdx0ogmq29utK+tMJJgf5cVR1lBd9KiPLq1TiuUf0aoFyRdTl0ghRS8rjJIfze6LDzaS7nO+PMrByW+QK+2JY26jgV3DSC/Lo4Rjdk0MNTlXHWFsSQYpAjRHHFV3LfsV+cX8TWdILNt1+Iy7xAamnRf560hIkLkbOOsIlBBwMqtVIIIRgb5Z47E5xv6y8tBh X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 966ed448-f296-47e3-c2ff-08d942aebde4 X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB6795.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2021 07:54:12.9106 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 952fvRCE0P0cviSpP0L3SGmmRIeBrTL14/7rJOedWsR47uJWuYgRKw0M4h43XwRwVozT8NYCd9D8CDmVkSnDNQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6793 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Fugang Duan i.MX8QM ENET IP version support timing specification that MAC integrate clock delay in RGMII mode, the delayed TXC/RXC as an alternative option to work well with various PHYs. Signed-off-by: Fugang Duan Signed-off-by: Joakim Zhang --- drivers/net/ethernet/freescale/fec.h | 6 ++++++ drivers/net/ethernet/freescale/fec_main.c | 26 +++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h index 0a741bc440e4..ae3259164395 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -381,6 +381,9 @@ struct bufdesc_ex { #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF) #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) +#define FEC_ENET_TXC_DLY ((uint)0x00010000) +#define FEC_ENET_RXC_DLY ((uint)0x00020000) + /* ENET interrupt coalescing macro define */ #define FEC_ITR_CLK_SEL (0x1 << 30) #define FEC_ITR_EN (0x1 << 31) @@ -543,6 +546,7 @@ struct fec_enet_private { struct clk *clk_ref; struct clk *clk_enet_out; struct clk *clk_ptp; + struct clk *clk_2x_txclk; bool ptp_clk_on; struct mutex ptp_clk_mutex; @@ -565,6 +569,8 @@ struct fec_enet_private { uint phy_speed; phy_interface_t phy_interface; struct device_node *phy_node; + bool rgmii_txc_dly; + bool rgmii_rxc_dly; int link; int full_duplex; int speed; diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 24082b3f2118..18ab60322688 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -1137,6 +1137,13 @@ fec_restart(struct net_device *ndev) if (fep->bufdesc_ex) ecntl |= (1 << 4); + if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && + fep->rgmii_txc_dly) + ecntl |= FEC_ENET_TXC_DLY; + if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && + fep->rgmii_rxc_dly) + ecntl |= FEC_ENET_RXC_DLY; + #ifndef CONFIG_M5272 /* Enable the MIB statistic event counters */ writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); @@ -2000,6 +2007,10 @@ static int fec_enet_clk_enable(struct net_device *ndev, bool enable) if (ret) goto failed_clk_ref; + ret = clk_prepare_enable(fep->clk_2x_txclk); + if (ret) + goto failed_clk_2x_txclk; + fec_enet_phy_reset_after_clk_enable(ndev); } else { clk_disable_unprepare(fep->clk_enet_out); @@ -2010,10 +2021,14 @@ static int fec_enet_clk_enable(struct net_device *ndev, bool enable) mutex_unlock(&fep->ptp_clk_mutex); } clk_disable_unprepare(fep->clk_ref); + clk_disable_unprepare(fep->clk_2x_txclk); } return 0; +failed_clk_2x_txclk: + if (fep->clk_ref) + clk_disable_unprepare(fep->clk_ref); failed_clk_ref: if (fep->clk_ptp) { mutex_lock(&fep->ptp_clk_mutex); @@ -3761,6 +3776,12 @@ fec_probe(struct platform_device *pdev) if (ret) goto failed_stop_mode; + if (of_get_property(np, "fsl,rgmii_txc_dly", NULL)) + fep->rgmii_txc_dly = true; + + if (of_get_property(np, "fsl,rgmii_rxc_dly", NULL)) + fep->rgmii_rxc_dly = true; + phy_node = of_parse_phandle(np, "phy-handle", 0); if (!phy_node && of_phy_is_fixed_link(np)) { ret = of_phy_register_fixed_link(np); @@ -3812,6 +3833,11 @@ fec_probe(struct platform_device *pdev) fep->clk_ref = NULL; fep->clk_ref_rate = clk_get_rate(fep->clk_ref); + /* clk_2x_txclk is optional, depends on board */ + fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); + if (IS_ERR(fep->clk_2x_txclk)) + fep->clk_2x_txclk = NULL; + fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); if (IS_ERR(fep->clk_ptp)) {