From patchwork Tue Jul 13 14:46:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 12374237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C992C07E95 for ; Tue, 13 Jul 2021 14:46:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E75CB6128C for ; Tue, 13 Jul 2021 14:46:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236882AbhGMOtW (ORCPT ); Tue, 13 Jul 2021 10:49:22 -0400 Received: from mail.kernel.org ([198.145.29.99]:58600 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236883AbhGMOtW (ORCPT ); Tue, 13 Jul 2021 10:49:22 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 695D961289; Tue, 13 Jul 2021 14:46:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626187592; bh=/oei90Ltg62kh8uWBdh1e3F5iY/fUBosgEXNrPGV8eM=; h=From:To:Cc:Subject:Date:From; b=DLjkEgMVuzJNNkwwONJ4zssNmeFtCQzlZR1aDCtwiayFNLOVQlv4G59X8y6w7nR9K 64QurgCEOprICLkPTQHqiMeaOQynMPpK7I6bDWZjDQLh4kCFcUuEM6gSR2489JRUki +HcL/Z19Nf2mFpRNWsULJnSBy/MPzIFh6rvgkh5uILOkEGyr375ZKJdA233cFXs4ku WOzi1XhMeWbBZRohTuMwiNm5cMDLDNzP/dXLWp04XdyHKhRTGtP58QSuUpzQenSyGO cfsmy+E11ZwbZ0B+EcadWFRVWVBGEnLy7EMu7A4JIWxPfhIb/b5n761VbWjBTRMFAK //LTIAHa706iw== From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, stable@vger.kernel.org, Kris Chaplin Subject: [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Date: Tue, 13 Jul 2021 09:46:19 -0500 Message-Id: <20210713144621.605140-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The psi_ref_clk comes from the C2 node of the main_pll and periph_pll, not the C3. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-agilex.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 1cb21ea79c64..9dffe9ba0e74 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -107,10 +107,10 @@ static const struct clk_parent_data gpio_db_free_mux[] = { }; static const struct clk_parent_data psi_ref_free_mux[] = { - { .fw_name = "main_pll_c3", - .name = "main_pll_c3", }, - { .fw_name = "peri_pll_c3", - .name = "peri_pll_c3", }, + { .fw_name = "main_pll_c2", + .name = "main_pll_c2", }, + { .fw_name = "peri_pll_c2", + .name = "peri_pll_c2", }, { .fw_name = "osc1", .name = "osc1", }, { .fw_name = "cb-intosc-hs-div2-clk", From patchwork Tue Jul 13 14:46:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 12374241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C29F7C07E96 for ; Tue, 13 Jul 2021 14:46:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A600960E0B for ; Tue, 13 Jul 2021 14:46:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236895AbhGMOtX (ORCPT ); Tue, 13 Jul 2021 10:49:23 -0400 Received: from mail.kernel.org ([198.145.29.99]:58618 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236883AbhGMOtW (ORCPT ); Tue, 13 Jul 2021 10:49:22 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 464CB6128E; Tue, 13 Jul 2021 14:46:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626187592; bh=aa1+k78QvBo+kDqvKs85sZ5WgLyQUoGB37e2UYiiUJc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ve77FGGqpAuHYBYkAY2cL2EaZqmLMoEWaMUYx+dxwjH2mE0Gf1tPe7BdLjlpDAXmG 1PnjplooqRs7/wQos/89QfdLk9N4zYpTDS9cFBkY0vBxCyQ6dh9vrGvBokTZiVG9Jn iAhxK8Fe3n6QmBrfJaZidk1s4Bbjg8zolZdI/l+PZlh1PqrhKLEeILyZhg+RqyFkwZ WIKjd2Eq1G3qDMPc/+Ua8WKeRB9/MIZ6iiXQu32nEKA0Jz7AtgCnnh1A+CQCJ5sis+ 9toXmjKVRmfRm/Qz7JxdBcDFZS3xPbVFzCsTsRorYv8qazbaITl28/FykxoGnqxA5o E4w87AQL1WhwA== From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, stable@vger.kernel.org, Kris Chaplin Subject: [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation Date: Tue, 13 Jul 2021 09:46:20 -0500 Message-Id: <20210713144621.605140-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713144621.605140-1-dinguyen@kernel.org> References: <20210713144621.605140-1-dinguyen@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Correct the s2f_user0_mux clock representation. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-agilex.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 9dffe9ba0e74..7baaa16dea7b 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -195,6 +195,13 @@ static const struct clk_parent_data sdmmc_mux[] = { .name = "boot_clk", }, }; +static const struct clk_parent_data s2f_user0_mux[] = { + { .fw_name = "s2f_user0_free_clk", + .name = "s2f_user0_free_clk", }, + { .fw_name = "boot_clk", + .name = "boot_clk", }, +}; + static const struct clk_parent_data s2f_user1_mux[] = { { .fw_name = "s2f_user1_free_clk", .name = "s2f_user1_free_clk", }, @@ -319,6 +326,8 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { 4, 0x98, 0, 16, 0x88, 3, 0}, { AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C, 5, 0, 0, 0, 0x88, 4, 4}, + { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24, + 6, 0, 0, 0, 0x30, 2, 0}, { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0}, { AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C, From patchwork Tue Jul 13 14:46:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 12374239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70F00C11F69 for ; Tue, 13 Jul 2021 14:46:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5FA3D61358 for ; Tue, 13 Jul 2021 14:46:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236909AbhGMOtX (ORCPT ); Tue, 13 Jul 2021 10:49:23 -0400 Received: from mail.kernel.org ([198.145.29.99]:58646 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236904AbhGMOtX (ORCPT ); Tue, 13 Jul 2021 10:49:23 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1E98461361; Tue, 13 Jul 2021 14:46:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626187593; bh=9gvfN36Dprd4TP8wUitT/YKG0D2SzJ4HMNTTVd9tPQY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l8BqSQE4rptH1MvFBDjFr07v3Ox4Bh9mvT0gpVA7UybbPUwa7RHRZ75+6FoXs8JNa uhYVLNhxD2jWu9bw9ko6olu8OGp3uSgshi3gTOAr5TN2sVBsG+oexuX2Wv0bXa7njv OBw3uNAIByt/ukuZ+F6+fjvNUfwRJZwVptYlf1UX+T6UIm8px7G7hOTMb2IIchRgkf JYTFJciw1zYQFs2aieFkTZMdedfkG2lfLEY0NWM7acg0uooG+mLy+kNBzGhGzCdZHX fqaIbHtDrjBWl8hwEQ51Qe9uDU7PQXQewV1jYvbO9/qgeGPS5O1Q/U7cDTFMCSrAYS Tn8iJeLjyHUOA== From: Dinh Nguyen To: linux-clk@vger.kernel.org Cc: dinguyen@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, stable@vger.kernel.org, Kris Chaplin Subject: [PATCH 3/3] clk: socfpga: agilex: add the bypass register for s2f_usr0 clock Date: Tue, 13 Jul 2021 09:46:21 -0500 Message-Id: <20210713144621.605140-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713144621.605140-1-dinguyen@kernel.org> References: <20210713144621.605140-1-dinguyen@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the bypass register for the s2f_user0_clk. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-agilex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 7baaa16dea7b..242e94c0cf8a 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -280,7 +280,7 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = { { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux, ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0}, { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux, - ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0}, + ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, 2}, { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux, ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5}, { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,