From patchwork Tue Dec 4 19:48:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10712563 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 073AC13AF for ; Tue, 4 Dec 2018 19:48:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE40A28F2C for ; Tue, 4 Dec 2018 19:48:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E20D829F6C; Tue, 4 Dec 2018 19:48:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3009A29F5E for ; Tue, 4 Dec 2018 19:48:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725859AbeLDTs0 (ORCPT ); Tue, 4 Dec 2018 14:48:26 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:36615 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725886AbeLDTs0 (ORCPT ); Tue, 4 Dec 2018 14:48:26 -0500 Received: by mail-lj1-f196.google.com with SMTP id g11-v6so16079452ljk.3 for ; Tue, 04 Dec 2018 11:48:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=subject:from:to:references:organization:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=sc8MvtQxCmVpiClgDNU/2M1d/NPNsLLlA1tVvSdzAag=; b=rjj9veCXkRUrVeqNHxRo34F/aPmBy/We/ZCRXteBPUmtYl1UNztwCqLO2mzdzBSw3D 9fZCCbRHvRPzpTz9IpLJnYSGjsZ853cWBvQmEVBAgqWcb8820v0NczssMntnP5MJ1dwF E2FFizQtMEm9XC2/ViehOY2mTkL01KeZ+CNAUFxgCsz1MSyQBGkn1Fp2MBteFVG83Ork jgWwSrq7c+6gFiwI5MjBLMSGwlViBW7INluY0ql3xyrmMRKtnYZb9Sj3xWOLjHzUMgHq S+Gk8gA0AhBt44mjRtQcRyqHpYQsw2UE++lnfWBUaY7+EnnGKV+alOWgA6gDpOlVptdW C8Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=sc8MvtQxCmVpiClgDNU/2M1d/NPNsLLlA1tVvSdzAag=; b=QZX3vLvR938XM7a5C+wlxTsJYLSrRyK7xmNUjBhiZDEOu9tIhUpnh2dcU+nKmJgruK WzWSRJgQ25Jj4bdTvy+NlEi73xcPWy4NYV8kMBrM4hsWPKtgE5ocTIgMxBiGnMJTDpG+ bU4shSwO+vN5DYan1Bg2S418aEkVOoNbUnCJto2xgOx6wtV8OQYtw4uFLzNu/FDyOaYQ h0YsarcbGU4K3OLC3iupiqscpi4sPNpTt9DvH6NYrRsEQXA3N1xVMzs5zXsf8dKnVSPz Qgih6aawIjsw1CSsntL7NsuHgTNDdaCTEa83zNp4OmLUuXx6CDfKyHPNH5/zO0/LaXXu fw7w== X-Gm-Message-State: AA+aEWag+v9wiI7bMnehmHhRNBqVJpAmlXwtiFl7mtaUup6sc15E7M4e sIGN/UNZ9Cw5lRsJz78n8EwAHSosKeU= X-Google-Smtp-Source: AFSGD/VDbw7BWIUxmITAeKl8Pc+RNZ5enmRmpe1xQwH9PkFIyWq1MdbhCksO2yaRH8p0DYRLHFtmbw== X-Received: by 2002:a2e:9107:: with SMTP id m7-v6mr13831958ljg.23.1543952903309; Tue, 04 Dec 2018 11:48:23 -0800 (PST) Received: from wasted.cogentembedded.com ([31.173.84.250]) by smtp.gmail.com with ESMTPSA id u15-v6sm3595917lja.63.2018.12.04.11.48.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Dec 2018 11:48:22 -0800 (PST) Subject: [PATCH v2 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: Organization: Cogent Embedded Message-ID: <8d3bd6b4-61eb-ceef-dc99-eb26c83f9e03@cogentembedded.com> Date: Tue, 4 Dec 2018 22:48:21 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There's quite often repeated sequence of a CPG register read-modify-write, so it seems worth factoring it out into a function -- this saves 68 bytes of the object code (AArch64 gcc 4.8.5) and simplifies protecting all such sequences with a spinlock in the next patch... Signed-off-by: Sergei Shtylyov Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - moved the readl() call from the initializer in cpg_reg_modify(); - adjusted the patch description. drivers/clk/renesas/rcar-gen3-cpg.c | 38 ++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c @@ -30,6 +30,16 @@ #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ +static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set) +{ + u32 val; + + val = readl(reg); + val &= ~clear; + val |= set; + writel(val, reg); +}; + struct cpg_simple_notifier { struct notifier_block nb; void __iomem *reg; @@ -118,7 +128,6 @@ static int cpg_z_clk_set_rate(struct clk struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; unsigned int i; - u32 val, kick; /* Factor of 2 is for fixed divider */ mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); @@ -127,17 +136,14 @@ static int cpg_z_clk_set_rate(struct clk if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; - val = readl(zclk->reg) & ~zclk->mask; - val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask; - writel(val, zclk->reg); + cpg_reg_modify(zclk->reg, zclk->mask, + ((32 - mult) << __ffs(zclk->mask)) & zclk->mask); /* * Set KICK bit in FRQCRB to update hardware setting and wait for * clock change completion. */ - kick = readl(zclk->kick_reg); - kick |= CPG_FRQCRB_KICK; - writel(kick, zclk->kick_reg); + cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); /* * Note: There is no HW information about the worst case latency. @@ -262,12 +268,10 @@ static const struct sd_div_table cpg_sd_ static int cpg_sd_clock_enable(struct clk_hw *hw) { struct sd_clock *clock = to_sd_clock(hw); - u32 val = readl(clock->csn.reg); - - val &= ~(CPG_SD_STP_MASK); - val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK; - writel(val, clock->csn.reg); + cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK, + clock->div_table[clock->cur_div_idx].val & + CPG_SD_STP_MASK); return 0; } @@ -276,7 +280,7 @@ static void cpg_sd_clock_disable(struct { struct sd_clock *clock = to_sd_clock(hw); - writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg); + cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK); } static int cpg_sd_clock_is_enabled(struct clk_hw *hw) @@ -323,7 +327,6 @@ static int cpg_sd_clock_set_rate(struct { struct sd_clock *clock = to_sd_clock(hw); unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); - u32 val; unsigned int i; for (i = 0; i < clock->div_num; i++) @@ -335,10 +338,9 @@ static int cpg_sd_clock_set_rate(struct clock->cur_div_idx = i; - val = readl(clock->csn.reg); - val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK); - val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK); - writel(val, clock->csn.reg); + cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK, + clock->div_table[i].val & + (CPG_SD_STP_MASK | CPG_SD_FC_MASK)); return 0; } From patchwork Tue Dec 4 19:49:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10712567 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10FB1109C for ; Tue, 4 Dec 2018 19:49:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 045402C57D for ; Tue, 4 Dec 2018 19:49:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EC16E2C4F7; Tue, 4 Dec 2018 19:49:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 94C9A2C4F6 for ; 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Tue, 04 Dec 2018 11:49:45 -0800 (PST) Subject: [PATCH v2 2/4] clk: renesas: rcar-gen3-cpg: add spinlock From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: Organization: Cogent Embedded Message-ID: Date: Tue, 4 Dec 2018 22:49:44 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Protect the CPG register read-modify-write sequence with a spinlock. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - new patch. drivers/clk/renesas/rcar-gen3-cpg.c | 8 ++++++++ 1 file changed, 8 insertions(+) Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c @@ -30,14 +30,19 @@ #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ +static spinlock_t cpg_lock; + static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set) { + unsigned long flags; u32 val; + spin_lock_irqsave(&cpg_lock, flags); val = readl(reg); val &= ~clear; val |= set; writel(val, reg); + spin_unlock_irqrestore(&cpg_lock, flags); }; struct cpg_simple_notifier { @@ -604,5 +609,8 @@ int __init rcar_gen3_cpg_init(const stru if (attr) cpg_quirks = (uintptr_t)attr->data; pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); + + spin_lock_init(&cpg_lock); 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Tue, 04 Dec 2018 11:51:38 -0800 (PST) Subject: [PATCH v2 3/4] clk: renesas: rcar-gen3-cpg: add RPC clocks From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: Organization: Cogent Embedded Message-ID: <29eba2fe-942a-6b71-afc1-e30ac603f162@cogentembedded.com> Date: Tue, 4 Dec 2018 22:51:37 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field is different between SoCs; it makes sense to support the most common case of this encoding in the R-Car gen3 CPG driver... After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except V3M (R8A77970); the composite clock driver seems handy for this task, using the spinlock added in the previous patch... Signed-off-by: Sergei Shtylyov --- Changes in version 2: - merged in the RPCD2 clock support from the next patch; - moved in the RPCSRC clock support from the R8A77980 CPG/MSSR driver patch; - switched the RPC and RPCSD2 clock support to the composite clock driver; - changed the 1st parameter of cpg_rpc[d2]_clk_register(); - rewrote the patch description, renamed the patch. drivers/clk/renesas/rcar-gen3-cpg.c | 99 ++++++++++++++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 4 + 2 files changed, 103 insertions(+) Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c @@ -415,6 +415,90 @@ free_clock: return clk; } +struct rpc_clock { + struct clk_divider div; + struct clk_gate gate; + struct cpg_simple_notifier csn; +}; + +static const struct clk_div_table cpg_rpcsrc_div_table[] = { + { 2, 5 }, { 3, 6 }, { 0, 0 }, +}; + +static const struct clk_div_table cpg_rpc_div_table[] = { + { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 }, +}; + +static struct clk * __init cpg_rpc_clk_register(const char *name, + void __iomem *base, const char *parent_name, + struct raw_notifier_head *notifiers) +{ + struct rpc_clock *rpc; + struct clk *clk; + + rpc = kzalloc(sizeof(*rpc), GFP_KERNEL); + if (!rpc) + return ERR_PTR(-ENOMEM); + + rpc->div.reg = base + CPG_RPCCKCR; + rpc->div.width = 3; + rpc->div.table = cpg_rpc_div_table; + rpc->div.lock = &cpg_lock; + + rpc->gate.reg = base + CPG_RPCCKCR; + rpc->gate.bit_idx = 8; + rpc->gate.flags = CLK_GATE_SET_TO_DISABLE; + rpc->gate.lock = &cpg_lock; + + rpc->csn.reg = base + CPG_RPCCKCR; + + clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, + &rpc->div.hw, &clk_divider_ops, + &rpc->gate.hw, &clk_gate_ops, 0); + if (IS_ERR(clk)) + kfree(rpc); + + cpg_simple_notifier_register(notifiers, &rpc->csn); + return clk; +} + +static struct clk * __init cpg_rpcd2_clk_register(const char *name, + void __iomem *base, + const char *parent_name) +{ + struct clk_fixed_factor *fixed; + struct clk_gate *gate; + struct clk *clk; + + fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return ERR_PTR(-ENOMEM); + + fixed->mult = 1; + fixed->div = 2; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) { + kfree(fixed); + return ERR_PTR(-ENOMEM); + } + + gate->reg = base + CPG_RPCCKCR; + gate->bit_idx = 9; + gate->flags = CLK_GATE_SET_TO_DISABLE; + gate->lock = &cpg_lock; + + clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, + &fixed->hw, &clk_fixed_factor_ops, + &gate->hw, &clk_gate_ops, 0); + if (IS_ERR(clk)) { + kfree(fixed); + kfree(gate); + } + + return clk; +} + static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; @@ -589,6 +673,21 @@ struct clk * __init rcar_gen3_cpg_clk_re } break; + case CLK_TYPE_GEN3_RPCSRC: + return clk_register_divider_table(NULL, core->name, + __clk_get_name(parent), 0, + base + CPG_RPCCKCR, 3, 2, 0, + cpg_rpcsrc_div_table, + &cpg_lock); + + case CLK_TYPE_GEN3_RPC: + return cpg_rpc_clk_register(core->name, base, + __clk_get_name(parent), notifiers); + + case CLK_TYPE_GEN3_RPCD2: + return cpg_rpcd2_clk_register(core->name, base, + __clk_get_name(parent)); + default: return ERR_PTR(-EINVAL); } Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.h +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h @@ -23,6 +23,9 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ + CLK_TYPE_GEN3_RPCSRC, + CLK_TYPE_GEN3_RPC, + CLK_TYPE_GEN3_RPCD2, /* SoC specific definitions start here */ CLK_TYPE_GEN3_SOC_BASE, @@ -57,6 +60,7 @@ struct rcar_gen3_cpg_pll_config { u8 osc_prediv; }; +#define CPG_RPCCKCR 0x238 #define CPG_RCKCR 0x240 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, From patchwork Tue Dec 4 19:52:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10712575 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1025818B8 for ; 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Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the R-Car V3H (R8A77980) CPG/MSSR driver. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - moved the RPCSRC clock support to the R-Car gen3 CPG patch adding the RPC clocks; - rewrote the patch description. drivers/clk/renesas/r8a77980-cpg-mssr.c | 8 ++++++++ 1 file changed, 8 insertions(+) Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -41,6 +41,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_OCO, /* Module Clocks */ @@ -65,8 +66,14 @@ static const struct cpg_core_clk r8a7798 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_RATE(".oco", CLK_OCO, 32768), + DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A77980_CLK_RPC), + /* Core Clock Outputs */ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), @@ -164,6 +171,7 @@ static const struct mssr_mod_clk r8a7798 DEF_MOD("gpio1", 911, R8A77980_CLK_CP), DEF_MOD("gpio0", 912, R8A77980_CLK_CP), DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2), + DEF_MOD("rpc-if", 917, R8A77980_CLK_RPC), DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6), DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6), DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),