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Wysocki" , Sinan Kaya , "Amey Narkhede" , Shanker Donthineni Subject: [PATCH v11 1/8] PCI: Add pcie_reset_flr to follow calling convention of other reset methods Date: Thu, 15 Jul 2021 16:30:53 -0500 Message-ID: <20210715213100.11539-2-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210715213100.11539-1-sdonthineni@nvidia.com> References: <20210715213100.11539-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 21670185-f272-412a-a799-08d947d7fa20 X-MS-TrafficTypeDiagnostic: CY4PR12MB1255: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: D1hTivFfKeSCHdsS4HX7t4f+jFI9U2EchJGfO9aXtxqq9kHc2zN8pnWh46y4yblbZfItyM3d9kbzuVV6mnmkgeGciXDgv9toUsg+pGR+wYujGUuako2VfOKWhbqdm0LScVXbcCc544ABPT2v2CcQuGKy94V6i/aG8dzpLBzfgV7C7K2AF3inN5e1CQY+1xYetimm2V5P4VhNWn8OkrbkpGn26znllBwo+t051P0o0VwMAPAWA24y9EpkNIls1p0/9nNPda3Y0cfTdQ+nnwrqepfOGzjDghGLRw1YZ+Jjr1mbhcVN0VTX0UFdkzINk1PYGDYYVqUxqUjAPIs0x9wgNS5H7ibOnZndKIHWZ6jiffyhv+55N2oRfQ7sQ6JW1cQaU7mmFIWmDFVZMc2z3iS2aE8MIRMiAHPN9zgdRaMZl05Q8RB9vwGJUQZEGOKVpY/9jCskuJLDDMYV2Zs2/rAB1XQzRg10ASHkiWQMFWpT+pagq+QlniRCp75MLvaqOuzAp6C7ilZsd1EPZUtT6eKPzRtnPctF0/24H9km7buvEzrkelzA0RmgCoyTBo6URgVlVO77eJZNM6aZ29V6AzGnePWmi9kdEm5DD1S9/ZAGtdMeG2anKgqT3qRyPCYUlSeevu72c9gjJre/SAMXnASYfMcT6QV4KIg0suhBdCKj1CXHJTqC2XQIZw9wPHYaWKOy8zL445z4kcjM7n9e9tSfLY09FxJUlJ3nQISm09WvAD4= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(346002)(376002)(136003)(396003)(39860400002)(36840700001)(46966006)(70586007)(2616005)(6916009)(6666004)(5660300002)(336012)(478600001)(86362001)(16526019)(4326008)(70206006)(426003)(26005)(186003)(36906005)(316002)(34020700004)(82310400003)(82740400003)(8936002)(36756003)(8676002)(83380400001)(7636003)(356005)(36860700001)(107886003)(7696005)(54906003)(2906002)(1076003)(47076005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2021 21:31:58.7261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21670185-f272-412a-a799-08d947d7fa20 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1255 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Amey Narkhede Add has_pcie_flr bitfield in struct pci_dev to indicate support for PCIe FLR to avoid reading PCI_EXP_DEVCAP multiple times. Currently there is separate function pcie_has_flr() to probe if PCIe FLR is supported by the device which does not match the calling convention followed by reset methods which use second function argument to decide whether to probe or not. Add new function pcie_reset_flr() that follows the calling convention of reset methods. Signed-off-by: Amey Narkhede Reviewed-by: Alex Williamson --- drivers/crypto/cavium/nitrox/nitrox_main.c | 4 +- drivers/pci/pci.c | 59 +++++++++++----------- drivers/pci/pcie/aer.c | 12 ++--- drivers/pci/probe.c | 6 ++- drivers/pci/quirks.c | 9 ++-- include/linux/pci.h | 3 +- 6 files changed, 45 insertions(+), 48 deletions(-) diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c index 96bc7b5c6532d..2db3fd5815c82 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_main.c +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c @@ -306,9 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev) return -ENOMEM; } - /* check flr support */ - if (pcie_has_flr(pdev)) - pcie_flr(pdev); + pcie_reset_flr(pdev, 0); pci_restore_state(pdev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index aacf575c15cff..16870e4d7863a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4621,32 +4621,12 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev) } EXPORT_SYMBOL(pci_wait_for_pending_transaction); -/** - * pcie_has_flr - check if a device supports function level resets - * @dev: device to check - * - * Returns true if the device advertises support for PCIe function level - * resets. - */ -bool pcie_has_flr(struct pci_dev *dev) -{ - u32 cap; - - if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) - return false; - - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); - return cap & PCI_EXP_DEVCAP_FLR; -} -EXPORT_SYMBOL_GPL(pcie_has_flr); - /** * pcie_flr - initiate a PCIe function level reset * @dev: device to reset * - * Initiate a function level reset on @dev. The caller should ensure the - * device supports FLR before calling this function, e.g. by using the - * pcie_has_flr() helper. + * Initiate a function level reset unconditionally on @dev without + * checking any flags and DEVCAP */ int pcie_flr(struct pci_dev *dev) { @@ -4669,6 +4649,28 @@ int pcie_flr(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pcie_flr); +/** + * pcie_reset_flr - initiate a PCIe function level reset + * @dev: device to reset + * @probe: If set, only check if the device can be reset this way. + * + * Initiate a function level reset on @dev. + */ +int pcie_reset_flr(struct pci_dev *dev, int probe) +{ + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) + return -ENOTTY; + + if (!dev->has_pcie_flr) + return -ENOTTY; + + if (probe) + return 0; + + return pcie_flr(dev); +} +EXPORT_SYMBOL_GPL(pcie_reset_flr); + static int pci_af_flr(struct pci_dev *dev, int probe) { int pos; @@ -5151,11 +5153,9 @@ int __pci_reset_function_locked(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 0); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - if (rc != -ENOTTY) - return rc; - } + rc = pcie_reset_flr(dev, 0); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 0); if (rc != -ENOTTY) return rc; @@ -5186,8 +5186,9 @@ int pci_probe_reset_function(struct pci_dev *dev) rc = pci_dev_specific_reset(dev, 1); if (rc != -ENOTTY) return rc; - if (pcie_has_flr(dev)) - return 0; + rc = pcie_reset_flr(dev, 1); + if (rc != -ENOTTY) + return rc; rc = pci_af_flr(dev, 1); if (rc != -ENOTTY) return rc; diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index df4ba9b384c24..031379deb1304 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1407,13 +1407,11 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) } if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { - if (pcie_has_flr(dev)) { - rc = pcie_flr(dev); - pci_info(dev, "has been reset (%d)\n", rc); - } else { - pci_info(dev, "not reset (no FLR support)\n"); - rc = -ENOTTY; - } + rc = pcie_reset_flr(dev, 0); + if (!rc) + pci_info(dev, "has been reset\n"); + else + pci_info(dev, "not reset (no FLR support: %d)\n", rc); } else { rc = pci_bus_error_reset(dev); pci_info(dev, "%s Port link has been reset (%d)\n", diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 79177ac37880f..d99ef232169e2 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1488,6 +1488,7 @@ void set_pcie_port_type(struct pci_dev *pdev) { int pos; u16 reg16; + u32 reg32; int type; struct pci_dev *parent; @@ -1498,8 +1499,9 @@ void set_pcie_port_type(struct pci_dev *pdev) pdev->pcie_cap = pos; pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); pdev->pcie_flags_reg = reg16; - pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); - pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; + pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, ®32); + pdev->pcie_mpss = reg32 & PCI_EXP_DEVCAP_PAYLOAD; + pdev->has_pcie_flr = !!(reg32 & PCI_EXP_DEVCAP_FLR); parent = pci_upstream_bridge(pdev); if (!parent) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 6d74386eadc2c..90144fbc4f4ea 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3852,7 +3852,7 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) u32 cfg; if (dev->class != PCI_CLASS_STORAGE_EXPRESS || - !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) + pcie_reset_flr(dev, 1) || !pci_resource_start(dev, 0)) return -ENOTTY; if (probe) @@ -3921,13 +3921,10 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) */ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) { - if (!pcie_has_flr(dev)) - return -ENOTTY; + int ret = pcie_reset_flr(dev, probe); if (probe) - return 0; - - pcie_flr(dev); + return ret; msleep(250); diff --git a/include/linux/pci.h b/include/linux/pci.h index 540b377ca8f61..5652214fe3a58 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -337,6 +337,7 @@ struct pci_dev { u8 msi_cap; /* MSI capability offset */ u8 msix_cap; /* MSI-X capability offset */ u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ + u8 has_pcie_flr:1; /* PCIe FLR supported */ u8 rom_base_reg; /* Config register controlling ROM */ u8 pin; /* Interrupt pin this device uses */ u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ @@ -1228,7 +1229,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); void pcie_print_link_status(struct pci_dev *dev); -bool pcie_has_flr(struct pci_dev *dev); +int pcie_reset_flr(struct pci_dev *dev, int probe); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); From patchwork Thu Jul 15 21:30:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 12381155 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27FFDC636C9 for ; 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Wysocki" , Sinan Kaya , "Amey Narkhede" , Shanker Donthineni Subject: [PATCH v11 2/8] PCI: Add new array for keeping track of ordering of reset methods Date: Thu, 15 Jul 2021 16:30:54 -0500 Message-ID: <20210715213100.11539-3-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210715213100.11539-1-sdonthineni@nvidia.com> References: <20210715213100.11539-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5b62462d-0680-42bc-9bf2-08d947d7fb53 X-MS-TrafficTypeDiagnostic: MW2PR12MB2540: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: y3zsP4Iy9+E70BnKhB6+eQfEFQypvSyjdwfOI/QU8/FeT1stp6vN+DwPNyT2s9Cnf4HfxA23VoU8bBHuHe7IjhsuZNDKpfIw3ZhzTyv4jqnaRriw3r1BgX21YqzXNQkiNFgMvzjOFoLexg3xtSxGH63hhdcvf1Vq9w7lZ+YSFeex4ZYINso6UGrfM9zBMouxq9HtoXQ5Ub7tswvRz6PpsOAccGTlxp74qjyyMkvUrBXi80jcMYi7xjsSsQ3CN0oTnaa5tQKBI5fwvn4swOcgMyHkrlFZwHHbAFIo/PAPaidn5HDgyHgVSokkXQaF18Z9dAnWNKMPTcyV1auQCfL1wzmDd+c2M6Tfmb4XGxujyRJ2pht0c9BlgI8o4wVzGB/Pu8T5cmA+VMex9/mHslP6Vh80AdQYye74eEZStJ7hRKf08VgX/EvVoj40I1Rz48SFhVW0a+tdcjabwyqQMAvNC/QqtzhGOg/ri+XYFW5pDQBToabh/NR8f6kWcPu6ggTsCZsoaQx8bjwoD3opSobAyjKfoUD8SHenBqOAFy9lczaxv96oq+/5VBLXz5tJstbQFXA6yWoO9G8/M1P8aIzMC4jv03eWXbWJmPHras714+1gdXJyWvTDu6hyqPqcldH8fDGkDTg3Y1gugFhgkhxX7mT87D51jJPxSgQuA3/PVCM1cUZNFThvVnIh3KsxS441953Z97deWw3ZDBlQCLeAvSA4+PZG5S4oP92+fUawh9E= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(376002)(39860400002)(346002)(396003)(136003)(46966006)(36840700001)(8936002)(82310400003)(54906003)(7636003)(86362001)(2616005)(36906005)(34020700004)(316002)(1076003)(107886003)(8676002)(36860700001)(36756003)(2906002)(478600001)(6666004)(186003)(16526019)(47076005)(5660300002)(26005)(82740400003)(356005)(6916009)(7696005)(336012)(4326008)(83380400001)(426003)(70586007)(70206006);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2021 21:32:00.7958 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b62462d-0680-42bc-9bf2-08d947d7fb53 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2540 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Amey Narkhede Introduce a new array reset_methods in struct pci_dev to keep track of reset mechanisms supported by the device and their ordering. Also refactor probing and reset functions to take advantage of calling convention of reset functions. Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/pci/pci.c | 92 ++++++++++++++++++++++++++------------------- drivers/pci/pci.h | 9 ++++- drivers/pci/probe.c | 5 +-- include/linux/pci.h | 7 ++++ 4 files changed, 70 insertions(+), 43 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 16870e4d7863a..4d5618b232363 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -72,6 +72,14 @@ static void pci_dev_d3_sleep(struct pci_dev *dev) msleep(delay); } +int pci_reset_supported(struct pci_dev *dev) +{ + u8 null_reset_methods[PCI_NUM_RESET_METHODS] = { 0 }; + + return memcmp(null_reset_methods, + dev->reset_methods, sizeof(null_reset_methods)); +} + #ifdef CONFIG_PCI_DOMAINS int pci_domains_supported = 1; #endif @@ -5116,6 +5124,15 @@ static void pci_dev_restore(struct pci_dev *dev) err_handler->reset_done(dev); } +const struct pci_reset_fn_method pci_reset_fn_methods[] = { + { }, + { &pci_dev_specific_reset, .name = "device_specific" }, + { &pcie_reset_flr, .name = "flr" }, + { &pci_af_flr, .name = "af_flr" }, + { &pci_pm_reset, .name = "pm" }, + { &pci_reset_bus_function, .name = "bus" }, +}; + /** * __pci_reset_function_locked - reset a PCI device function while holding * the @dev mutex lock. @@ -5138,65 +5155,62 @@ static void pci_dev_restore(struct pci_dev *dev) */ int __pci_reset_function_locked(struct pci_dev *dev) { - int rc; + int i, m, rc = -ENOTTY; might_sleep(); /* - * A reset method returns -ENOTTY if it doesn't support this device - * and we should try the next method. + * A reset method returns -ENOTTY if it doesn't support this device and + * we should try the next method. * - * If it returns 0 (success), we're finished. If it returns any - * other error, we're also finished: this indicates that further - * reset mechanisms might be broken on the device. + * If it returns 0 (success), we're finished. If it returns any other + * error, we're also finished: this indicates that further reset + * mechanisms might be broken on the device. */ - rc = pci_dev_specific_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 0); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 0); - if (rc != -ENOTTY) - return rc; - return pci_reset_bus_function(dev, 0); + for (i = 0; i < PCI_NUM_RESET_METHODS && (m = dev->reset_methods[i]); i++) { + rc = pci_reset_fn_methods[m].reset_fn(dev, 0); + if (!rc) + return 0; + if (rc != -ENOTTY) + return rc; + } + + return -ENOTTY; } EXPORT_SYMBOL_GPL(__pci_reset_function_locked); /** - * pci_probe_reset_function - check whether the device can be safely reset - * @dev: PCI device to reset + * pci_init_reset_methods - check whether device can be safely reset + * and store supported reset mechanisms. + * @dev: PCI device to check for reset mechanisms * * Some devices allow an individual function to be reset without affecting * other functions in the same device. The PCI device must be responsive - * to PCI config space in order to use this function. + * to reads and writes to its PCI config space in order to use this function. * - * Returns 0 if the device function can be reset or negative if the - * device doesn't support resetting a single function. + * Stores reset mechanisms supported by device in reset_methods byte array + * which is a member of struct pci_dev. */ -int pci_probe_reset_function(struct pci_dev *dev) +void pci_init_reset_methods(struct pci_dev *dev) { - int rc; + int i, n, rc; + u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 }; + + n = 0; + + BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS); might_sleep(); - rc = pci_dev_specific_reset(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pcie_reset_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_af_flr(dev, 1); - if (rc != -ENOTTY) - return rc; - rc = pci_pm_reset(dev, 1); - if (rc != -ENOTTY) - return rc; + for (i = 1; i < PCI_NUM_RESET_METHODS; i++) { + rc = pci_reset_fn_methods[i].reset_fn(dev, 1); + if (!rc) + reset_methods[n++] = i; + else if (rc != -ENOTTY) + break; + } - return pci_reset_bus_function(dev, 1); + memcpy(dev->reset_methods, reset_methods, sizeof(reset_methods)); } /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 93dcdd4310726..482d26cff7912 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -33,7 +33,8 @@ enum pci_mmap_api { int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, enum pci_mmap_api mmap_api); -int pci_probe_reset_function(struct pci_dev *dev); +int pci_reset_supported(struct pci_dev *dev); +void pci_init_reset_methods(struct pci_dev *dev); int pci_bridge_secondary_bus_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev); @@ -610,6 +611,12 @@ struct pci_dev_reset_methods { int (*reset)(struct pci_dev *dev, int probe); }; +struct pci_reset_fn_method { + int (*reset_fn)(struct pci_dev *pdev, int probe); + char *name; +}; + +extern const struct pci_reset_fn_method pci_reset_fn_methods[]; #ifdef CONFIG_PCI_QUIRKS int pci_dev_specific_reset(struct pci_dev *dev, int probe); #else diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index d99ef232169e2..4ce7979d703eb 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2430,9 +2430,8 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rcec_init(dev); /* Root Complex Event Collector */ pcie_report_downtraining(dev); - - if (pci_probe_reset_function(dev) == 0) - dev->reset_fn = 1; + pci_init_reset_methods(dev); + dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/include/linux/pci.h b/include/linux/pci.h index 5652214fe3a58..8c2d3a357eedb 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -49,6 +49,9 @@ PCI_STATUS_SIG_TARGET_ABORT | \ PCI_STATUS_PARITY) +/* Number of reset methods used in pci_reset_fn_methods array in pci.c */ +#define PCI_NUM_RESET_METHODS 6 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -506,6 +509,10 @@ struct pci_dev { char *driver_override; /* Driver name to force a match */ unsigned long priv_flags; /* Private flags for the PCI driver */ + /* + * See pci_reset_fn_methods array in pci.c for ordering. + */ + u8 reset_methods[PCI_NUM_RESET_METHODS]; /* Reset methods ordered by priority */ }; static inline struct pci_dev *pci_physfn(struct pci_dev *dev) From patchwork Thu Jul 15 21:30:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 12381157 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 384FBC636CD for ; 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Wysocki" , Sinan Kaya , "Amey Narkhede" , Shanker Donthineni , Raphael Norwitz Subject: [PATCH v11 3/8] PCI: Remove reset_fn field from pci_dev Date: Thu, 15 Jul 2021 16:30:55 -0500 Message-ID: <20210715213100.11539-4-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210715213100.11539-1-sdonthineni@nvidia.com> References: <20210715213100.11539-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9937bcf8-6e27-43ac-124c-08d947d7fc62 X-MS-TrafficTypeDiagnostic: DM6PR12MB5552: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vVqi32VvYUXJE/a33763wRaOSqX6EpJ9yzdCHXluR6JD2IobtBVzmffeCciBJ+d6S4oI5IYqcVm0lKgoFWPE1S9acs0dnZfZ9zPjligTvekPMPbqutiMy0+3d0HQBzL2otwcBLckYZTnvs+upZOdAOfQ2b/ng788RKMCsMPIJiLbVn/wvGOAXzcZlE9WMW5pbknJr2wei22qdSwdQQb9wpENW5uqsyobd60A1A5VstgxKyyuWaDVruaeFqBdefJDSyahN+D4TJrbrSNOl/8PLF/nZ1YY0grMLfO1oyKyMBQTRE09UNE3xXqOOgB9JTaHofZqE3w8IN1YRs87kMFccCorzuwtu2xl48A78pK1JstPoCHCLCDfLvtjYtZzQI45TNaQ9SzjAxasgrh32KQ8K8avPjS9QIBFwXI4jjzTottlbiCmvix8EH5QINvxwKGigvCzYm4BNJ21GVfVV1g5NRGxfTEXYwTilnQYK86nwxYcQLPHPcLTeGOkXCaLOptU3b6aXkNwHAW5J2ooVtYUYTchWaNrniHGSwT7i1CuCQeXxP+KIRPhrXF/bqIXHilK9MPQPUGzZ5rvgCcvEHVTis0rXfnzXZ9gEbRrlBWANjzy4sVz23ZHVZi3MN7cacQOQlKkR73LMM1X9iONqW6ndNxkV4VJXicsoGwXSLU+5Rx+QyYSK9OSATncMps2h5ntIyy9iX1U6FgTxbtb+Kj60pQW31wDw66tFeVDjUCj8II= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(39860400002)(346002)(376002)(396003)(136003)(46966006)(36840700001)(36756003)(86362001)(4326008)(6916009)(2616005)(8676002)(1076003)(6666004)(36906005)(336012)(5660300002)(316002)(83380400001)(54906003)(26005)(7696005)(34020700004)(70206006)(16526019)(47076005)(7636003)(36860700001)(2906002)(82310400003)(8936002)(186003)(7416002)(82740400003)(356005)(426003)(478600001)(70586007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2021 21:32:02.5783 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9937bcf8-6e27-43ac-124c-08d947d7fc62 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5552 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Amey Narkhede reset_fn field is used to indicate whether the device supports any reset mechanism or not. Remove the use of reset_fn in favor of new reset_methods array which can be used to keep track of all supported reset mechanisms of a device and their ordering. The octeon driver is incorrectly using reset_fn field to detect if the device supports FLR or not. Use pcie_reset_flr() to probe whether it supports FLR or not. Reviewed-by: Alex Williamson Reviewed-by: Raphael Norwitz Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede --- drivers/net/ethernet/cavium/liquidio/lio_vf_main.c | 2 +- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/pci.c | 6 +++--- drivers/pci/probe.c | 1 - drivers/pci/quirks.c | 2 +- drivers/pci/remove.c | 1 - include/linux/pci.h | 1 - 7 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c index ffddb3126a323..d185df5acea69 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c @@ -526,7 +526,7 @@ static void octeon_destroy_resources(struct octeon_device *oct) oct->irq_name_storage = NULL; } /* Soft reset the octeon device before exiting */ - if (oct->pci_dev->reset_fn) + if (!pcie_reset_flr(oct->pci_dev, 1)) octeon_pci_flr(oct); else cn23xx_vf_ask_pf_to_do_flr(oct); diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 5d63df7c18206..a1d9b0e83615a 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1367,7 +1367,7 @@ static umode_t pci_dev_reset_attr_is_visible(struct kobject *kobj, { struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj)); - if (!pdev->reset_fn) + if (!pci_reset_supported(pdev)) return 0; return a->mode; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4d5618b232363..cc9f96effa546 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5233,7 +5233,7 @@ int pci_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_lock(dev); @@ -5269,7 +5269,7 @@ int pci_reset_function_locked(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; pci_dev_save_and_disable(dev); @@ -5292,7 +5292,7 @@ int pci_try_reset_function(struct pci_dev *dev) { int rc; - if (!dev->reset_fn) + if (!pci_reset_supported(dev)) return -ENOTTY; if (!pci_dev_trylock(dev)) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4ce7979d703eb..66f052446de20 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2431,7 +2431,6 @@ static void pci_init_capabilities(struct pci_dev *dev) pcie_report_downtraining(dev); pci_init_reset_methods(dev); - dev->reset_fn = pci_reset_supported(dev); } /* diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 90144fbc4f4ea..f43883a2e33df 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5626,7 +5626,7 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || pdev->subsystem_device != 0x222e || - !pdev->reset_fn) + !pci_reset_supported(pdev)) return; if (pci_enable_device_mem(pdev)) diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index dd12c2fcc7dc1..4c54c75050dc1 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -19,7 +19,6 @@ static void pci_stop_dev(struct pci_dev *dev) pci_pme_active(dev, false); if (pci_dev_is_added(dev)) { - dev->reset_fn = 0; device_release_driver(&dev->dev); pci_proc_detach_device(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 8c2d3a357eedb..58cc2e2b05051 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -431,7 +431,6 @@ struct pci_dev { unsigned int state_saved:1; unsigned int is_physfn:1; unsigned int is_virtfn:1; - unsigned int reset_fn:1; unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ From patchwork Thu Jul 15 21:30:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 12381159 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B702C636CE for ; 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Wysocki" , Sinan Kaya , "Amey Narkhede" , Shanker Donthineni , Leon Romanovsky Subject: [PATCH v11 4/8] PCI/sysfs: Allow userspace to query and set device reset mechanism Date: Thu, 15 Jul 2021 16:30:56 -0500 Message-ID: <20210715213100.11539-5-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210715213100.11539-1-sdonthineni@nvidia.com> References: <20210715213100.11539-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ee13e45c-b2bf-4c79-eaf2-08d947d7fdaf X-MS-TrafficTypeDiagnostic: CH2PR12MB4054: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1388; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1lEYqyh4YkfU9/XGFJ/WxlcwkUUI2yAsngEinmJYgKwPMC0YnKKSK/c6kJ8OvMQgqzBfMX0p7ros07dD9Cs3yLngv2rtqBsZAFmYH4Di5rnnBPg4HMVHMYqjidwOoRYSaEOTlnYr5OS7U81rcURGaVPekVfkk5R2sx0l4k2K8rNKH/MeNdXR2Ggcs/2iIBkzTQ4xRpywYzjKUPEdBNZQkRZ/JS9srBCJ4TjJuekOQ8tir2b1H2l31j81xKeUV5ehGqfSBMNg9n2g4+XRxkNj4uWMZ3ffaTDdFy0aLrSD2CxccS72+GhlgnlyKJ6/yirMDWcHg36nKQprSEXKWU3PSA8esAueUKlLFpATDPp8PC7aSdUvbDGDzXGTMXThP6TJuDqT2CanNWtA30lSzR61ljViK8ixPW5BSGMxZLqzWgWu4cP6J6CVigOHWKtw8qhuw9IIzmW1u5Klg/M6vKHNAJDW4I0aYopVIxkpjCfhnrqz38qxOnXrPZUJn+bs6MYAT9omkcbRFwMCTP5MWqhjJYqJUOwnNZkxeQ37+mv4/vaeKmFx9QMLg0LxKPf0rN7ybstC9vs2WR6ADzgRPpGTByirimSyYLExNbw5hVg5ij4iZYIzyUPnZTD6HribHGsLchmHtX1vW+oqjenYsD9ibV0nqLBnY3D6XM6quxQJ91v7yi/WJK0BIL1MX3hSuSXb1Tr0BxIVnuOwmKClF1UtA8luaRXfSiNQiuiaS18r7r8= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(346002)(136003)(39860400002)(376002)(396003)(46966006)(36840700001)(83380400001)(1076003)(186003)(4326008)(8936002)(356005)(107886003)(26005)(54906003)(316002)(36860700001)(36756003)(82740400003)(34020700004)(5660300002)(16526019)(2906002)(47076005)(6916009)(36906005)(8676002)(70206006)(82310400003)(86362001)(70586007)(2616005)(426003)(7696005)(6666004)(7636003)(478600001)(336012);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2021 21:32:04.6432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee13e45c-b2bf-4c79-eaf2-08d947d7fdaf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4054 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Amey Narkhede Add reset_method sysfs attribute to enable user to query and set user preferred device reset methods and their ordering. Co-developed-by: Alex Williamson Signed-off-by: Alex Williamson Signed-off-by: Amey Narkhede Reviewed-by: Leon Romanovsky --- Documentation/ABI/testing/sysfs-bus-pci | 19 +++++ drivers/pci/pci-sysfs.c | 103 ++++++++++++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index 793cbb76cd250..beb94b9c18c78 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -121,6 +121,25 @@ Description: child buses, and re-discover devices removed earlier from this part of the device tree. +What: /sys/bus/pci/devices/.../reset_method +Date: March 2021 +Contact: Amey Narkhede +Description: + Some devices allow an individual function to be reset + without affecting other functions in the same slot. + + For devices that have this support, a file named + reset_method will be present in sysfs. Initially reading + this file will give names of the device supported reset + methods and their ordering. After write, this file will + give names and ordering of currently enabled reset methods. + Writing the name or comma separated list of names of any of + the device supported reset methods to this file will set + the reset methods and their ordering to be used when + resetting the device. Writing empty string to this file + will disable ability to reset the device and writing + "default" will return to the original value. + What: /sys/bus/pci/devices/.../reset Date: July 2009 Contact: Michael S. Tsirkin diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index a1d9b0e83615a..65791d8b07aa5 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1334,6 +1334,108 @@ static const struct attribute_group pci_dev_rom_attr_group = { .is_bin_visible = pci_dev_rom_attr_is_visible, }; +static ssize_t reset_method_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + ssize_t len = 0; + int i, idx; + + for (i = 0; i < PCI_NUM_RESET_METHODS; i++) { + idx = pdev->reset_methods[i]; + if (!idx) + break; + + len += sysfs_emit_at(buf, len, "%s%s", len ? "," : "", + pci_reset_fn_methods[idx].name); + } + + if (len) + len += sysfs_emit_at(buf, len, "\n"); + + return len; +} + +static ssize_t reset_method_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pci_dev *pdev = to_pci_dev(dev); + int n = 0; + char *name, *options = NULL; + u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 }; + + if (count >= (PAGE_SIZE - 1)) + return -EINVAL; + + if (sysfs_streq(buf, "")) { + pci_warn(pdev, "All device reset methods disabled by user"); + goto set_reset_methods; + } + + if (sysfs_streq(buf, "default")) { + pci_init_reset_methods(pdev); + return count; + } + + options = kstrndup(buf, count, GFP_KERNEL); + if (!options) + return -ENOMEM; + + while ((name = strsep(&options, ",")) != NULL) { + int i; + + if (sysfs_streq(name, "")) + continue; + + name = strim(name); + + for (i = 1; i < PCI_NUM_RESET_METHODS; i++) { + if (sysfs_streq(name, pci_reset_fn_methods[i].name) && + !pci_reset_fn_methods[i].reset_fn(pdev, 1)) { + reset_methods[n++] = i; + break; + } + } + + if (i == PCI_NUM_RESET_METHODS) { + kfree(options); + return -EINVAL; + } + } + + if (!pci_reset_fn_methods[1].reset_fn(pdev, 1) && reset_methods[0] != 1) + pci_warn(pdev, "Device specific reset disabled/de-prioritized by user"); + +set_reset_methods: + memcpy(pdev->reset_methods, reset_methods, sizeof(reset_methods)); + kfree(options); + return count; +} +static DEVICE_ATTR_RW(reset_method); + +static struct attribute *pci_dev_reset_method_attrs[] = { + &dev_attr_reset_method.attr, + NULL, +}; + +static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj, + struct attribute *a, int n) +{ + struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj)); + + if (!pci_reset_supported(pdev)) + return 0; + + return a->mode; +} + +static const struct attribute_group pci_dev_reset_method_attr_group = { + .attrs = pci_dev_reset_method_attrs, + .is_visible = pci_dev_reset_method_attr_is_visible, +}; + static ssize_t reset_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -1491,6 +1593,7 @@ const struct attribute_group *pci_dev_groups[] = { &pci_dev_config_attr_group, &pci_dev_rom_attr_group, &pci_dev_reset_attr_group, + &pci_dev_reset_method_attr_group, &pci_dev_vpd_attr_group, #ifdef CONFIG_DMI &pci_dev_smbios_attr_group, From patchwork Thu Jul 15 21:30:57 2021 Content-Type: text/plain; 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Wysocki" , Sinan Kaya , "Amey Narkhede" , Shanker Donthineni Subject: [PATCH v11 5/8] PCI: Define a function to set ACPI_COMPANION in pci_dev Date: Thu, 15 Jul 2021 16:30:57 -0500 Message-ID: <20210715213100.11539-6-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210715213100.11539-1-sdonthineni@nvidia.com> References: <20210715213100.11539-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a1706e09-d44c-44c1-9ac8-08d947d7fe7a X-MS-TrafficTypeDiagnostic: MWHPR12MB1885: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2582; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mIKtd3jnqB3hQ9rPbogSpmOQJsRjGKT+Eq1XlJVAM+7hmrMR5yklaonExnIfoxG/CB6XULblbCXIQgMESg27mYHwkY66/Xz7Gmi903/lGDveHvl4rMthVeDh3uustPcdDpRo/V4rlPfAcm26BmBHqC556Z+zTtEmJPdjC0UuaUBGjwd1qLE+apnzAYcdkMNHgkmk/etpQ7yOP9Cbwj0UlOWmMDaqKiFV5z0ypRZs8vgBv8iEIwxzboWF60YV2UKGCwMdtY/Wxy31xZ4c+QgRXx7gUyrZ+fbY9843LmzWjkeW+8vLfmK89QyBLLXdSsnL51cYrtHM+lHXHa/DTX9XxcSI1NTV1AB6xowmJ+GpR3mMKVSJIYm12E5yMMI0CCVY2VUjjd7D/fHmgMOzj6fDRIQ9ZxGcysKlwIHsoQKWpk7A83eZswF5C+mbA4BdeLAymiTUXiGxTHLd+C0UiDxlEyCLjwGL9a71go8akvQru7R1+VKRv634f7HOetAukkKyqMrxvSTKhkut8EWLbL6gP6M14DhiU/U239stPNl1SuM7HmlzTY/6Xd0LV1oJbs2kjaCUZTb5M/iGJBJqhzU6pU2Ke5UE02QqPoB0HoEgHo6MFsNbBClsGGJYKHs/eEkRjkltfqsfvECNlxPE3CQdJ1zyKcsWV6J8zIYgXkOSQ/ieLzK4LvonB6YfraIFTc82POMfkLUihIkXsNmvVZ+eV5ptHmTLuxseBiflNYvXfWc= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(426003)(82310400003)(86362001)(2616005)(6916009)(26005)(36860700001)(107886003)(356005)(34020700004)(54906003)(7636003)(478600001)(316002)(47076005)(6666004)(8676002)(70586007)(186003)(4326008)(36756003)(2906002)(36906005)(70206006)(1076003)(83380400001)(7696005)(336012)(5660300002)(16526019)(8936002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2021 21:32:06.0225 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1706e09-d44c-44c1-9ac8-08d947d7fe7a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1885 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Move the existing code logic from acpi_pci_bridge_d3() to a separate function pci_set_acpi_fwnode() to set the ACPI fwnode. No functional change with this patch. Signed-off-by: Shanker Donthineni Reviewed-by: Alex Williamson --- drivers/pci/pci-acpi.c | 12 ++++++++---- drivers/pci/pci.h | 2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 36bc23e217592..eaddbf7017594 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -934,6 +934,13 @@ static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) static struct acpi_device *acpi_pci_find_companion(struct device *dev); +void pci_set_acpi_fwnode(struct pci_dev *dev) +{ + if (!ACPI_COMPANION(&dev->dev) && !pci_dev_is_added(dev)) + ACPI_COMPANION_SET(&dev->dev, + acpi_pci_find_companion(&dev->dev)); +} + static bool acpi_pci_bridge_d3(struct pci_dev *dev) { const struct fwnode_handle *fwnode; @@ -945,11 +952,8 @@ static bool acpi_pci_bridge_d3(struct pci_dev *dev) return false; /* Assume D3 support if the bridge is power-manageable by ACPI. */ + pci_set_acpi_fwnode(dev); adev = ACPI_COMPANION(&dev->dev); - if (!adev && !pci_dev_is_added(dev)) { - adev = acpi_pci_find_companion(&dev->dev); - ACPI_COMPANION_SET(&dev->dev, adev); - } if (adev && acpi_device_power_manageable(adev)) return true; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 482d26cff7912..37381734fcc78 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -708,7 +708,9 @@ static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL #ifdef CONFIG_ACPI int pci_acpi_program_hp_params(struct pci_dev *dev); extern const struct attribute_group pci_dev_acpi_attr_group; +void pci_set_acpi_fwnode(struct pci_dev *dev); #else +static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {} static inline int pci_acpi_program_hp_params(struct pci_dev *dev) { return -ENODEV; From patchwork Thu Jul 15 21:30:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 12381163 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96D35C636CD for ; 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Wysocki" , Sinan Kaya , "Amey Narkhede" , Shanker Donthineni Subject: [PATCH v11 6/8] PCI: Setup ACPI fwnode early and at the same time with OF Date: Thu, 15 Jul 2021 16:30:58 -0500 Message-ID: <20210715213100.11539-7-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210715213100.11539-1-sdonthineni@nvidia.com> References: <20210715213100.11539-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c62fba77-e0c8-402a-85bf-08d947d800fc X-MS-TrafficTypeDiagnostic: MN2PR12MB3023: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tozVFMrHMsybDcm3eyG4wuJg4AJ8c+PjDmbiCBpOEmDAmEfn1/sTpWohFo+FRJUl5ixJIhEbAme1y+gLp8sVUB1r+v/u9pwCLGsU86qSjcCbS/KOlaYodcvv6nCUvcgzgKovaXENTUkCM5V01eUSLowRMD1S2jF4AE4DOioD4ZwzPx1BI6XvxQeaSTVGbf0gBm+k4Z3x6rZ+IeIMU4a5AceNCOniZ1+Pxp6RUTqUK7D38WUaXiQFYdmSeZ+nt/2J2x44avglfjTP/eJfYGXyvHOG92yS0J+DiCWxg3r5L8rYHrXUAevN4jGfO83kgAxbZv/x6B36SrGRl478eBb6oUbi45lVnMnnlcz1IlenGzmxr2UWziR5/10yW/+31G/qyGFDXM6ysSanyp+itn2TzDac4jpcUx0wzBCipUok16686r26mOSV0De/H/TY7v4+o/LuEDZ+H9GImMp9tJ7AZ19LmJN+Vfdixv8mrCw85UvIkqJHQ1+mbqQ7eBd6T/vyg3uQjdxDXAgv1H2aE6ccPSZsxWs9g3yGL2yqM3G6+91exrBQcqvixqxQX8IpO4aMZKv6Ls0B6Vwcyw1dCw9/Nurnu4SiSoZ+vJMLqthjomYf/PLtoIldRvU2YzHG7Pko8VJffbEamkQOg3Iv8FFYAncl97hLa+0ZIVQkyy2b4SCEBLw6FHL5n4Pbvah+DgqD7blvs2BYSXUpAQz/c/L8dZG0XVzyD86LXaUGHLyxkMlKrQVlvMHFupZZ4wrl/Z6pzk7/rWdrBtIqgOArOmvo2A== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(39860400002)(396003)(376002)(136003)(346002)(46966006)(36840700001)(34020700004)(86362001)(82310400003)(83380400001)(8936002)(6916009)(8676002)(5660300002)(26005)(16526019)(186003)(4326008)(2906002)(2616005)(70206006)(7696005)(70586007)(336012)(426003)(316002)(36860700001)(47076005)(356005)(82740400003)(6666004)(478600001)(1076003)(107886003)(54906003)(36756003)(7636003)(36906005)(21314003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2021 21:32:09.7466 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c62fba77-e0c8-402a-85bf-08d947d800fc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3023 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The pci_dev objects are created through two mechanisms 1) during PCI bus scan and 2) from I/O Virtualization. The fwnode in pci_dev object is being set at different places depends on the type of firmware used, device creation mechanism, and acpi_pci_bridge_d3() WAR. The software features which have a dependency on ACPI fwnode properties and need to be handled before device_add() will not work. One use case, the software has to check the existence of _RST method to support ACPI based reset method. This patch does the two changes in order to provide fwnode consistently. - Set ACPI and OF fwnodes from pci_setup_device(). - Remove pci_set_acpi_fwnode() in acpi_pci_bridge_d3(). After this patch, ACPI/OF firmware properties are visible at the same time during the early stage of pci_dev setup. And also call sites should be able to use firmware agnostic functions device_property_xxx() for the early PCI quirks in the future. Signed-off-by: Shanker Donthineni Reviewed-by: Alex Williamson --- drivers/pci/pci-acpi.c | 1 - drivers/pci/probe.c | 7 ++++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index eaddbf7017594..dae021322b3fc 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -952,7 +952,6 @@ static bool acpi_pci_bridge_d3(struct pci_dev *dev) return false; /* Assume D3 support if the bridge is power-manageable by ACPI. */ - pci_set_acpi_fwnode(dev); adev = ACPI_COMPANION(&dev->dev); if (adev && acpi_device_power_manageable(adev)) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 66f052446de20..a0f20a6e3c04c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1811,6 +1811,9 @@ int pci_setup_device(struct pci_dev *dev) dev->error_state = pci_channel_io_normal; set_pcie_port_type(dev); + pci_set_of_node(dev); + pci_set_acpi_fwnode(dev); + pci_dev_assign_slot(dev); /* @@ -1948,6 +1951,7 @@ int pci_setup_device(struct pci_dev *dev) default: /* unknown header */ pci_err(dev, "unknown header type %02x, ignoring device\n", dev->hdr_type); + pci_release_of_node(dev); return -EIO; bad: @@ -2376,10 +2380,7 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) dev->vendor = l & 0xffff; dev->device = (l >> 16) & 0xffff; - pci_set_of_node(dev); - if (pci_setup_device(dev)) { - pci_release_of_node(dev); pci_bus_put(dev->bus); kfree(dev); return NULL; From patchwork Thu Jul 15 21:30:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 12381161 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8B78C636CB for ; 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Wysocki" , Sinan Kaya , "Amey Narkhede" , Shanker Donthineni Subject: [PATCH v11 7/8] PCI: Add support for ACPI _RST reset method Date: Thu, 15 Jul 2021 16:30:59 -0500 Message-ID: <20210715213100.11539-8-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210715213100.11539-1-sdonthineni@nvidia.com> References: <20210715213100.11539-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 147a66e4-86a6-44ef-b402-08d947d801ba X-MS-TrafficTypeDiagnostic: CY4PR12MB1445: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OhIpg0jzmB1zSpbCqFPqPpkL0YnkwTmowMMKTc8bxrlUyqtD08U8wwRYXquzynCeV+jFA11ZwDmIZ8pBoMeZ79h5tkJ3DXsTjDR8KcRZE1HiUloMdPUcFji2dMsWUMPzK3hIumU2J63mUPQ/UZqUAwct3C8hW0vm5G4I9JowlLW1jMfZ6mTRLngGmWgO8DV3jvYlnueVNpvnThPDEvgmcIOdBx6229LSJ5Ot2GJJT+7cs9RJDDgb1qpuASUb49h8u9RMOSJghzi75GhlZklBTcitgx4NmyOTWBI1E9myHCWgo3wNGdwJaONjQYbbmNuTfNyz7eiSdeyQLVpnwGfVjzD2MQjnvv86lCTUZDewoJPEPMgczmQ/6DcWVZ8/g8jbW+o19H/HrR9exutwZhulgbT7NHgYL/cfOzR2FCXWmIoa07F2WQw2sXqNqn4sMY9qk869Rvyz6wKXSenhArZSxsaNCJOiURYA8+0HCbxAkQP8n3sH2SSH5ytYA8vM0Ht/Dz/B6U8wYwwKk5f7D501YqlzLmA5QL6N3coWEwCzlyPB8x5cUiGDgGIzrVXHGxOqKgYunFChxm8xdmWvAkLrOIMnD+SNY6jUGg2GUg3xdirE5R3BQpuJTzaSNWmm55S/cMT3EBT1Nh5EZoU2jNQdxckxy/lWyt9vhMxdziOBvGHfMAOUzRBhNwyRcqYzFtG6JzmDeInLa4uKu2SmdxQUianBWs9WtKVCHRyowMEk3qs= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(396003)(376002)(136003)(39860400002)(346002)(46966006)(36840700001)(426003)(36906005)(336012)(26005)(70206006)(186003)(478600001)(2616005)(6916009)(54906003)(36860700001)(316002)(5660300002)(8936002)(70586007)(7696005)(107886003)(8676002)(86362001)(82310400003)(82740400003)(6666004)(2906002)(36756003)(7636003)(356005)(4326008)(47076005)(16526019)(1076003)(34020700004)(83380400001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2021 21:32:11.4908 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 147a66e4-86a6-44ef-b402-08d947d801ba X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1445 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The _RST is a standard method specified in the ACPI specification. It provides a function level reset when it is described in the acpi_device context associated with PCI-device. Implement a new reset function pci_dev_acpi_reset() for probing RST method and execute if it is defined in the firmware. The default priority of the ACPI reset is set to below device-specific and above hardware resets. Signed-off-by: Shanker Donthineni Suggested-by: Alex Williamson Reviewed-by: Sinan Kaya Reviewed-by: Alex Williamson --- drivers/pci/pci-acpi.c | 23 +++++++++++++++++++++++ drivers/pci/pci.c | 1 + drivers/pci/pci.h | 6 ++++++ include/linux/pci.h | 2 +- 4 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index dae021322b3fc..31f76746741f5 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -941,6 +941,29 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) acpi_pci_find_companion(&dev->dev)); } +/** + * pci_dev_acpi_reset - do a function level reset using _RST method + * @dev: device to reset + * @probe: check if _RST method is included in the acpi_device context. + */ +int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +{ + acpi_handle handle = ACPI_HANDLE(&dev->dev); + + if (!handle || !acpi_has_method(handle, "_RST")) + return -ENOTTY; + + if (probe) + return 0; + + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { + pci_warn(dev, "ACPI _RST failed\n"); + return -ENOTTY; + } + + return 0; +} + static bool acpi_pci_bridge_d3(struct pci_dev *dev) { const struct fwnode_handle *fwnode; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index cc9f96effa546..8aab4097f80bc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5127,6 +5127,7 @@ static void pci_dev_restore(struct pci_dev *dev) const struct pci_reset_fn_method pci_reset_fn_methods[] = { { }, { &pci_dev_specific_reset, .name = "device_specific" }, + { &pci_dev_acpi_reset, .name = "acpi" }, { &pcie_reset_flr, .name = "flr" }, { &pci_af_flr, .name = "af_flr" }, { &pci_pm_reset, .name = "pm" }, diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 37381734fcc78..699d14243867a 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -709,7 +709,13 @@ static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL int pci_acpi_program_hp_params(struct pci_dev *dev); extern const struct attribute_group pci_dev_acpi_attr_group; void pci_set_acpi_fwnode(struct pci_dev *dev); +int pci_dev_acpi_reset(struct pci_dev *dev, int probe); #else +static inline int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +{ + return -ENOTTY; +} + static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {} static inline int pci_acpi_program_hp_params(struct pci_dev *dev) { diff --git a/include/linux/pci.h b/include/linux/pci.h index 58cc2e2b05051..698a668828f66 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -50,7 +50,7 @@ PCI_STATUS_PARITY) /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ -#define PCI_NUM_RESET_METHODS 6 +#define PCI_NUM_RESET_METHODS 7 /* * The PCI interface treats multi-function devices as independent From patchwork Thu Jul 15 21:31:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 12381167 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B644C636C8 for ; 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Wysocki" , Sinan Kaya , "Amey Narkhede" , Shanker Donthineni Subject: [PATCH v11 8/8] PCI: Change the type of probe argument in reset functions Date: Thu, 15 Jul 2021 16:31:00 -0500 Message-ID: <20210715213100.11539-9-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210715213100.11539-1-sdonthineni@nvidia.com> References: <20210715213100.11539-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5be9149f-1bf0-452b-1215-08d947d80226 X-MS-TrafficTypeDiagnostic: BN8PR12MB3316: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7Mnm8O0A2Y2EOCnAFLUtGUO492xISHEZQjaer0+pY1QGx623ZivCJ8ZUXZJDXhzw9N1fYANxDSJw2YQ+gY7k8oIwZVnSSx62lcZ4reNbRZx6jlsROX0mQO/BDHlJ+/1221kCp0aJ03j7abtY5eN4e3CCTI2S+gAuS1s4+6WbhqD6pgEhxGK5wrRZAgP2kgsNFT+mEpYKSqqHp2zX72pzh8khF5RjiPRjveiBAr9danhmzW/rlGkJHb/+kvsI/8q3I4KHi81/wr1tzlm4xBREzf0qM5f27HqAcDredbG+nq/njeSDKMFedy+2QnByiFpmui3B4h8OjKnwBW9YymBuxT2bE+shBmc5OFTxkCk3Tsb2IbbkqGjpCj+v1SP4jAFiDs5064zZnskZsh6p6bcuaoHZ5vOs4lDtqqjVaSOTY0qq7fY9DHnZVTdu9a/QxPPyPFvnZvP/qytZAypZfYLL7T6mv+f+oFh95OZJ9UMCYjUpC3t3BWYpKH1pA6Mkvdantv34vRXZOmp0agbyQonOJxvn//xZrUJ2Lq1sOIJuFKg19Th9qRLUR8lLSZD0mHXqCCrQ7Pt2g6A+cBuR/E0XSXZgbqwDmOfrSVAcLXAKf292lMedBtEspOkXED7RVl0nB94YCw7/L0laPnE29PPZaVUV3Iqkqt/TzgZ+E92JiphwSnIDIrRmfAabEWiZZ3xAaOVhDDsQDEIzZSpFYipjBan7r69Z3KU8IJpHiSV6bSBj933GDgv005aKPkPutmOCXgdtY2wlxuhcGQgIhPS4SLlvZb1R8qEXOB16A1ie+x8t6XkwCoCKx8i978k/wK38 X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(346002)(376002)(136003)(39860400002)(396003)(46966006)(36840700001)(186003)(426003)(2906002)(316002)(82740400003)(54906003)(36756003)(2616005)(16526019)(6666004)(70206006)(34020700004)(82310400003)(66574015)(47076005)(86362001)(70586007)(26005)(336012)(7636003)(478600001)(36860700001)(30864003)(5660300002)(4326008)(107886003)(6916009)(356005)(966005)(8936002)(8676002)(1076003)(7696005)(83380400001)(36906005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2021 21:32:12.1554 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5be9149f-1bf0-452b-1215-08d947d80226 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3316 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Amey Narkhede Introduce a new enum pci_reset_mode_t to make the context of probe argument in reset functions clear and the code easier to read. Change the type of probe argument in functions which implement reset methods from int to pci_reset_mode_t to make the intent clear. Add a new line in return statement of pci_reset_bus_function(). Suggested-by: Alex Williamson Suggested-by: Krzysztof Wilczyński Signed-off-by: Amey Narkhede Reviewed-by: Alex Williamson --- drivers/crypto/cavium/nitrox/nitrox_main.c | 2 +- .../ethernet/cavium/liquidio/lio_vf_main.c | 2 +- drivers/pci/hotplug/pciehp.h | 2 +- drivers/pci/hotplug/pciehp_hpc.c | 4 +- drivers/pci/hotplug/pnv_php.c | 4 +- drivers/pci/pci-acpi.c | 10 ++- drivers/pci/pci-sysfs.c | 6 +- drivers/pci/pci.c | 85 ++++++++++++------- drivers/pci/pci.h | 12 +-- drivers/pci/pcie/aer.c | 2 +- drivers/pci/quirks.c | 37 ++++---- include/linux/pci.h | 8 +- include/linux/pci_hotplug.h | 2 +- 13 files changed, 107 insertions(+), 69 deletions(-) diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c index 2db3fd5815c82..6c61817996a33 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_main.c +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c @@ -306,7 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev) return -ENOMEM; } - pcie_reset_flr(pdev, 0); + pcie_reset_flr(pdev, PCI_RESET_DO_RESET); pci_restore_state(pdev); diff --git a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c index d185df5acea69..ac821c5532a4e 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_vf_main.c @@ -526,7 +526,7 @@ static void octeon_destroy_resources(struct octeon_device *oct) oct->irq_name_storage = NULL; } /* Soft reset the octeon device before exiting */ - if (!pcie_reset_flr(oct->pci_dev, 1)) + if (!pcie_reset_flr(oct->pci_dev, PCI_RESET_PROBE)) octeon_pci_flr(oct); else cn23xx_vf_ask_pf_to_do_flr(oct); diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index d4a930881054d..6c5de749ece82 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h @@ -184,7 +184,7 @@ void pciehp_release_ctrl(struct controller *ctrl); int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot); int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot); -int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe); +int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, pci_reset_mode_t mode); int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status); int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status); int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status); diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 9d06939736c0f..67fd7024a29aa 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -870,14 +870,14 @@ void pcie_disable_interrupt(struct controller *ctrl) * momentarily, if we see that they could interfere. Also, clear any spurious * events after. */ -int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe) +int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, pci_reset_mode_t mode) { struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 stat_mask = 0, ctrl_mask = 0; int rc; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; down_write(&ctrl->reset_lock); diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c index 04565162a4495..77df598c8deaf 100644 --- a/drivers/pci/hotplug/pnv_php.c +++ b/drivers/pci/hotplug/pnv_php.c @@ -526,7 +526,7 @@ static int pnv_php_enable(struct pnv_php_slot *php_slot, bool rescan) return 0; } -static int pnv_php_reset_slot(struct hotplug_slot *slot, int probe) +static int pnv_php_reset_slot(struct hotplug_slot *slot, pci_reset_mode_t mode) { struct pnv_php_slot *php_slot = to_pnv_php_slot(slot); struct pci_dev *bridge = php_slot->pdev; @@ -537,7 +537,7 @@ static int pnv_php_reset_slot(struct hotplug_slot *slot, int probe) * which don't have a bridge. Only claim to support * reset_slot() if we have a bridge device (for now...) */ - if (probe) + if (mode == PCI_RESET_PROBE) return !bridge; /* mask our interrupt while resetting the bridge */ diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 31f76746741f5..4cb84ce6829f7 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -944,16 +944,20 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) /** * pci_dev_acpi_reset - do a function level reset using _RST method * @dev: device to reset - * @probe: check if _RST method is included in the acpi_device context. + * @probe: If PCI_RESET_PROBE, check whether _RST method is included + * in the acpi_device context. */ -int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +int pci_dev_acpi_reset(struct pci_dev *dev, pci_reset_mode_t mode) { acpi_handle handle = ACPI_HANDLE(&dev->dev); + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 65791d8b07aa5..87dbe33fb149e 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1393,7 +1393,8 @@ static ssize_t reset_method_store(struct device *dev, for (i = 1; i < PCI_NUM_RESET_METHODS; i++) { if (sysfs_streq(name, pci_reset_fn_methods[i].name) && - !pci_reset_fn_methods[i].reset_fn(pdev, 1)) { + !pci_reset_fn_methods[i].reset_fn(pdev, + PCI_RESET_PROBE)) { reset_methods[n++] = i; break; } @@ -1405,7 +1406,8 @@ static ssize_t reset_method_store(struct device *dev, } } - if (!pci_reset_fn_methods[1].reset_fn(pdev, 1) && reset_methods[0] != 1) + if (!pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) && + reset_methods[0] != 1) pci_warn(pdev, "Device specific reset disabled/de-prioritized by user"); set_reset_methods: diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8aab4097f80bc..5a2452d0f1771 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4660,30 +4660,36 @@ EXPORT_SYMBOL_GPL(pcie_flr); /** * pcie_reset_flr - initiate a PCIe function level reset * @dev: device to reset - * @probe: If set, only check if the device can be reset this way. + * @mode: If PCI_RESET_PROBE, only check if the device can be reset this way. * * Initiate a function level reset on @dev. */ -int pcie_reset_flr(struct pci_dev *dev, int probe) +int pcie_reset_flr(struct pci_dev *dev, pci_reset_mode_t mode) { + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) return -ENOTTY; if (!dev->has_pcie_flr) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; return pcie_flr(dev); } EXPORT_SYMBOL_GPL(pcie_reset_flr); -static int pci_af_flr(struct pci_dev *dev, int probe) +static int pci_af_flr(struct pci_dev *dev, pci_reset_mode_t mode) { int pos; u8 cap; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + pos = pci_find_capability(dev, PCI_CAP_ID_AF); if (!pos) return -ENOTTY; @@ -4695,7 +4701,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe) if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* @@ -4726,7 +4732,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe) /** * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. * @dev: Device to reset. - * @probe: If set, only check if the device can be reset this way. + * @mode: If PCI_RESET_PROBE, only check if the device can be reset this way. * * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is * unset, it will be reinitialized internally when going from PCI_D3hot to @@ -4738,10 +4744,13 @@ static int pci_af_flr(struct pci_dev *dev, int probe) * by default (i.e. unless the @dev's d3hot_delay field has a different value). * Moreover, only devices in D0 can be reset by this function. */ -static int pci_pm_reset(struct pci_dev *dev, int probe) +static int pci_pm_reset(struct pci_dev *dev, pci_reset_mode_t mode) { u16 csr; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4749,7 +4758,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) if (csr & PCI_PM_CTRL_NO_SOFT_RESET) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; if (dev->current_state != PCI_D0) @@ -4998,10 +5007,13 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) } EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); -static int pci_parent_bus_reset(struct pci_dev *dev, int probe) +static int pci_parent_bus_reset(struct pci_dev *dev, pci_reset_mode_t mode) { struct pci_dev *pdev; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) return -ENOTTY; @@ -5010,44 +5022,47 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe) if (pdev != dev) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; return pci_bridge_secondary_bus_reset(dev->bus->self); } -static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) +static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, pci_reset_mode_t mode) { int rc = -ENOTTY; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!hotplug || !try_module_get(hotplug->owner)) return rc; if (hotplug->ops->reset_slot) - rc = hotplug->ops->reset_slot(hotplug, probe); + rc = hotplug->ops->reset_slot(hotplug, mode); module_put(hotplug->owner); return rc; } -static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) +static int pci_dev_reset_slot_function(struct pci_dev *dev, pci_reset_mode_t mode) { if (dev->multifunction || dev->subordinate || !dev->slot || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) return -ENOTTY; - return pci_reset_hotplug_slot(dev->slot->hotplug, probe); + return pci_reset_hotplug_slot(dev->slot->hotplug, mode); } -static int pci_reset_bus_function(struct pci_dev *dev, int probe) +static int pci_reset_bus_function(struct pci_dev *dev, pci_reset_mode_t mode) { int rc; - rc = pci_dev_reset_slot_function(dev, probe); + rc = pci_dev_reset_slot_function(dev, mode); if (rc != -ENOTTY) return rc; - return pci_parent_bus_reset(dev, probe); + return pci_parent_bus_reset(dev, mode); } static void pci_dev_lock(struct pci_dev *dev) @@ -5169,7 +5184,7 @@ int __pci_reset_function_locked(struct pci_dev *dev) * mechanisms might be broken on the device. */ for (i = 0; i < PCI_NUM_RESET_METHODS && (m = dev->reset_methods[i]); i++) { - rc = pci_reset_fn_methods[m].reset_fn(dev, 0); + rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET); if (!rc) return 0; if (rc != -ENOTTY) @@ -5204,7 +5219,7 @@ void pci_init_reset_methods(struct pci_dev *dev) might_sleep(); for (i = 1; i < PCI_NUM_RESET_METHODS; i++) { - rc = pci_reset_fn_methods[i].reset_fn(dev, 1); + rc = pci_reset_fn_methods[i].reset_fn(dev, PCI_RESET_PROBE); if (!rc) reset_methods[n++] = i; else if (rc != -ENOTTY) @@ -5521,21 +5536,24 @@ static void pci_slot_restore_locked(struct pci_slot *slot) } } -static int pci_slot_reset(struct pci_slot *slot, int probe) +static int pci_slot_reset(struct pci_slot *slot, pci_reset_mode_t mode) { int rc; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!slot || !pci_slot_resetable(slot)) return -ENOTTY; - if (!probe) + if (mode != PCI_RESET_PROBE) pci_slot_lock(slot); might_sleep(); - rc = pci_reset_hotplug_slot(slot->hotplug, probe); + rc = pci_reset_hotplug_slot(slot->hotplug, mode); - if (!probe) + if (mode != PCI_RESET_PROBE) pci_slot_unlock(slot); return rc; @@ -5549,7 +5567,7 @@ static int pci_slot_reset(struct pci_slot *slot, int probe) */ int pci_probe_reset_slot(struct pci_slot *slot) { - return pci_slot_reset(slot, 1); + return pci_slot_reset(slot, PCI_RESET_PROBE); } EXPORT_SYMBOL_GPL(pci_probe_reset_slot); @@ -5572,14 +5590,14 @@ static int __pci_reset_slot(struct pci_slot *slot) { int rc; - rc = pci_slot_reset(slot, 1); + rc = pci_slot_reset(slot, PCI_RESET_PROBE); if (rc) return rc; if (pci_slot_trylock(slot)) { pci_slot_save_and_disable_locked(slot); might_sleep(); - rc = pci_reset_hotplug_slot(slot->hotplug, 0); + rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); pci_slot_restore_locked(slot); pci_slot_unlock(slot); } else @@ -5588,14 +5606,17 @@ static int __pci_reset_slot(struct pci_slot *slot) return rc; } -static int pci_bus_reset(struct pci_bus *bus, int probe) +static int pci_bus_reset(struct pci_bus *bus, pci_reset_mode_t mode) { int ret; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + if (!bus->self || !pci_bus_resetable(bus)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; pci_bus_lock(bus); @@ -5634,14 +5655,14 @@ int pci_bus_error_reset(struct pci_dev *bridge) goto bus_reset; list_for_each_entry(slot, &bus->slots, list) - if (pci_slot_reset(slot, 0)) + if (pci_slot_reset(slot, PCI_RESET_DO_RESET)) goto bus_reset; mutex_unlock(&pci_slot_mutex); return 0; bus_reset: mutex_unlock(&pci_slot_mutex); - return pci_bus_reset(bridge->subordinate, 0); + return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); } /** @@ -5652,7 +5673,7 @@ int pci_bus_error_reset(struct pci_dev *bridge) */ int pci_probe_reset_bus(struct pci_bus *bus) { - return pci_bus_reset(bus, 1); + return pci_bus_reset(bus, PCI_RESET_PROBE); } EXPORT_SYMBOL_GPL(pci_probe_reset_bus); @@ -5666,7 +5687,7 @@ static int __pci_reset_bus(struct pci_bus *bus) { int rc; - rc = pci_bus_reset(bus, 1); + rc = pci_bus_reset(bus, PCI_RESET_PROBE); if (rc) return rc; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 699d14243867a..cc480c238db9c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -608,19 +608,19 @@ static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) struct pci_dev_reset_methods { u16 vendor; u16 device; - int (*reset)(struct pci_dev *dev, int probe); + int (*reset)(struct pci_dev *dev, pci_reset_mode_t mode); }; struct pci_reset_fn_method { - int (*reset_fn)(struct pci_dev *pdev, int probe); + int (*reset_fn)(struct pci_dev *pdev, pci_reset_mode_t mode); char *name; }; extern const struct pci_reset_fn_method pci_reset_fn_methods[]; #ifdef CONFIG_PCI_QUIRKS -int pci_dev_specific_reset(struct pci_dev *dev, int probe); +int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode); #else -static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) +static inline int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode) { return -ENOTTY; } @@ -709,9 +709,9 @@ static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL int pci_acpi_program_hp_params(struct pci_dev *dev); extern const struct attribute_group pci_dev_acpi_attr_group; void pci_set_acpi_fwnode(struct pci_dev *dev); -int pci_dev_acpi_reset(struct pci_dev *dev, int probe); +int pci_dev_acpi_reset(struct pci_dev *dev, pci_reset_mode_t mode); #else -static inline int pci_dev_acpi_reset(struct pci_dev *dev, int probe) +static inline int pci_dev_acpi_reset(struct pci_dev *dev, pci_reset_mode_t mode) { return -ENOTTY; } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 031379deb1304..9784fdcf30061 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1407,7 +1407,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) } if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { - rc = pcie_reset_flr(dev, 0); + rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET); if (!rc) pci_info(dev, "has been reset\n"); else diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index f43883a2e33df..b230bd07a0295 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3702,7 +3702,7 @@ DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, * reset a single function if other methods (e.g. FLR, PM D0->D3) are * not available. */ -static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) +static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, pci_reset_mode_t mode) { /* * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf @@ -3712,7 +3712,7 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) * Thus we must call pcie_flr() directly without first checking if it is * supported. */ - if (!probe) + if (mode == PCI_RESET_DO_RESET) pcie_flr(dev); return 0; } @@ -3724,13 +3724,13 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) #define NSDE_PWR_STATE 0xd0100 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ -static int reset_ivb_igd(struct pci_dev *dev, int probe) +static int reset_ivb_igd(struct pci_dev *dev, pci_reset_mode_t mode) { void __iomem *mmio_base; unsigned long timeout; u32 val; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; mmio_base = pci_iomap(dev, 0, 0); @@ -3767,7 +3767,7 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe) } /* Device-specific reset method for Chelsio T4-based adapters */ -static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) +static int reset_chelsio_generic_dev(struct pci_dev *dev, pci_reset_mode_t mode) { u16 old_command; u16 msix_flags; @@ -3783,7 +3783,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) * If this is the "probe" phase, return 0 indicating that we can * reset this device. */ - if (probe) + if (mode == PCI_RESET_PROBE) return 0; /* @@ -3845,17 +3845,17 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) * Chapter 3: NVMe control registers * Chapter 7.3: Reset behavior */ -static int nvme_disable_and_flr(struct pci_dev *dev, int probe) +static int nvme_disable_and_flr(struct pci_dev *dev, pci_reset_mode_t mode) { void __iomem *bar; u16 cmd; u32 cfg; if (dev->class != PCI_CLASS_STORAGE_EXPRESS || - pcie_reset_flr(dev, 1) || !pci_resource_start(dev, 0)) + pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) return -ENOTTY; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); @@ -3919,11 +3919,13 @@ static int nvme_disable_and_flr(struct pci_dev *dev, int probe) * device too soon after FLR. A 250ms delay after FLR has heuristically * proven to produce reliably working results for device assignment cases. */ -static int delay_250ms_after_flr(struct pci_dev *dev, int probe) +static int delay_250ms_after_flr(struct pci_dev *dev, pci_reset_mode_t mode) { - int ret = pcie_reset_flr(dev, probe); + int ret; + + ret = pcie_reset_flr(dev, mode); - if (probe) + if (ret || mode == PCI_RESET_PROBE) return ret; msleep(250); @@ -3939,13 +3941,13 @@ static int delay_250ms_after_flr(struct pci_dev *dev, int probe) #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ -static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe) +static int reset_hinic_vf_dev(struct pci_dev *pdev, pci_reset_mode_t mode) { unsigned long timeout; void __iomem *bar; u32 val; - if (probe) + if (mode == PCI_RESET_PROBE) return 0; bar = pci_iomap(pdev, 0, 0); @@ -4016,16 +4018,19 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { * because when a host assigns a device to a guest VM, the host may need * to reset the device but probably doesn't have a driver for it. */ -int pci_dev_specific_reset(struct pci_dev *dev, int probe) +int pci_dev_specific_reset(struct pci_dev *dev, pci_reset_mode_t mode) { const struct pci_dev_reset_methods *i; + if (mode >= PCI_RESET_MODE_MAX) + return -EINVAL; + for (i = pci_dev_reset_methods; i->reset; i++) { if ((i->vendor == dev->vendor || i->vendor == (u16)PCI_ANY_ID) && (i->device == dev->device || i->device == (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return i->reset(dev, mode); } return -ENOTTY; diff --git a/include/linux/pci.h b/include/linux/pci.h index 698a668828f66..e6f34fbd19332 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -52,6 +52,12 @@ /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ #define PCI_NUM_RESET_METHODS 7 +typedef enum pci_reset_mode { + PCI_RESET_DO_RESET, + PCI_RESET_PROBE, + PCI_RESET_MODE_MAX, +} pci_reset_mode_t; + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -1235,7 +1241,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); void pcie_print_link_status(struct pci_dev *dev); -int pcie_reset_flr(struct pci_dev *dev, int probe); +int pcie_reset_flr(struct pci_dev *dev, pci_reset_mode_t mode); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index 2dac431d94ac1..75e4e13887d0b 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -44,7 +44,7 @@ struct hotplug_slot_ops { int (*get_attention_status) (struct hotplug_slot *slot, u8 *value); int (*get_latch_status) (struct hotplug_slot *slot, u8 *value); int (*get_adapter_status) (struct hotplug_slot *slot, u8 *value); - int (*reset_slot) (struct hotplug_slot *slot, int probe); + int (*reset_slot) (struct hotplug_slot *slot, pci_reset_mode_t mode); }; /**