From patchwork Sat Jul 17 23:48:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 12384113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4374AC636C9 for ; Sat, 17 Jul 2021 23:49:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0BBBF61108 for ; Sat, 17 Jul 2021 23:49:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0BBBF61108 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=googlemail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OmnfvhPsNtZxhcI95XMevRcYYCm3IFIQZpiKxEffs34=; b=XEA1ebcF5k1bOH YHQ+tQd2Xkyby93SDnKuw+7C8Q3Sfm2oWc1X8ciJB/18+KEGIyeXgNui+P59YQHmwo7gVHg3U2d6O ak/L2HA00FtgWO385fq9zGP4Y8CVExzUQ3LPcAAAtzv8GrIccpycll6WT+LzXwI3E0UrEoWrH07Ck YuANm0Kv2TYn09x0BgvMXtYLvsOFftaA7Kn6le6IyV+Kw6Yu0hUXQa2bI4gO92FtjjC1tVb8iLxZ6 I8kJKjjLAX5dQw7oPuholTjK4i0uoATTLn+mbUUQUynUitEYs2hFWX4oATZ0gQp2DYpxDIn4bmHQ6 zJmrXde4AUBXlWsaFZrw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m4u3h-007BZV-Fk; Sat, 17 Jul 2021 23:49:25 +0000 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m4u3T-007BW9-7d; Sat, 17 Jul 2021 23:49:12 +0000 Received: by mail-wr1-x431.google.com with SMTP id d12so16493094wre.13; Sat, 17 Jul 2021 16:49:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bT1+fPwFJ9flWJpalc9w5DJNPuQ3S3336QWUFAF7Nzg=; b=MX4ao7FsMDbMFDHM0HBg1o5Vka3eWBtFWTATqUoGK7Tv01xDX8zaRsuG9sr3csWNQo r3GjNQWjHEO1M7/GR+vU8rBy9gCAH/4ae9BJLARD8QqSh4wQXry7JJBsthQ7hazbFhrt moUU/AvbYyYg9cig+IAIUwKsALiQ5chduykZ4r0bO2u3JED9utY95Uimj2Qll2Li6rPs bv+3MoRQkFnRUCYErJguo5lA6AjhcLL7AV1nPdG0Xi0JzeJDflFn01x34Ih3ILjsMWz/ xEBMDU6H6gjC52h2ujbqPtR1vaMJwOmtIpyrkGcFdofeA5fHdSTjYPoHKbT8FRXn3nqb KVcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bT1+fPwFJ9flWJpalc9w5DJNPuQ3S3336QWUFAF7Nzg=; b=HzTxx+78q0kldZ78twlc/bqx/J871dJBH7TWwYmXID4EwuHQBQ7WNxuDWHDv0az/x3 0kkPHAvME2wfcegii8A1BC26D/xn+pXTxASSkJGj4KxX0HMMdrzCNKDgG7x0q4MQaC18 /5dgTeKtxNBhMODgYrT6GFkH2oZjJVFqV14XxR8u4gU6nPLw9b59E/C1NbFjY2JAWOtB CXSpqPkbTJ3ZClCzHvVDjm5WVOk7QU7FhxceGt5Ib4tGyfS78k0P7WpOFVTYkszufDY3 ZUCpYZOKB0vBqS6geYxkjJXcL/vxu6798wCARqdRTBRuretwj5E07EiGAqMOdKIarWXA 2afQ== X-Gm-Message-State: AOAM531ORUDWFBTIguz4+b0bnih3nL7h4+ZJp2c/nrLkjbYKDDHDJHFO 7gQvN4CNmTd2SOgrZy6pu2g= X-Google-Smtp-Source: ABdhPJx7hpMPMGYC00iF95XI7OMBCypMiepPby1ZWDAXHuBTefApnReU1/cPQgrg0n0cffiS4Nq14w== X-Received: by 2002:a5d:64aa:: with SMTP id m10mr21395971wrp.351.1626565749759; Sat, 17 Jul 2021 16:49:09 -0700 (PDT) Received: from localhost.localdomain (dynamic-2a01-0c22-7602-4e00-f22f-74ff-fe21-0725.c22.pool.telefonica.de. [2a01:c22:7602:4e00:f22f:74ff:fe21:725]) by smtp.googlemail.com with ESMTPSA id p11sm14505044wro.78.2021.07.17.16.49.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 16:49:09 -0700 (PDT) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org, bjorn.andersson@linaro.org, ohad@wizery.com, Martin Blumenstingl , Rob Herring Subject: [PATCH v3 1/2] dt-bindings: remoteproc: Add the documentation for Meson AO ARC rproc Date: Sun, 18 Jul 2021 01:48:58 +0200 Message-Id: <20210717234859.351911-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717234859.351911-1-martin.blumenstingl@googlemail.com> References: <20210717234859.351911-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210717_164911_318384_D77B0097 X-CRM114-Status: GOOD ( 15.78 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4 controller for always-on operations, typically used for managing system suspend. Reviewed-by: Rob Herring Signed-off-by: Martin Blumenstingl --- .../remoteproc/amlogic,meson-mx-ao-arc.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml new file mode 100644 index 000000000000..d892d29a656b --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/remoteproc/amlogic,meson-mx-ao-arc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson AO ARC Remote Processor bindings + +description: + Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC core + controller for always-on operations, typically used for managing + system suspend. Meson6 and older use a ARC core based on the ARCv1 + ISA, while Meson8, Meson8b and Meson8m2 use an ARC EM4 (ARCv2 ISA) + core. + +maintainers: + - Martin Blumenstingl + +properties: + compatible: + items: + - enum: + - amlogic,meson8-ao-arc + - amlogic,meson8b-ao-arc + - const: amlogic,meson-mx-ao-arc + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + The name of the firmware which should be loaded for this remote + processor. + + reg: + description: + Address ranges of the remap and CPU control addresses for the + remote processor. + minItems: 2 + + reg-names: + items: + - const: remap + - const: cpu + + resets: + minItems: 1 + + clocks: + minItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandles to a reserved SRAM region which is used as the memory of + the ARC core. The region should be defined as child nodes of the + AHB SRAM node as per the generic bindings in + Documentation/devicetree/bindings/sram/sram.yaml + + amlogic,secbus2: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the SECBUS2 region which contains some configuration + bits of this remote processor + +required: + - compatible + - reg + - reg-names + - resets + - clocks + - sram + - amlogic,secbus2 + +additionalProperties: false + +examples: + - | + remoteproc@1c { + compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; + reg = <0x1c 0x8>, <0x38 0x8>; + reg-names = "remap", "cpu"; + resets = <&media_cpu_reset>; + clocks = <&media_cpu_clock>; + sram = <&ahb_sram_ao_arc>; + amlogic,secbus2 = <&secbus2>; + }; + +... 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[2a01:c22:7602:4e00:f22f:74ff:fe21:725]) by smtp.googlemail.com with ESMTPSA id p11sm14505044wro.78.2021.07.17.16.49.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 16:49:10 -0700 (PDT) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org, bjorn.andersson@linaro.org, ohad@wizery.com, Martin Blumenstingl Subject: [PATCH v3 2/2] remoteproc: meson-mx-ao-arc: Add a driver for the AO ARC remote procesor Date: Sun, 18 Jul 2021 01:48:59 +0200 Message-Id: <20210717234859.351911-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717234859.351911-1-martin.blumenstingl@googlemail.com> References: <20210717234859.351911-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210717_164912_194655_EF30A363 X-CRM114-Status: GOOD ( 31.28 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Amlogic Meson6, Meson8, Meson8b and Meson8m2 embed an ARC core in the Always-On (AO) power-domain. This is typically used for waking up the ARM cores after system suspend. The configuration is spread across three different registers: - AO_REMAP_REG0 which must be programmed to zero, it's actual purpose is unknown. There is a second remap register which is not used in the vendor kernel (which served as reference for this driver). - AO_CPU_CNTL is used to start and stop the ARC core. - AO_SECURE_REG0 in the SECBUS2 register area with unknown purpose. To boot the ARC core we also need to enable it's gate clock and trigger a reset. The actual code for this ARC core can come from an ELF binary, for example by building the Zephyr RTOS for an ARC EM4 core and then taking "zephyr.elf" as firmware. This executable does not have any "rsc table" so we are skipping rproc_elf_load_rsc_table (rproc_ops.parse_fw) and rproc_elf_find_loaded_rsc_table (rproc_ops.find_loaded_rsc_table). Signed-off-by: Martin Blumenstingl Reviewed-by: Mathieu Poirier --- drivers/remoteproc/Kconfig | 11 ++ drivers/remoteproc/Makefile | 1 + drivers/remoteproc/meson_mx_ao_arc.c | 260 +++++++++++++++++++++++++++ 3 files changed, 272 insertions(+) create mode 100644 drivers/remoteproc/meson_mx_ao_arc.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 9a6eedc3994a..3197bbe38785 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -127,6 +127,17 @@ config KEYSTONE_REMOTEPROC It's safe to say N here if you're not interested in the Keystone DSPs or just want to use a bare minimum kernel. +config MESON_MX_AO_ARC_REMOTEPROC + tristate "Amlogic Meson6/8/8b/8m2 AO ARC remote processor support" + depends on HAS_IOMEM + depends on (ARM && ARCH_MESON) || COMPILE_TEST + select GENERIC_ALLOCATOR + help + Say m or y here to have support for the AO ARC remote processor + on Amlogic Meson6/Meson8/Meson8b/Meson8m2 SoCs. This is + typically used for system suspend. + If unusre say N. + config PRU_REMOTEPROC tristate "TI PRU remoteproc support" depends on TI_PRUSS diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index bb26c9e4ef9c..ce1abeb30907 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_OMAP_REMOTEPROC) += omap_remoteproc.o obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o +obj-$(CONFIG_MESON_MX_AO_ARC_REMOTEPROC)+= meson_mx_ao_arc.o obj-$(CONFIG_PRU_REMOTEPROC) += pru_rproc.o obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o diff --git a/drivers/remoteproc/meson_mx_ao_arc.c b/drivers/remoteproc/meson_mx_ao_arc.c new file mode 100644 index 000000000000..86c0f3e48701 --- /dev/null +++ b/drivers/remoteproc/meson_mx_ao_arc.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020 Martin Blumenstingl + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "remoteproc_internal.h" + +#define AO_REMAP_REG0 0x0 +#define AO_REMAP_REG0_REMAP_AHB_SRAM_BITS_17_14_FOR_ARM_CPU GENMASK(3, 0) + +#define AO_REMAP_REG1 0x4 +#define AO_REMAP_REG1_MOVE_AHB_SRAM_TO_0X0_INSTEAD_OF_DDR BIT(4) +#define AO_REMAP_REG1_REMAP_AHB_SRAM_BITS_17_14_FOR_MEDIA_CPU GENMASK(3, 0) + +#define AO_CPU_CNTL 0x0 +#define AO_CPU_CNTL_AHB_SRAM_BITS_31_20 GENMASK(28, 16) +#define AO_CPU_CNTL_HALT BIT(9) +#define AO_CPU_CNTL_UNKNONWN BIT(8) +#define AO_CPU_CNTL_RUN BIT(0) + +#define AO_CPU_STAT 0x4 + +#define AO_SECURE_REG0 0x0 +#define AO_SECURE_REG0_AHB_SRAM_BITS_19_12 GENMASK(15, 8) + +/* Only bits [31:20] and [17:14] are usable, all other bits must be zero */ +#define MESON_AO_RPROC_SRAM_USABLE_BITS 0xfff3c000 + +#define MESON_AO_RPROC_MEMORY_OFFSET 0x10000000 + +struct meson_mx_ao_arc_rproc_priv { + void __iomem *remap_base; + void __iomem *cpu_base; + unsigned long sram_va; + phys_addr_t sram_pa; + size_t sram_size; + struct gen_pool *sram_pool; + struct reset_control *arc_reset; + struct clk *arc_pclk; + struct regmap *secbus2_regmap; +}; + +static int meson_mx_ao_arc_rproc_start(struct rproc *rproc) +{ + struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv; + phys_addr_t translated_sram_addr; + int ret; + + ret = clk_prepare_enable(priv->arc_pclk); + if (ret) + return ret; + + writel(FIELD_PREP(AO_REMAP_REG0_REMAP_AHB_SRAM_BITS_17_14_FOR_ARM_CPU, + priv->sram_pa >> 14), + priv->remap_base + AO_REMAP_REG0); + + /* + * The SRAM content as seen by the ARC core always starts at 0x0 + * regardless of the value given here (this was discovered by trial and + * error). For SoCs older than Meson6 we probably have to set + * AO_REMAP_REG1_MOVE_AHB_SRAM_TO_0X0_INSTEAD_OF_DDR to achieve the + * same. (At least) For Meson8 and newer that bit must not be set. + */ + writel(0x0, priv->remap_base + AO_REMAP_REG1); + + regmap_update_bits(priv->secbus2_regmap, AO_SECURE_REG0, + AO_SECURE_REG0_AHB_SRAM_BITS_19_12, + FIELD_PREP(AO_SECURE_REG0_AHB_SRAM_BITS_19_12, + priv->sram_pa >> 12)); + + ret = reset_control_reset(priv->arc_reset); + if (ret) { + clk_disable_unprepare(priv->arc_pclk); + return ret; + } + + usleep_range(10, 100); + + /* + * Convert from 0xd9000000 to 0xc9000000 as the vendor driver does. + * This only seems to be relevant for the AO_CPU_CNTL register. It is + * unknown why this is needed. + */ + translated_sram_addr = priv->sram_pa - MESON_AO_RPROC_MEMORY_OFFSET; + + writel(FIELD_PREP(AO_CPU_CNTL_AHB_SRAM_BITS_31_20, + translated_sram_addr >> 20) | + AO_CPU_CNTL_UNKNONWN | + AO_CPU_CNTL_RUN, + priv->cpu_base + AO_CPU_CNTL); + usleep_range(20, 200); + + return 0; +} + +static int meson_mx_ao_arc_rproc_stop(struct rproc *rproc) +{ + struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv; + + writel(AO_CPU_CNTL_HALT, priv->cpu_base + AO_CPU_CNTL); + + clk_disable_unprepare(priv->arc_pclk); + + return 0; +} + +static void *meson_mx_ao_arc_rproc_da_to_va(struct rproc *rproc, u64 da, + size_t len, bool *is_iomem) +{ + struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv; + + if ((da + len) > priv->sram_size) + return NULL; + + return (void *)priv->sram_va + da; +} + +static struct rproc_ops meson_mx_ao_arc_rproc_ops = { + .start = meson_mx_ao_arc_rproc_start, + .stop = meson_mx_ao_arc_rproc_stop, + .da_to_va = meson_mx_ao_arc_rproc_da_to_va, + .get_boot_addr = rproc_elf_get_boot_addr, + .load = rproc_elf_load_segments, + .sanity_check = rproc_elf_sanity_check, +}; + +static int meson_mx_ao_arc_rproc_probe(struct platform_device *pdev) +{ + struct meson_mx_ao_arc_rproc_priv *priv; + struct device *dev = &pdev->dev; + const char *fw_name = NULL; + struct rproc *rproc; + int ret; + + device_property_read_string(dev, "firmware-name", &fw_name); + + rproc = devm_rproc_alloc(dev, "meson-mx-ao-arc", + &meson_mx_ao_arc_rproc_ops, fw_name, + sizeof(*priv)); + if (!rproc) + return -ENOMEM; + + rproc->has_iommu = false; + priv = rproc->priv; + + priv->sram_pool = of_gen_pool_get(dev->of_node, "sram", 0); + if (!priv->sram_pool) { + dev_err(dev, "Could not get SRAM pool\n"); + return -ENODEV; + } + + priv->sram_size = gen_pool_avail(priv->sram_pool); + + priv->sram_va = gen_pool_alloc(priv->sram_pool, priv->sram_size); + if (!priv->sram_va) { + dev_err(dev, "Could not alloc memory in SRAM pool\n"); + return -ENOMEM; + } + + priv->sram_pa = gen_pool_virt_to_phys(priv->sram_pool, priv->sram_va); + if (priv->sram_pa & ~MESON_AO_RPROC_SRAM_USABLE_BITS) { + dev_err(dev, "SRAM address contains unusable bits\n"); + ret = -EINVAL; + goto err_free_genpool; + } + + priv->secbus2_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "amlogic,secbus2"); + if (IS_ERR(priv->secbus2_regmap)) { + dev_err(dev, "Failed to find SECBUS2 regmap\n"); + ret = PTR_ERR(priv->secbus2_regmap); + goto err_free_genpool; + } + + priv->remap_base = devm_platform_ioremap_resource_byname(pdev, "remap"); + if (IS_ERR(priv->remap_base)) { + ret = PTR_ERR(priv->remap_base); + goto err_free_genpool; + } + + priv->cpu_base = devm_platform_ioremap_resource_byname(pdev, "cpu"); + if (IS_ERR(priv->cpu_base)) { + ret = PTR_ERR(priv->cpu_base); + goto err_free_genpool; + } + + priv->arc_reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(priv->arc_reset)) { + dev_err(dev, "Failed to get ARC reset\n"); + ret = PTR_ERR(priv->arc_reset); + goto err_free_genpool; + } + + priv->arc_pclk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->arc_pclk)) { + dev_err(dev, "Failed to get the ARC PCLK\n"); + ret = PTR_ERR(priv->arc_pclk); + goto err_free_genpool; + } + + platform_set_drvdata(pdev, rproc); + + ret = rproc_add(rproc); + if (ret) + goto err_free_genpool; + + return 0; + +err_free_genpool: + gen_pool_free(priv->sram_pool, priv->sram_va, priv->sram_size); + return ret; +} + +static int meson_mx_ao_arc_rproc_remove(struct platform_device *pdev) +{ + struct rproc *rproc = platform_get_drvdata(pdev); + struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv; + + rproc_del(rproc); + gen_pool_free(priv->sram_pool, priv->sram_va, priv->sram_size); + + return 0; +} + +static const struct of_device_id meson_mx_ao_arc_rproc_match[] = { + { .compatible = "amlogic,meson8-ao-arc" }, + { .compatible = "amlogic,meson8b-ao-arc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, meson_mx_ao_arc_rproc_match); + +static struct platform_driver meson_mx_ao_arc_rproc_driver = { + .probe = meson_mx_ao_arc_rproc_probe, + .remove = meson_mx_ao_arc_rproc_remove, + .driver = { + .name = "meson-mx-ao-arc-rproc", + .of_match_table = meson_mx_ao_arc_rproc_match, + }, +}; +module_platform_driver(meson_mx_ao_arc_rproc_driver); + +MODULE_DESCRIPTION("Amlogic Meson6/8/8b/8m2 AO ARC remote processor driver"); +MODULE_AUTHOR("Martin Blumenstingl "); +MODULE_LICENSE("GPL v2");